diff --git a/os/hal/ports/STM32/STM32L1xx/adc_lld.c b/os/hal/ports/STM32/STM32L1xx/adc_lld.c
index 424d5cf1f..ad7700fb6 100644
--- a/os/hal/ports/STM32/STM32L1xx/adc_lld.c
+++ b/os/hal/ports/STM32/STM32L1xx/adc_lld.c
@@ -159,6 +159,8 @@ void adc_lld_start(ADCDriver *adcp) {
     }
 #endif /* STM32_ADC_USE_ADC1 */
 
+    ADC->CCR = (ADC->CCR & ADC_CCR_TSVREFE) | (STM32_ADC_ADCPRE << 16);
+
     /* ADC initial setup, starting the analog part here in order to reduce
        the latency when starting a conversion.*/
     adcp->adc->CR1 = 0;
diff --git a/os/hal/ports/STM32/STM32L1xx/adc_lld.h b/os/hal/ports/STM32/STM32L1xx/adc_lld.h
index aa8e1ddef..758cd918d 100644
--- a/os/hal/ports/STM32/STM32L1xx/adc_lld.h
+++ b/os/hal/ports/STM32/STM32L1xx/adc_lld.h
@@ -175,6 +175,20 @@
 #define STM32_DMA_REQUIRED
 #endif
 
+/**
+ *  * @brief   ADC frequency.
+ *   */
+/* ADC clock related settings and checks.*/
+#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV1
+#define STM32_ADCCLK                        STM32_HSICLK
+#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
+#define STM32_ADCCLK                        (STM32_HSICLK / 2)
+#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
+#define STM32_ADCCLK                        (STM32_HSICLK / 4)
+#else
+#error "invalid STM32_ADC_ADCPRE value specified"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/os/hal/ports/STM32/STM32L1xx/hal_lld.h
index e952e302f..00e52892d 100644
--- a/os/hal/ports/STM32/STM32L1xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.h
@@ -770,11 +770,6 @@
 #error "invalid STM32_RTCSEL value specified"
 #endif
 
-/**
- * @brief   ADC frequency.
- */
-#define STM32_ADCCLK                STM32_HSICLK
-
 /**
  * @brief   USB frequency.
  */