andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.2.x@2824 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2011-03-18 13:54:23 +00:00
parent c413e450e1
commit aa6802f223
6 changed files with 56 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
os/ports/IAR/ARMCMx/chcore_v6m.c
View File

@ -34,11 +34,6 @@
#include "ch.h"
/**
* @brief PC register temporary storage.
*/
regarm_t _port_saved_pc;
/**
* @brief System Timer vector.
* @details This interrupt is used as system tick.

22
os/ports/IAR/ARMCMx/chcore_v6m.h
View File

@ -39,10 +39,8 @@
/* Port implementation part. */
/*===========================================================================*/
/**
* @brief Cortex-Mx exception context.
*/
struct cmxctx {
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
regarm_t r1;
regarm_t r2;
@ -53,18 +51,6 @@ struct cmxctx {
regarm_t xpsr;
};
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t xpsr;
regarm_t r12;
regarm_t lr;
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
regarm_t pc;
};
struct intctx {
regarm_t r8;
regarm_t r9;
@ -238,10 +224,6 @@ struct intctx {
}
#endif
#if !defined(__DOXYGEN__)
extern regarm_t _port_saved_pc;
#endif
#ifdef __cplusplus
extern "C" {
#endif

50
os/ports/IAR/ARMCMx/chcoreasm_v6m.s
View File

@ -37,16 +37,15 @@
#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
EXTCTX_SIZE SET 32
CONTEXT_OFFSET SET 12
EXTCTX_SIZE SET 32
CONTEXT_OFFSET SET 12
SCB_ICSR SET 0xE000ED04
SECTION .text:CODE:NOROOT(2)
EXTERN chThdExit
EXTERN chSchIsRescRequiredExI
EXTERN chSchDoRescheduleI
EXTERN _port_saved_pc
EXTERN _port_irq_nesting
THUMB
@ -83,29 +82,32 @@ _port_thread_start:
blx r4
bl chThdExit
/*
* NMI vector.
* The NMI vector is used for exception mode re-entering after a context
* switch.
*/
PUBLIC NMIVector
NMIVector:
mrs r3, PSP
adds r3, r3, #32
msr PSP, r3
cpsie i
bx lr
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
PUBLIC _port_switch_from_isr
_port_switch_from_isr:
/* Note, saves r4 to make space for the PC.*/
push {r0, r1, r2, r3, r4}
mrs r0, APSR
mov r1, r12
push {r0, r1, lr}
ldr r0, =_port_saved_pc
ldr r0, [r0]
adds r0, r0, #1
str r0, [sp, #28]
bl chSchDoRescheduleI
pop {r0, r1, r2}
mov r12, r1
msr APSR, r0
mov lr, r2
pop {r0, r1, r2, r3}
cpsie i
pop {pc}
movs r3, #128
lsls r3, r3, #24
ldr r2, =SCB_ICSR
str r3, [r2, #0]
_waitnmi:
b _waitnmi
/*
* Reschedule verification and setup after an IRQ.
@ -124,11 +126,13 @@ stillnested
pop {r3, pc}
doresch
mrs r3, PSP
ldr r2, =_port_saved_pc
ldr r1, [r3, #24]
str r1, [r2]
subs r3, r3, #32
msr PSP, r3
ldr r2, =_port_switch_from_isr
str r2, [r3, #24]
movs r2, #128
lsls r2, r2, #17
str r2, [r3, #28]
pop {r3, pc}
END

5
os/ports/RVCT/ARMCMx/chcore_v6m.c
View File

@ -34,11 +34,6 @@
#include "ch.h"
/**
* @brief PC register temporary storage.
*/
regarm_t _port_saved_pc;
/**
* @brief System Timer vector.
* @details This interrupt is used as system tick.

22
os/ports/RVCT/ARMCMx/chcore_v6m.h
View File

@ -39,10 +39,8 @@
/* Port implementation part. */
/*===========================================================================*/
/**
* @brief Cortex-Mx exception context.
*/
struct cmxctx {
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t r0;
regarm_t r1;
regarm_t r2;
@ -53,18 +51,6 @@ struct cmxctx {
regarm_t xpsr;
};
#if !defined(__DOXYGEN__)
struct extctx {
regarm_t xpsr;
regarm_t r12;
regarm_t lr;
regarm_t r0;
regarm_t r1;
regarm_t r2;
regarm_t r3;
regarm_t pc;
};
struct intctx {
regarm_t r8;
regarm_t r9;
@ -230,10 +216,6 @@ struct intctx {
*/
#define port_switch(ntp, otp) _port_switch(ntp, otp)
#if !defined(__DOXYGEN__)
extern regarm_t _port_saved_pc;
#endif
#ifdef __cplusplus
extern "C" {
#endif

45
os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
View File

@ -34,6 +34,7 @@
EXTCTX_SIZE EQU 32
CONTEXT_OFFSET EQU 12
SCB_ICSR EQU 0xE000ED04
PRESERVE8
THUMB
@ -42,7 +43,6 @@ CONTEXT_OFFSET EQU 12
IMPORT chThdExit
IMPORT chSchIsRescRequiredExI
IMPORT chSchDoRescheduleI
IMPORT _port_saved_pc
/*
* Performs a context switch between two threads.
@ -79,29 +79,32 @@ _port_thread_start PROC
bl chThdExit
ENDP
/*
* NMI vector.
* The NMI vector is used for exception mode re-entering after a context
* switch.
*/
EXPORT NMIVector
NMIVector PROC
mrs r3, PSP
adds r3, r3, #32
msr PSP, r3
cpsie i
bx lr
ENDP
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
EXPORT _port_switch_from_isr
_port_switch_from_isr PROC
/* Note, saves r4 to make space for the PC.*/
push {r0, r1, r2, r3, r4}
mrs r0, APSR
mov r1, r12
push {r0, r1, lr}
ldr r0, =_port_saved_pc
ldr r0, [r0]
adds r0, r0, #1
str r0, [sp, #28]
bl chSchDoRescheduleI
pop {r0, r1, r2}
mov r12, r1
msr APSR, r0
mov lr, r2
pop {r0, r1, r2, r3}
cpsie i
pop {pc}
movs r3, #128
lsls r3, r3, #24
ldr r2, =SCB_ICSR
str r3, [r2, #0]
_waitnmi b _waitnmi
ENDP
/*
@ -121,11 +124,13 @@ stillnested
pop {r3, pc}
doresch
mrs r3, PSP
ldr r2, =_port_saved_pc
ldr r1, [r3, #24]
str r1, [r2]
subs r3, r3, #32
msr PSP, r3
ldr r2, =_port_switch_from_isr
str r2, [r3, #24]
movs r2, #128
lsls r2, r2, #17
str r2, [r3, #28]
pop {r3, pc}
ENDP