git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6188 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
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@ -368,7 +368,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
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#define CH_DBG_SYSTEM_STATE_CHECK TRUE
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#define CH_DBG_SYSTEM_STATE_CHECK FALSE
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#endif
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/**
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@ -379,7 +379,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_CHECKS TRUE
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#define CH_DBG_ENABLE_CHECKS FALSE
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#endif
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/**
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@ -391,7 +391,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_ASSERTS TRUE
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#define CH_DBG_ENABLE_ASSERTS FALSE
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#endif
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/**
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@ -402,7 +402,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_TRACE TRUE
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#define CH_DBG_ENABLE_TRACE FALSE
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#endif
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/**
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@ -416,7 +416,7 @@
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* @p panic_msg variable set to @p NULL.
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*/
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#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
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#define CH_DBG_ENABLE_STACK_CHECK TRUE
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#define CH_DBG_ENABLE_STACK_CHECK FALSE
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#endif
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/**
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@ -428,7 +428,7 @@
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* @note The default is @p FALSE.
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*/
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#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
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#define CH_DBG_FILL_THREADS TRUE
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#define CH_DBG_FILL_THREADS FALSE
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#endif
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/**
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@ -30,13 +30,6 @@
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#include "mcuconf.h"
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/**
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* @brief Enables the TM subsystem.
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*/
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#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
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#define HAL_USE_TM FALSE
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#endif
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/**
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* @brief Enables the PAL subsystem.
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*/
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@ -89,11 +89,12 @@
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*/
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#define STM32_I2C_USE_I2C1 FALSE
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#define STM32_I2C_USE_I2C2 FALSE
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_IRQ_PRIORITY 10
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#define STM32_I2C_I2C2_IRQ_PRIORITY 10
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt()
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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@ -133,7 +134,7 @@
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#define STM32_SPI_SPI1_IRQ_PRIORITY 2
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#define STM32_SPI_SPI2_IRQ_PRIORITY 2
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#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* UART driver system settings.
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@ -144,4 +145,5 @@
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#define STM32_UART_USART2_IRQ_PRIORITY 3
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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@ -132,14 +132,6 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* TODO: Move the following DMA settings in the STM32F0XX registry.*/
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#if defined(STM32F0XX)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif
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/* TODO: Move the following DMA settings in the STM32F37X registry.*/
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#if defined(STM32F37X)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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@ -124,15 +124,6 @@
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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#endif
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/* TODO: Move the following DMA settings in the STM32F0XX registry.*/
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#if defined(STM32F0XX)
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/* Fixed values for STM32F0xx devices.*/
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#endif /* defined(STM32F0XX) */
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/* TODO: Move the following DMA settings in the STM32F37X registry.*/
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#if defined(STM32F37X)
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/* Fixed values for STM32F3xx devices.*/
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@ -126,14 +126,6 @@
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#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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#endif
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#if defined(STM32F0XX)
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/* Fixed values for STM32F0xx devices.*/
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif /* defined(STM32F0XX) */
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#if defined(STM32F37X)
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/* Fixed values for STM32F3xx devices.*/
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/*===========================================================================*/
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rccResetAPB1(0xFFFFFFFF);
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rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
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/* SysTick initialization using the system clock.*/
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SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk |
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SysTick_CTRL_TICKINT_Msk;
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/* PWR clock enabled.*/
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rccEnablePWRInterface(FALSE);
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@ -761,7 +761,8 @@
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/* External declarations. */
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/*===========================================================================*/
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/* STM32 ISR, DMA and RCC helpers.*/
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/* Various helpers.*/
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#include "nvic.h"
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#include "stm32_isr.h"
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#include "stm32_dma.h"
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#include "stm32_rcc.h"
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@ -1,5 +1,6 @@
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# List of all the STM32F0xx platform files.
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PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
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PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/common/ARMCMx/nvic.c \
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${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
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${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \
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${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/TIMv1/st_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
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${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
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# Required include directories
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PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
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PLATFORMINC = ${CHIBIOS}/os/hal/platforms/common/ARMCMx \
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${CHIBIOS}/os/hal/platforms/STM32F0xx \
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${CHIBIOS}/os/hal/platforms/STM32 \
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${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
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${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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/* The following macro is only defined if some driver requiring DMA services
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector64) {
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OSAL_IRQ_HANDLER(Vector64) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
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DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
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if (dma_isr_redir[0].dma_func)
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dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector68) {
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OSAL_IRQ_HANDLER(Vector68) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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/* Check on channel 2.*/
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flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
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dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
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}
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/**
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector6C) {
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OSAL_IRQ_HANDLER(Vector6C) {
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uint32_t flags;
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CH_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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/* Check on channel 4.*/
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flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
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dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
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}
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CH_IRQ_EPILOGUE();
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OSAL_IRQ_EPILOGUE();
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}
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/*===========================================================================*/
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stm32_dmaisr_t func,
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void *param) {
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chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
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osalDbgCheck(dmastp != NULL);
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/* Checks if the stream is already taken.*/
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if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
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/* Enables the associated IRQ vector if a callback is defined.*/
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if (func != NULL)
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nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
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nvicEnableVector(dmastp->vector, priority);
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return FALSE;
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}
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@ -270,11 +269,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
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*/
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void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
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chDbgCheck(dmastp != NULL, "dmaStreamRelease");
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osalDbgCheck(dmastp != NULL);
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/* Check if the streams is not taken.*/
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chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
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"dmaStreamRelease(), #1", "not allocated");
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osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
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"not allocated");
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/* Disables the associated IRQ vector.*/
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nvicDisableVector(dmastp->vector);
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@ -34,163 +34,113 @@
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* @{
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*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_ADC2_DMA_MSK 0x00000000
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 FALSE
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#define STM32_ADC3_DMA_MSK 0x00000000
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 FALSE
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#define STM32_ADC4_DMA_MSK 0x00000000
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#define STM32_ADC4_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 0
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC TRUE
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#define STM32_HAS_DAC TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 28
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#define STM32_EXTI_NUM_CHANNELS 28
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
#define STM32_I2C3_RX_DMA_MSK 0
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C3_TX_DMA_MSK 0
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00000000
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS FALSE
|
||||
#define STM32_RTC_IS_CALENDAR TRUE
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS FALSE
|
||||
#define STM32_RTC_IS_CALENDAR TRUE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_SPI3_RX_DMA_MSK 0
|
||||
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI3_TX_DMA_MSK 0
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 TRUE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 TRUE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \
|
||||
STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_USART3_RX_DMA_MSK 0
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK 0
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_UART4_RX_DMA_MSK 0
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK 0
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_UART5_RX_DMA_MSK 0
|
||||
#define STM32_UART5_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART5_TX_DMA_MSK 0
|
||||
#define STM32_UART5_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_USART6_RX_DMA_MSK 0
|
||||
#define STM32_USART6_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART6_TX_DMA_MSK 0
|
||||
#define STM32_USART6_TX_DMA_CHN 0x00000000
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
|
||||
#endif /* _STM32_REGISTRY_H_ */
|
||||
|
|
|
@ -102,17 +102,6 @@ void hal_lld_init(void) {
|
|||
rccResetAPB1(0xFFFFFFFF);
|
||||
rccResetAPB2(0xFFFFFFFF);
|
||||
|
||||
/* SysTick initialization using the system clock.*/
|
||||
// SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
|
||||
// SysTick->VAL = 0;
|
||||
// SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
// SysTick_CTRL_ENABLE_Msk |
|
||||
// SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
/* DWT cycle counter enable.*/
|
||||
// SCS_DEMCR |= SCS_DEMCR_TRCENA;
|
||||
// DWT_CTRL |= DWT_CTRL_CYCCNTENA;
|
||||
|
||||
/* PWR clock enabled.*/
|
||||
rccEnablePWRInterface(FALSE);
|
||||
|
||||
|
|
|
@ -120,8 +120,9 @@ _port_switch_from_isr:
|
|||
#endif
|
||||
.globl _port_exit_from_isr
|
||||
_port_exit_from_isr:
|
||||
ldr r3, .L2
|
||||
ldr r2, .L3
|
||||
ldr r2, .L2
|
||||
ldr r3, .L3
|
||||
str r3, [r2, #0]
|
||||
#if CORTEX_ALTERNATE_SWITCH
|
||||
cpsie i
|
||||
#endif
|
||||
|
|
|
@ -34,7 +34,7 @@ __ram_start__ = ORIGIN(ram);
|
|||
__ram_size__ = LENGTH(ram);
|
||||
__ram_end__ = __ram_start__ + __ram_size__;
|
||||
|
||||
ENTRY(ResetHandler)
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
|
Loading…
Reference in New Issue