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ChibiOS
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Added OTG clock setting to the STM32 HAL. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2641 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2011-01-15 08:01:07 +00:00
parent 8f86368f15
commit ac63722245
5 changed files with 34 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
demos/ARMCM3-STM32F107-GCC/mcuconf.h
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@ -45,6 +45,7 @@
#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
#define STM32_MCO STM32_MCO_NOCLOCK #define STM32_MCO STM32_MCO_NOCLOCK
/* /*

5
os/hal/platforms/STM32/hal_lld.c
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@ -180,8 +180,13 @@ void stm32_clock_init(void) {
#endif #endif
/* Clock settings.*/ /* Clock settings.*/
#if STM32_HAS_OTG1
RCC->CFGR = STM32_MCO | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
#else
RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
#endif
/* Flash setup and final clock selection. */ /* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */

14
os/hal/platforms/STM32/hal_lld.h
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@ -125,7 +125,7 @@
#define STM32_HAS_UART4 FALSE #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB FALSE #define STM32_HAS_USB FALSE
#define STM32_HAS_USBOTG FALSE #define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_MD_VL) #elif defined(STM32F10X_MD_VL)
/* /*
@ -192,7 +192,7 @@
#define STM32_HAS_UART4 FALSE #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB FALSE #define STM32_HAS_USB FALSE
#define STM32_HAS_USBOTG FALSE #define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_LD) #elif defined(STM32F10X_LD)
/* /*
@ -259,7 +259,7 @@
#define STM32_HAS_UART4 FALSE #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB FALSE #define STM32_HAS_USB FALSE
#define STM32_HAS_USBOTG FALSE #define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_MD) #elif defined(STM32F10X_MD)
/* /*
@ -326,7 +326,7 @@
#define STM32_HAS_UART4 FALSE #define STM32_HAS_UART4 FALSE
#define STM32_HAS_USB TRUE #define STM32_HAS_USB TRUE
#define STM32_HAS_USBOTG FALSE #define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_HD) #elif defined(STM32F10X_HD)
/* /*
@ -393,7 +393,7 @@
#define STM32_HAS_UART4 TRUE #define STM32_HAS_UART4 TRUE
#define STM32_HAS_USB TRUE #define STM32_HAS_USB TRUE
#define STM32_HAS_USBOTG FALSE #define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_XD) #elif defined(STM32F10X_XD)
/* /*
@ -460,7 +460,7 @@
#define STM32_HAS_UART4 TRUE #define STM32_HAS_UART4 TRUE
#define STM32_HAS_USB TRUE #define STM32_HAS_USB TRUE
#define STM32_HAS_USBOTG FALSE #define STM32_HAS_OTG1 FALSE
#elif defined(STM32F10X_CL) #elif defined(STM32F10X_CL)
/* /*
@ -527,7 +527,7 @@
#define STM32_HAS_UART4 TRUE #define STM32_HAS_UART4 TRUE
#define STM32_HAS_USB FALSE #define STM32_HAS_USB FALSE
#define STM32_HAS_USBOTG TRUE #define STM32_HAS_OTG1 TRUE
#else #else
#error "unspecified, unsupported or invalid STM32 platform" #error "unspecified, unsupported or invalid STM32 platform"

18
os/hal/platforms/STM32/hal_lld_f105_f107.h
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@ -276,6 +276,13 @@
#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif #endif
/**
* @brief OTG prescaler initialization.
*/
#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__)
#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3
#endif
/** /**
* @brief MCO pin setting. * @brief MCO pin setting.
*/ */
@ -504,6 +511,17 @@
#error "STM32_ADCCLK exceeding maximum frequency (14MHz)" #error "STM32_ADCCLK exceeding maximum frequency (14MHz)"
#endif #endif
/**
* @brief OTG frequency.
*/
#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__)
#define STM32_OTGFSCLK ((STM32_PLLCLKOUT * 2) / 3)
#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2)
#define STM32_OTGFSCLK STM32_PLLCLKOUT
#else
#error "invalid STM32_OTGFSPRE value specified"
#endif
/** /**
* @brief Timers 2, 3, 4, 5, 6, 7 clock. * @brief Timers 2, 3, 4, 5, 6, 7 clock.
*/ */

1
readme.txt
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@ -66,6 +66,7 @@
*** 2.1.8 *** *** 2.1.8 ***
- FIX: Fixed STM32F103 demo's incorrect clock settings (bug 3153746). - FIX: Fixed STM32F103 demo's incorrect clock settings (bug 3153746).
- NEW: Added OTG clock setting to the STM32 HAL.
*** 2.1.7 *** *** 2.1.7 ***
- FIX: Fixed various errors in the HAL documentation (bug 3153591). - FIX: Fixed various errors in the HAL documentation (bug 3153591).