diff --git a/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
index 1e9570ade..0f48faec9 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c
@@ -138,26 +138,12 @@ GPTDriver GPTD14;
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] gptp      pointer to a @p GPTDriver object
- */
-static void gpt_lld_serve_interrupt(GPTDriver *gptp) {
-
-  gptp->tim->SR = 0;
-  if (gptp->state == GPT_ONESHOT) {
-    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
-    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
-  }
-  gptp->config->callback(gptp);
-}
-
 /*===========================================================================*/
 /* Driver interrupt handlers.                                                */
 /*===========================================================================*/
 
-#if STM32_GPT_USE_TIM1
+#if STM32_GPT_USE_TIM1 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
 #if !defined(STM32_TIM1_UP_HANDLER)
 #error "STM32_TIM1_UP_HANDLER not defined"
 #endif
@@ -174,9 +160,11 @@ OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM1 */
 
-#if STM32_GPT_USE_TIM2
+#if STM32_GPT_USE_TIM2 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
 #if !defined(STM32_TIM2_HANDLER)
 #error "STM32_TIM2_HANDLER not defined"
 #endif
@@ -193,9 +181,11 @@ OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM2 */
 
-#if STM32_GPT_USE_TIM3
+#if STM32_GPT_USE_TIM3 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
 #if !defined(STM32_TIM3_HANDLER)
 #error "STM32_TIM3_HANDLER not defined"
 #endif
@@ -212,9 +202,11 @@ OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM3 */
 
-#if STM32_GPT_USE_TIM4
+#if STM32_GPT_USE_TIM4 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
 #if !defined(STM32_TIM4_HANDLER)
 #error "STM32_TIM4_HANDLER not defined"
 #endif
@@ -231,9 +223,11 @@ OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM4 */
 
-#if STM32_GPT_USE_TIM5
+#if STM32_GPT_USE_TIM5 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
 #if !defined(STM32_TIM5_HANDLER)
 #error "STM32_TIM5_HANDLER not defined"
 #endif
@@ -250,9 +244,11 @@ OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM5 */
 
-#if STM32_GPT_USE_TIM6
+#if STM32_GPT_USE_TIM6 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM6_SUPPRESS_ISR)
 #if !defined(STM32_TIM6_HANDLER)
 #error "STM32_TIM6_HANDLER not defined"
 #endif
@@ -269,9 +265,11 @@ OSAL_IRQ_HANDLER(STM32_TIM6_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM6_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM6 */
 
-#if STM32_GPT_USE_TIM7
+#if STM32_GPT_USE_TIM7 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM7_SUPPRESS_ISR)
 #if !defined(STM32_TIM7_HANDLER)
 #error "STM32_TIM7_HANDLER not defined"
 #endif
@@ -288,9 +286,11 @@ OSAL_IRQ_HANDLER(STM32_TIM7_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM7_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM7 */
 
-#if STM32_GPT_USE_TIM8
+#if STM32_GPT_USE_TIM8 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
 #if !defined(STM32_TIM8_UP_HANDLER)
 #error "STM32_TIM8_UP_HANDLER not defined"
 #endif
@@ -307,9 +307,11 @@ OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM8 */
 
-#if STM32_GPT_USE_TIM9
+#if STM32_GPT_USE_TIM9 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
 #if !defined(STM32_TIM9_HANDLER)
 #error "STM32_TIM9_HANDLER not defined"
 #endif
@@ -326,9 +328,11 @@ OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM9 */
 
-#if STM32_GPT_USE_TIM11
+#if STM32_GPT_USE_TIM11 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM11_SUPPRESS_ISR)
 #if !defined(STM32_TIM11_HANDLER)
 #error "STM32_TIM11_HANDLER not defined"
 #endif
@@ -345,9 +349,11 @@ OSAL_IRQ_HANDLER(STM32_TIM11_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM11_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM11 */
 
-#if STM32_GPT_USE_TIM12
+#if STM32_GPT_USE_TIM12 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM12_SUPPRESS_ISR)
 #if !defined(STM32_TIM12_HANDLER)
 #error "STM32_TIM12_HANDLER not defined"
 #endif
@@ -364,9 +370,11 @@ OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM12_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM12 */
 
-#if STM32_GPT_USE_TIM14
+#if STM32_GPT_USE_TIM14 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM14_SUPPRESS_ISR)
 #if !defined(STM32_TIM14_HANDLER)
 #error "STM32_TIM14_HANDLER not defined"
 #endif
@@ -383,6 +391,7 @@ OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */
 #endif /* STM32_GPT_USE_TIM14 */
 
 /*===========================================================================*/
@@ -485,7 +494,9 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD1 == gptp) {
       rccEnableTIM1(FALSE);
       rccResetTIM1();
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_GPT_TIM1_IRQ_PRIORITY);
+#endif
 #if defined(STM32_TIM1CLK)
       gptp->clock = STM32_TIM1CLK;
 #else
@@ -493,28 +504,49 @@ void gpt_lld_start(GPTDriver *gptp) {
 #endif
     }
 #endif
+
 #if STM32_GPT_USE_TIM2
     if (&GPTD2 == gptp) {
       rccEnableTIM2(FALSE);
       rccResetTIM2();
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM2_NUMBER, STM32_GPT_TIM2_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM2CLK)
+      gptp->clock = STM32_TIM2CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_GPT_USE_TIM3
     if (&GPTD3 == gptp) {
       rccEnableTIM3(FALSE);
       rccResetTIM3();
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM3_NUMBER, STM32_GPT_TIM3_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM3CLK)
+      gptp->clock = STM32_TIM3CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_GPT_USE_TIM4
     if (&GPTD4 == gptp) {
       rccEnableTIM4(FALSE);
       rccResetTIM4();
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM4_NUMBER, STM32_GPT_TIM4_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM4CLK)
+      gptp->clock = STM32_TIM4CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
 
@@ -522,8 +554,14 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD5 == gptp) {
       rccEnableTIM5(FALSE);
       rccResetTIM5();
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM5_NUMBER, STM32_GPT_TIM5_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM5CLK)
+      gptp->clock = STM32_TIM5CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
 
@@ -531,8 +569,14 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD6 == gptp) {
       rccEnableTIM6(FALSE);
       rccResetTIM6();
+#if !defined(STM32_TIM6_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM6_NUMBER, STM32_GPT_TIM6_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM6CLK)
+      gptp->clock = STM32_TIM6CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
 
@@ -540,8 +584,14 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD7 == gptp) {
       rccEnableTIM7(FALSE);
       rccResetTIM7();
+#if !defined(STM32_TIM7_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM7_NUMBER, STM32_GPT_TIM7_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM7CLK)
+      gptp->clock = STM32_TIM7CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
 
@@ -549,7 +599,9 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD8 == gptp) {
       rccEnableTIM8(FALSE);
       rccResetTIM8();
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_GPT_TIM8_IRQ_PRIORITY);
+#endif
 #if defined(STM32_TIM8CLK)
       gptp->clock = STM32_TIM8CLK;
 #else
@@ -562,8 +614,14 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD9 == gptp) {
       rccEnableTIM9(FALSE);
       rccResetTIM9();
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM9_NUMBER, STM32_GPT_TIM9_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM9CLK)
+      gptp->clock = STM32_TIM9CLK;
+#else
       gptp->clock = STM32_TIMCLK2;
+#endif
     }
 #endif
 
@@ -571,8 +629,14 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD11 == gptp) {
       rccEnableTIM11(FALSE);
       rccResetTIM11();
+#if !defined(STM32_TIM11_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM11_NUMBER, STM32_GPT_TIM11_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM11CLK)
+      gptp->clock = STM32_TIM11CLK;
+#else
       gptp->clock = STM32_TIMCLK2;
+#endif
     }
 #endif
 
@@ -580,8 +644,14 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD12 == gptp) {
       rccEnableTIM12(FALSE);
       rccResetTIM12();
+#if !defined(STM32_TIM12_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM12_NUMBER, STM32_GPT_TIM12_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM12CLK)
+      gptp->clock = STM32_TIM12CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
 
@@ -589,8 +659,14 @@ void gpt_lld_start(GPTDriver *gptp) {
     if (&GPTD14 == gptp) {
       rccEnableTIM14(FALSE);
       rccResetTIM14();
+#if !defined(STM32_TIM14_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM14_NUMBER, STM32_GPT_TIM14_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM14CLK)
+      gptp->clock = STM32_TIM14CLK;
+#else
       gptp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
   }
@@ -625,73 +701,108 @@ void gpt_lld_stop(GPTDriver *gptp) {
 
 #if STM32_GPT_USE_TIM1
     if (&GPTD1 == gptp) {
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
+#endif
       rccDisableTIM1(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM2
     if (&GPTD2 == gptp) {
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM2_NUMBER);
+#endif
       rccDisableTIM2(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM3
     if (&GPTD3 == gptp) {
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM3_NUMBER);
+#endif
       rccDisableTIM3(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM4
     if (&GPTD4 == gptp) {
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM4_NUMBER);
+#endif
       rccDisableTIM4(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM5
     if (&GPTD5 == gptp) {
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM5_NUMBER);
+#endif
       rccDisableTIM5(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM6
     if (&GPTD6 == gptp) {
+#if !defined(STM32_TIM6_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM6_NUMBER);
+#endif
       rccDisableTIM6(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM7
     if (&GPTD7 == gptp) {
+#if !defined(STM32_TIM7_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM7_NUMBER);
+#endif
       rccDisableTIM7(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM8
     if (&GPTD8 == gptp) {
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
+#endif
       rccDisableTIM8(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM9
     if (&GPTD9 == gptp) {
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM9_NUMBER);
+#endif
       rccDisableTIM9(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM11
     if (&GPTD11 == gptp) {
+#if !defined(STM32_TIM11_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM11_NUMBER);
+#endif
       rccDisableTIM11(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM12
     if (&GPTD12 == gptp) {
+#if !defined(STM32_TIM12_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM12_NUMBER);
+#endif
       rccDisableTIM12(FALSE);
     }
 #endif
+
 #if STM32_GPT_USE_TIM14
     if (&GPTD14 == gptp) {
+#if !defined(STM32_TIM14_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM14_NUMBER);
+#endif
       rccDisableTIM14(FALSE);
     }
 #endif
@@ -758,6 +869,23 @@ void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
   gptp->tim->SR   = 0;                          /* Clear pending IRQs.      */
 }
 
+/**
+ * @brief   Shared IRQ handler.
+ *
+ * @param[in] gptp      pointer to a @p GPTDriver object
+ *
+ * @notapi
+ */
+void gpt_lld_serve_interrupt(GPTDriver *gptp) {
+
+  gptp->tim->SR = 0;
+  if (gptp->state == GPT_ONESHOT) {
+    gptp->state = GPT_READY;                /* Back in GPT_READY state.     */
+    gpt_lld_stop_timer(gptp);               /* Timer automatically stopped. */
+  }
+  gptp->config->callback(gptp);
+}
+
 #endif /* HAL_USE_GPT */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h
index 946115402..3feba7526 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.h
@@ -393,62 +393,62 @@
 #endif
 
 /* IRQ priority checks.*/
-#if STM32_GPT_USE_TIM1 &&                                                   \
+#if STM32_GPT_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM1"
 #endif
 
-#if STM32_GPT_USE_TIM2 &&                                                   \
+#if STM32_GPT_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM2_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM2"
 #endif
 
-#if STM32_GPT_USE_TIM3 &&                                                   \
+#if STM32_GPT_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM3"
 #endif
 
-#if STM32_GPT_USE_TIM4 &&                                                   \
+#if STM32_GPT_USE_TIM4 && !defined(STM32_TIM_SUPPRESS_ISR) &&               \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM4"
 #endif
 
-#if STM32_GPT_USE_TIM5 &&                                                   \
+#if STM32_GPT_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM5_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM5"
 #endif
 
-#if STM32_GPT_USE_TIM6 &&                                                   \
+#if STM32_GPT_USE_TIM6 && !defined(STM32_TIM6_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM6_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM6"
 #endif
 
-#if STM32_GPT_USE_TIM7 &&                                                   \
+#if STM32_GPT_USE_TIM7 && !defined(STM32_TIM7_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM7_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM7"
 #endif
 
-#if STM32_GPT_USE_TIM8 &&                                                   \
+#if STM32_GPT_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM8_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM8"
 #endif
 
-#if STM32_GPT_USE_TIM9 &&                                                   \
+#if STM32_GPT_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM9_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM9"
 #endif
 
-#if STM32_GPT_USE_TIM11 &&                                                   \
+#if STM32_GPT_USE_TIM11 && !defined(STM32_TIM11_SUPPRESS_ISR) &&            \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM11_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM11"
 #endif
 
-#if STM32_GPT_USE_TIM12 &&                                                   \
+#if STM32_GPT_USE_TIM12 && !defined(STM32_TIM12_SUPPRESS_ISR) &&            \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM12_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM12"
 #endif
 
-#if STM32_GPT_USE_TIM14 &&                                                   \
+#if STM32_GPT_USE_TIM14 && !defined(STM32_TIM14_SUPPRESS_ISR) &&            \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM14_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM14"
 #endif
@@ -629,6 +629,7 @@ extern "C" {
   void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period);
   void gpt_lld_stop_timer(GPTDriver *gptp);
   void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval);
+  void gpt_lld_serve_interrupt(GPTDriver *gptp);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c
index 6b2d35398..5959cbda1 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c
@@ -138,46 +138,17 @@ static bool icu_lld_wait_edge(ICUDriver *icup) {
   return result;
 }
 
-/**
- * @brief   Shared IRQ handler.
- *
- * @param[in] icup      pointer to the @p ICUDriver object
- */
-static void icu_lld_serve_interrupt(ICUDriver *icup) {
-  uint32_t sr;
-
-  sr  = icup->tim->SR;
-  sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
-  icup->tim->SR = ~sr;
-  if (icup->config->channel == ICU_CHANNEL_1) {
-    if ((sr & STM32_TIM_SR_CC2IF) != 0)
-      _icu_isr_invoke_width_cb(icup);
-    if ((sr & STM32_TIM_SR_CC1IF) != 0)
-      _icu_isr_invoke_period_cb(icup);
-  }
-  else {
-    if ((sr & STM32_TIM_SR_CC1IF) != 0)
-      _icu_isr_invoke_width_cb(icup);
-    if ((sr & STM32_TIM_SR_CC2IF) != 0)
-      _icu_isr_invoke_period_cb(icup);
-  }
-  if ((sr & STM32_TIM_SR_UIF) != 0)
-    _icu_isr_invoke_overflow_cb(icup);
-}
-
 /*===========================================================================*/
 /* Driver interrupt handlers.                                                */
 /*===========================================================================*/
 
-#if STM32_ICU_USE_TIM1
+#if STM32_ICU_USE_TIM1 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
 #if !defined(STM32_TIM1_UP_HANDLER)
 #error "STM32_TIM1_UP_HANDLER not defined"
 #endif
 /**
  * @brief   TIM1 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -195,9 +166,6 @@ OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
 #endif
 /**
  * @brief   TIM1 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -209,17 +177,16 @@ OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM1 */
 
-#if STM32_ICU_USE_TIM2
+#if STM32_ICU_USE_TIM2 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
 #if !defined(STM32_TIM2_HANDLER)
 #error "STM32_TIM2_HANDLER not defined"
 #endif
 /**
  * @brief   TIM2 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -231,17 +198,16 @@ OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM2 */
 
-#if STM32_ICU_USE_TIM3
+#if STM32_ICU_USE_TIM3 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
 #if !defined(STM32_TIM3_HANDLER)
 #error "STM32_TIM3_HANDLER not defined"
 #endif
 /**
  * @brief   TIM3 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -253,17 +219,16 @@ OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM3 */
 
-#if STM32_ICU_USE_TIM4
+#if STM32_ICU_USE_TIM4 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
 #if !defined(STM32_TIM4_HANDLER)
 #error "STM32_TIM4_HANDLER not defined"
 #endif
 /**
  * @brief   TIM4 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -275,17 +240,16 @@ OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM4 */
 
-#if STM32_ICU_USE_TIM5
+#if STM32_ICU_USE_TIM5 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
 #if !defined(STM32_TIM5_HANDLER)
 #error "STM32_TIM5_HANDLER not defined"
 #endif
 /**
  * @brief   TIM5 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -297,17 +261,16 @@ OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM5 */
 
-#if STM32_ICU_USE_TIM8
+#if STM32_ICU_USE_TIM8 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
 #if !defined(STM32_TIM8_UP_HANDLER)
 #error "STM32_TIM8_UP_HANDLER not defined"
 #endif
 /**
  * @brief   TIM8 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -325,9 +288,6 @@ OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
 #endif
 /**
  * @brief   TIM8 compare interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -339,17 +299,16 @@ OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM8 */
 
-#if STM32_ICU_USE_TIM9
+#if STM32_ICU_USE_TIM9 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
 #if !defined(STM32_TIM9_HANDLER)
 #error "STM32_TIM9_HANDLER not defined"
 #endif
 /**
  * @brief   TIM9 interrupt handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
  *
  * @isr
  */
@@ -361,6 +320,7 @@ OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
 #endif /* STM32_ICU_USE_TIM9 */
 
 /*===========================================================================*/
@@ -437,8 +397,10 @@ void icu_lld_start(ICUDriver *icup) {
     if (&ICUD1 == icup) {
       rccEnableTIM1(FALSE);
       rccResetTIM1();
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
       nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_ICU_TIM1_IRQ_PRIORITY);
+#endif
 #if defined(STM32_TIM1CLK)
       icup->clock = STM32_TIM1CLK;
 #else
@@ -446,44 +408,75 @@ void icu_lld_start(ICUDriver *icup) {
 #endif
     }
 #endif
+
 #if STM32_ICU_USE_TIM2
     if (&ICUD2 == icup) {
       rccEnableTIM2(FALSE);
       rccResetTIM2();
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM2_NUMBER, STM32_ICU_TIM2_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM2CLK)
+      icup->clock = STM32_TIM2CLK;
+#else
       icup->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_ICU_USE_TIM3
     if (&ICUD3 == icup) {
       rccEnableTIM3(FALSE);
       rccResetTIM3();
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM3_NUMBER, STM32_ICU_TIM3_IRQ_PRIORITY);
-      icup->clock = STM32_TIMCLK1;
+#endif
+#if defined(STM32_TIM3CLK)
+      icup->clock = STM32_TIM3CLK;
+#else
+     icup->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_ICU_USE_TIM4
     if (&ICUD4 == icup) {
       rccEnableTIM4(FALSE);
       rccResetTIM4();
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM4_NUMBER, STM32_ICU_TIM4_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM4CLK)
+      icup->clock = STM32_TIM4CLK;
+#else
       icup->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_ICU_USE_TIM5
     if (&ICUD5 == icup) {
       rccEnableTIM5(FALSE);
       rccResetTIM5();
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM5_NUMBER, STM32_ICU_TIM5_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM5CLK)
+      icup->clock = STM32_TIM5CLK;
+#else
       icup->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_ICU_USE_TIM8
     if (&ICUD8 == icup) {
       rccEnableTIM8(FALSE);
       rccResetTIM8();
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
       nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_ICU_TIM8_IRQ_PRIORITY);
+#endif
 #if defined(STM32_TIM8CLK)
       icup->clock = STM32_TIM8CLK;
 #else
@@ -491,12 +484,19 @@ void icu_lld_start(ICUDriver *icup) {
 #endif
     }
 #endif
+
 #if STM32_ICU_USE_TIM9
     if (&ICUD9 == icup) {
       rccEnableTIM9(FALSE);
       rccResetTIM9();
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM9_NUMBER, STM32_ICU_TIM9_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM9CLK)
+      icup->clock = STM32_TIM9CLK;
+#else
       icup->clock = STM32_TIMCLK2;
+#endif
     }
 #endif
   }
@@ -588,45 +588,65 @@ void icu_lld_stop(ICUDriver *icup) {
 
 #if STM32_ICU_USE_TIM1
     if (&ICUD1 == icup) {
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
+#endif
       rccDisableTIM1(FALSE);
     }
 #endif
+
 #if STM32_ICU_USE_TIM2
     if (&ICUD2 == icup) {
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM2_NUMBER);
+#endif
       rccDisableTIM2(FALSE);
     }
 #endif
+
 #if STM32_ICU_USE_TIM3
     if (&ICUD3 == icup) {
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM3_NUMBER);
+#endif
       rccDisableTIM3(FALSE);
     }
 #endif
+
 #if STM32_ICU_USE_TIM4
     if (&ICUD4 == icup) {
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM4_NUMBER);
+#endif
       rccDisableTIM4(FALSE);
     }
 #endif
+
 #if STM32_ICU_USE_TIM5
     if (&ICUD5 == icup) {
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM5_NUMBER);
+#endif
       rccDisableTIM5(FALSE);
     }
 #endif
+
 #if STM32_ICU_USE_TIM8
     if (&ICUD8 == icup) {
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
+#endif
       rccDisableTIM8(FALSE);
     }
 #endif
+
 #if STM32_ICU_USE_TIM9
     if (&ICUD9 == icup) {
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM9_NUMBER);
+#endif
       rccDisableTIM9(FALSE);
     }
 #endif
@@ -697,7 +717,7 @@ void icu_lld_stop_capture(ICUDriver *icup) {
  *
  * @param[in] icup      pointer to the @p ICUDriver object
  *
- * @api
+ * @notapi
  */
 void icu_lld_enable_notifications(ICUDriver *icup) {
   uint32_t dier = icup->tim->DIER;
@@ -743,7 +763,7 @@ void icu_lld_enable_notifications(ICUDriver *icup) {
  *
  * @param[in] icup      pointer to the @p ICUDriver object
  *
- * @api
+ * @notapi
  */
 void icu_lld_disable_notifications(ICUDriver *icup) {
 
@@ -751,6 +771,35 @@ void icu_lld_disable_notifications(ICUDriver *icup) {
   icup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
 }
 
+/**
+ * @brief   Shared IRQ handler.
+ *
+ * @param[in] icup      pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+void icu_lld_serve_interrupt(ICUDriver *icup) {
+  uint32_t sr;
+
+  sr  = icup->tim->SR;
+  sr &= icup->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
+  icup->tim->SR = ~sr;
+  if (icup->config->channel == ICU_CHANNEL_1) {
+    if ((sr & STM32_TIM_SR_CC2IF) != 0)
+      _icu_isr_invoke_width_cb(icup);
+    if ((sr & STM32_TIM_SR_CC1IF) != 0)
+      _icu_isr_invoke_period_cb(icup);
+  }
+  else {
+    if ((sr & STM32_TIM_SR_CC1IF) != 0)
+      _icu_isr_invoke_width_cb(icup);
+    if ((sr & STM32_TIM_SR_CC2IF) != 0)
+      _icu_isr_invoke_period_cb(icup);
+  }
+  if ((sr & STM32_TIM_SR_UIF) != 0)
+    _icu_isr_invoke_overflow_cb(icup);
+}
+
 #endif /* HAL_USE_ICU */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h
index 0de59080c..543a91c3e 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/icu_lld.h
@@ -251,37 +251,37 @@
 #endif
 
 /* IRQ priority checks.*/
-#if STM32_ICU_USE_TIM1 &&                                                   \
+#if STM32_ICU_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM1"
 #endif
 
-#if STM32_ICU_USE_TIM2 &&                                                   \
+#if STM32_ICU_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM2_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM2"
 #endif
 
-#if STM32_ICU_USE_TIM3 &&                                                   \
+#if STM32_ICU_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM3"
 #endif
 
-#if STM32_ICU_USE_TIM4 &&                                                   \
+#if STM32_ICU_USE_TIM4 && !defined(STM32_TIM4_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM4"
 #endif
 
-#if STM32_ICU_USE_TIM5 &&                                                   \
+#if STM32_ICU_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM5_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM5"
 #endif
 
-#if STM32_ICU_USE_TIM8 &&                                                   \
+#if STM32_ICU_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM8_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM8"
 #endif
 
-#if STM32_ICU_USE_TIM9 &&                                                   \
+#if STM32_ICU_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ICU_TIM9_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM9"
 #endif
@@ -475,6 +475,7 @@ extern "C" {
   void icu_lld_stop_capture(ICUDriver *icup);
   void icu_lld_enable_notifications(ICUDriver *icup);
   void icu_lld_disable_notifications(ICUDriver *icup);
+  void icu_lld_serve_interrupt(ICUDriver *icup);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
index c03303577..748675885 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c
@@ -98,44 +98,12 @@ PWMDriver PWMD9;
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-#if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 ||       \
-    STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
-/**
- * @brief   Common TIM2...TIM5,TIM9 IRQ handler.
- * @note    It is assumed that the various sources are only activated if the
- *          associated callback pointer is not equal to @p NULL in order to not
- *          perform an extra check in a potentially critical interrupt handler.
- *
- * @param[in] pwmp      pointer to a @p PWMDriver object
- */
-static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
-  uint32_t sr;
-
-  sr  = pwmp->tim->SR;
-  sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
-  pwmp->tim->SR = ~sr;
-  if (((sr & STM32_TIM_SR_CC1IF) != 0) &&
-      (pwmp->config->channels[0].callback != NULL))
-    pwmp->config->channels[0].callback(pwmp);
-  if (((sr & STM32_TIM_SR_CC2IF) != 0) &&
-      (pwmp->config->channels[1].callback != NULL))
-    pwmp->config->channels[1].callback(pwmp);
-  if (((sr & STM32_TIM_SR_CC3IF) != 0) &&
-      (pwmp->config->channels[2].callback != NULL))
-    pwmp->config->channels[2].callback(pwmp);
-  if (((sr & STM32_TIM_SR_CC4IF) != 0) &&
-      (pwmp->config->channels[3].callback != NULL))
-    pwmp->config->channels[3].callback(pwmp);
-  if (((sr & STM32_TIM_SR_UIF) != 0) && (pwmp->config->callback != NULL))
-    pwmp->config->callback(pwmp);
-}
-#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */
-
 /*===========================================================================*/
 /* Driver interrupt handlers.                                                */
 /*===========================================================================*/
 
-#if STM32_PWM_USE_TIM1
+#if STM32_PWM_USE_TIM1 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
 #if !defined(STM32_TIM1_UP_HANDLER)
 #error "STM32_TIM1_UP_HANDLER not defined"
 #endif
@@ -151,9 +119,7 @@ OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
 
   OSAL_IRQ_PROLOGUE();
 
-  STM32_TIM1->SR = ~STM32_TIM_SR_UIF;
-  if (PWMD1.config->callback != NULL)
-    PWMD1.config->callback(&PWMD1);
+  pwm_lld_serve_interrupt(&PWMD1);
 
   OSAL_IRQ_EPILOGUE();
 }
@@ -170,33 +136,18 @@ OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) {
  * @isr
  */
 OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) {
-  uint32_t sr;
 
   OSAL_IRQ_PROLOGUE();
 
-  sr = STM32_TIM1->SR & STM32_TIM1->DIER & (STM32_TIM_DIER_CC1IE |
-                                            STM32_TIM_DIER_CC2IE |
-                                            STM32_TIM_DIER_CC3IE |
-                                            STM32_TIM_DIER_CC4IE);
-  STM32_TIM1->SR = ~sr;
-  if (((sr & STM32_TIM_SR_CC1IF) != 0) &&
-      (PWMD1.config->channels[0].callback != NULL))
-    PWMD1.config->channels[0].callback(&PWMD1);
-  if (((sr & STM32_TIM_SR_CC2IF) != 0) &&
-      (PWMD1.config->channels[1].callback != NULL))
-    PWMD1.config->channels[1].callback(&PWMD1);
-  if (((sr & STM32_TIM_SR_CC3IF) != 0) &&
-      (PWMD1.config->channels[2].callback != NULL))
-    PWMD1.config->channels[2].callback(&PWMD1);
-  if (((sr & STM32_TIM_SR_CC4IF) != 0) &&
-      (PWMD1.config->channels[3].callback != NULL))
-    PWMD1.config->channels[3].callback(&PWMD1);
+  pwm_lld_serve_interrupt(&PWMD1);
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM1_SUPPRESS_ISR) */
 #endif /* STM32_PWM_USE_TIM1 */
 
-#if STM32_PWM_USE_TIM2
+#if STM32_PWM_USE_TIM2 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
 #if !defined(STM32_TIM2_HANDLER)
 #error "STM32_TIM2_HANDLER not defined"
 #endif
@@ -213,9 +164,11 @@ OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
 #endif /* STM32_PWM_USE_TIM2 */
 
-#if STM32_PWM_USE_TIM3
+#if STM32_PWM_USE_TIM3 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
 #if !defined(STM32_TIM3_HANDLER)
 #error "STM32_TIM3_HANDLER not defined"
 #endif
@@ -232,9 +185,11 @@ OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM3_SUPPRESS_ISR) */
 #endif /* STM32_PWM_USE_TIM3 */
 
-#if STM32_PWM_USE_TIM4
+#if STM32_PWM_USE_TIM4 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
 #if !defined(STM32_TIM4_HANDLER)
 #error "STM32_TIM4_HANDLER not defined"
 #endif
@@ -251,9 +206,11 @@ OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM4_SUPPRESS_ISR) */
 #endif /* STM32_PWM_USE_TIM4 */
 
-#if STM32_PWM_USE_TIM5
+#if STM32_PWM_USE_TIM5 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
 #if !defined(STM32_TIM5_HANDLER)
 #error "STM32_TIM5_HANDLER not defined"
 #endif
@@ -270,9 +227,11 @@ OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM5_SUPPRESS_ISR) */
 #endif /* STM32_PWM_USE_TIM5 */
 
-#if STM32_PWM_USE_TIM8
+#if STM32_PWM_USE_TIM8 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
 #if !defined(STM32_TIM8_UP_HANDLER)
 #error "STM32_TIM8_UP_HANDLER not defined"
 #endif
@@ -288,9 +247,7 @@ OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
 
   OSAL_IRQ_PROLOGUE();
 
-  STM32_TIM8->SR = ~TIM_SR_UIF;
-  if (PWMD8.config->callback != NULL)
-    PWMD8.config->callback(&PWMD8);
+  pwm_lld_serve_interrupt(&PWMD8);
 
   OSAL_IRQ_EPILOGUE();
 }
@@ -307,33 +264,18 @@ OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) {
  * @isr
  */
 OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) {
-  uint32_t sr;
 
   OSAL_IRQ_PROLOGUE();
 
-  sr = STM32_TIM8->SR & STM32_TIM8->DIER & (STM32_TIM_DIER_CC1IE |
-                                            STM32_TIM_DIER_CC2IE |
-                                            STM32_TIM_DIER_CC3IE |
-                                            STM32_TIM_DIER_CC4IE);
-  STM32_TIM8->SR = ~sr;
-  if (((sr & STM32_TIM_SR_CC1IF) != 0) &&
-      (PWMD8.config->channels[0].callback != NULL))
-    PWMD8.config->channels[0].callback(&PWMD8);
-  if (((sr & STM32_TIM_SR_CC2IF) != 0) &&
-      (PWMD8.config->channels[1].callback != NULL))
-    PWMD8.config->channels[1].callback(&PWMD8);
-  if (((sr & STM32_TIM_SR_CC3IF) != 0) &&
-      (PWMD8.config->channels[2].callback != NULL))
-    PWMD8.config->channels[2].callback(&PWMD8);
-  if (((sr & STM32_TIM_SR_CC4IF) != 0) &&
-      (PWMD8.config->channels[3].callback != NULL))
-    PWMD8.config->channels[3].callback(&PWMD8);
+  pwm_lld_serve_interrupt(&PWMD8);
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM8_SUPPRESS_ISR) */
 #endif /* STM32_PWM_USE_TIM8 */
 
-#if STM32_PWM_USE_TIM9
+#if STM32_PWM_USE_TIM9 || defined(__DOXYGEN__)
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
 #if !defined(STM32_TIM9_HANDLER)
 #error "STM32_TIM9_HANDLER not defined"
 #endif
@@ -350,6 +292,7 @@ OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* !defined(STM32_TIM9_SUPPRESS_ISR) */
 #endif /* STM32_PWM_USE_TIM9 */
 
 /*===========================================================================*/
@@ -432,8 +375,10 @@ void pwm_lld_start(PWMDriver *pwmp) {
     if (&PWMD1 == pwmp) {
       rccEnableTIM1(FALSE);
       rccResetTIM1();
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
       nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_PWM_TIM1_IRQ_PRIORITY);
+#endif
 #if defined(STM32_TIM1CLK)
       pwmp->clock = STM32_TIM1CLK;
 #else
@@ -441,28 +386,49 @@ void pwm_lld_start(PWMDriver *pwmp) {
 #endif
     }
 #endif
+
 #if STM32_PWM_USE_TIM2
     if (&PWMD2 == pwmp) {
       rccEnableTIM2(FALSE);
       rccResetTIM2();
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM2_NUMBER, STM32_PWM_TIM2_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM2CLK)
+      pwmp->clock = STM32_TIM2CLK;
+#else
       pwmp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_PWM_USE_TIM3
     if (&PWMD3 == pwmp) {
       rccEnableTIM3(FALSE);
       rccResetTIM3();
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM3_NUMBER, STM32_PWM_TIM3_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM3CLK)
+      pwmp->clock = STM32_TIM3CLK;
+#else
       pwmp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_PWM_USE_TIM4
     if (&PWMD4 == pwmp) {
       rccEnableTIM4(FALSE);
       rccResetTIM4();
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM4_NUMBER, STM32_PWM_TIM4_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM4CLK)
+      pwmp->clock = STM32_TIM4CLK;
+#else
       pwmp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
 
@@ -470,16 +436,25 @@ void pwm_lld_start(PWMDriver *pwmp) {
     if (&PWMD5 == pwmp) {
       rccEnableTIM5(FALSE);
       rccResetTIM5();
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM5_NUMBER, STM32_PWM_TIM5_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM5CLK)
+      pwmp->clock = STM32_TIM5CLK;
+#else
       pwmp->clock = STM32_TIMCLK1;
+#endif
     }
 #endif
+
 #if STM32_PWM_USE_TIM8
     if (&PWMD8 == pwmp) {
       rccEnableTIM8(FALSE);
       rccResetTIM8();
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
       nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_PWM_TIM8_IRQ_PRIORITY);
+#endif
 #if defined(STM32_TIM8CLK)
       pwmp->clock = STM32_TIM8CLK;
 #else
@@ -487,12 +462,19 @@ void pwm_lld_start(PWMDriver *pwmp) {
 #endif
     }
 #endif
+
 #if STM32_PWM_USE_TIM9
     if (&PWMD9 == pwmp) {
       rccEnableTIM9(FALSE);
       rccResetTIM9();
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
       nvicEnableVector(STM32_TIM9_NUMBER, STM32_PWM_TIM9_IRQ_PRIORITY);
+#endif
+#if defined(STM32_TIM9CLK)
+      pwmp->clock = STM32_TIM9CLK;
+#else
       pwmp->clock = STM32_TIMCLK2;
+#endif
     }
 #endif
 
@@ -640,45 +622,65 @@ void pwm_lld_stop(PWMDriver *pwmp) {
 
 #if STM32_PWM_USE_TIM1
     if (&PWMD1 == pwmp) {
+#if !defined(STM32_TIM1_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
+#endif
       rccDisableTIM1(FALSE);
     }
 #endif
+
 #if STM32_PWM_USE_TIM2
     if (&PWMD2 == pwmp) {
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM2_NUMBER);
+#endif
       rccDisableTIM2(FALSE);
     }
 #endif
+
 #if STM32_PWM_USE_TIM3
     if (&PWMD3 == pwmp) {
+#if !defined(STM32_TIM3_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM3_NUMBER);
+#endif
       rccDisableTIM3(FALSE);
     }
 #endif
+
 #if STM32_PWM_USE_TIM4
     if (&PWMD4 == pwmp) {
+#if !defined(STM32_TIM4_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM4_NUMBER);
+#endif
       rccDisableTIM4(FALSE);
     }
 #endif
+
 #if STM32_PWM_USE_TIM5
     if (&PWMD5 == pwmp) {
+#if !defined(STM32_TIM5_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM5_NUMBER);
+#endif
       rccDisableTIM5(FALSE);
     }
 #endif
+
 #if STM32_PWM_USE_TIM8
     if (&PWMD8 == pwmp) {
+#if !defined(STM32_TIM8_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
+#endif
       rccDisableTIM8(FALSE);
     }
 #endif
+
 #if STM32_PWM_USE_TIM9
     if (&PWMD9 == pwmp) {
+#if !defined(STM32_TIM9_SUPPRESS_ISR)
       nvicDisableVector(STM32_TIM9_NUMBER);
+#endif
       rccDisableTIM9(FALSE);
     }
 #endif
@@ -819,6 +821,38 @@ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
   pwmp->tim->DIER &= ~(2 << channel);
 }
 
+/**
+ * @brief   Common TIM2...TIM5,TIM9 IRQ handler.
+ * @note    It is assumed that the various sources are only activated if the
+ *          associated callback pointer is not equal to @p NULL in order to not
+ *          perform an extra check in a potentially critical interrupt handler.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+  uint32_t sr;
+
+  sr  = pwmp->tim->SR;
+  sr &= pwmp->tim->DIER & STM32_TIM_DIER_IRQ_MASK;
+  pwmp->tim->SR = ~sr;
+  if (((sr & STM32_TIM_SR_CC1IF) != 0) &&
+      (pwmp->config->channels[0].callback != NULL))
+    pwmp->config->channels[0].callback(pwmp);
+  if (((sr & STM32_TIM_SR_CC2IF) != 0) &&
+      (pwmp->config->channels[1].callback != NULL))
+    pwmp->config->channels[1].callback(pwmp);
+  if (((sr & STM32_TIM_SR_CC3IF) != 0) &&
+      (pwmp->config->channels[2].callback != NULL))
+    pwmp->config->channels[2].callback(pwmp);
+  if (((sr & STM32_TIM_SR_CC4IF) != 0) &&
+      (pwmp->config->channels[3].callback != NULL))
+    pwmp->config->channels[3].callback(pwmp);
+  if (((sr & STM32_TIM_SR_UIF) != 0) && (pwmp->config->callback != NULL))
+    pwmp->config->callback(pwmp);
+}
+
 #endif /* HAL_USE_PWM */
 
 /** @} */
diff --git a/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h
index a7da37007..4bf83b056 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.h
@@ -306,37 +306,37 @@
 #endif
 
 /* IRQ priority checks.*/
-#if STM32_PWM_USE_TIM1 &&                                                   \
+#if STM32_PWM_USE_TIM1 && !defined(STM32_TIM1_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM1"
 #endif
 
-#if STM32_PWM_USE_TIM2 &&                                                   \
+#if STM32_PWM_USE_TIM2 && !defined(STM32_TIM2_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM2_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM2"
 #endif
 
-#if STM32_PWM_USE_TIM3 &&                                                   \
+#if STM32_PWM_USE_TIM3 && !defined(STM32_TIM3_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM3"
 #endif
 
-#if STM32_PWM_USE_TIM4 &&                                                   \
+#if STM32_PWM_USE_TIM4 && !defined(STM32_TIM4_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM4"
 #endif
 
-#if STM32_PWM_USE_TIM5 &&                                                   \
+#if STM32_PWM_USE_TIM5 && !defined(STM32_TIM5_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM5_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM5"
 #endif
 
-#if STM32_PWM_USE_TIM8 &&                                                   \
+#if STM32_PWM_USE_TIM8 && !defined(STM32_TIM8_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM8_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM8"
 #endif
 
-#if STM32_PWM_USE_TIM9 &&                                                   \
+#if STM32_PWM_USE_TIM9 && !defined(STM32_TIM9_SUPPRESS_ISR) &&              \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_PWM_TIM9_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to TIM9"
 #endif
@@ -538,6 +538,7 @@ extern "C" {
                                            pwmchannel_t channel);
   void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
                                             pwmchannel_t channel);
+  void pwm_lld_serve_interrupt(PWMDriver *pwmp);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.c b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.c
index 419997c5d..5c854c89f 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/stm32_tim.c
@@ -47,6 +47,46 @@
 /* Driver interrupt handlers.                                                */
 /*===========================================================================*/
 
+#if defined(STM32_TIM2_IS_USED) || defined(__DOXYGEN__)
+#if !defined(STM32_TIM2_SUPPRESS_ISR)
+#if !defined(STM32_TIM2_HANDLER)
+#error "STM32_TIM2_HANDLER not defined"
+#endif
+/**
+ * @brief   TIM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) {
+  uint32_t sr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  sr  = TIM2->SR;
+  sr &= TIM2->DIER & STM32_TIM_DIER_IRQ_MASK;
+  TIM2->SR = ~sr;
+
+#if STM32_GPT_USE_TIM2
+  gpt_lld_serve_interrupt(&GPTD2);
+#endif
+
+#if STM32_ICU_USE_TIM2
+  icu_lld_serve_interrupt(&ICUD2, sr);
+#endif
+
+#if STM32_PWM_USE_TIM2
+  gpt_lld_serve_interrupt(&PWMD2, sr);
+#endif
+
+#if STM32_GPT_USE_TIM2
+  st_lld_serve_interrupt();
+#endif
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* !defined(STM32_TIM2_SUPPRESS_ISR) */
+#endif /* defined(STM32_TIM2_IS_USED) */
+
 /*===========================================================================*/
 /* Driver exported functions.                                                */
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt b/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt
new file mode 100644
index 000000000..f2abe5efc
--- /dev/null
+++ b/os/hal/ports/STM32/LLD/TIMv1/tim_irq_mapping.txt
@@ -0,0 +1,14 @@
+TIM units IRQ collisions mapping.
+
+       1B 1UP 1TC 1CC   2   3   4   5   6   7 8B  8UP 8TC 8CC   9  10  11  12  13  14  15  16  17  18  19  20  21  22 LP1 LP2
+F0xx    1---1   2---2   *   *           *   *                                       *   *   *   *
+F030    1---1   2---2       *                                                       *   *   *   *
+F1xx    1   2   3   *   *   *   *   *   *   *                   1   2   3
+F100    1   2   3   *   *   *   *   *   *   *                                           1   2   3
+F3xx    1   2   3   *   *   *   *       *   *   *   *   *   *                           1   2   3
+F37x                    *   *   *   *   *   *                               *   *   *   *   *   *   *   *
+F4xx    1   2   3   *   *   *   *   *   *   *   4   5   6   *   1   2   3   4   5   6
+F7xx    1   2   3   *   *   *   *   *   *   *   4   5   6   *   1   2   3   4   5   6                                   *
+L0xx                    *               *                                                                       *   *   *
+L1xx                    *   *   *   *   *   *                   *   *   *
+L4xx    1   2   3   *   *   *   *   *   *   *   *   *   *   *                           1   2   3                       *   *
diff --git a/readme.txt b/readme.txt
index 2682ea28e..95b503475 100644
--- a/readme.txt
+++ b/readme.txt
@@ -73,6 +73,12 @@
 *****************************************************************************
 
 *** 3.1.0 ***
+- HAL: STM32 GPT, ICU and PWM driver enhancements. Now it is possible to
+       suppress default ISRs by defining STM32_TIMx_SUPPRESS_ISR.
+       The application is now able to define custom handlers if required
+       or simply save space if the driver callbacks are not used.
+       Now the functions xxx_lld_serve_interrupts() have global scope, this
+       way custom ISRs can call them from outside the driver module.
 - HAL: Added TIM units use cross-check in STM32 GPT, ICU, PWM and ST drivers,
        now use collisions are explicitly reported.
 - NIL: Added polled delays required to fix bug #629.