Files mcuconf.h for STM32F746, F767, L432, L452, L476, L496 received the missing setting STM32_WSPI_QUADSPI1_PRESCALER_VALUE.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@14285 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -420,5 +420,6 @@
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*****************************************************************************
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*** 20.3.4 ***
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- NEW: Files mcuconf.h for STM32F746, F767, L432, L452, L476, L496 received
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the missing setting STM32_WSPI_QUADSPI1_PRESCALER_VALUE.
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- FIX: Fixed STM32G431 DMA defines error (bug #1155).
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- FIX: Fixed errors in STM32L4xx registry (bug #1154).
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- FIX: Fixed QUADSPI errata fix applied to all platforms (bug #1153).
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 FALSE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 TRUE
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#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
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#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
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#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
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#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
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#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
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#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
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#endif /* MCUCONF_H */
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*/
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#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
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#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
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#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
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#endif /* MCUCONF_H */
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