From ade12538d6f49f87f21b7b96d61dd33eefa1ad52 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Tue, 21 Sep 2021 14:22:22 +0000
Subject: [PATCH] More clock tree definitions.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14815 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/hal/boards/ST_STM32MP157A_DK1/board.h |  4 ++-
 os/hal/ports/STM32/STM32MP1xx/hal_lld.h  | 38 ++++++++++++++++++++++--
 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/os/hal/boards/ST_STM32MP157A_DK1/board.h b/os/hal/boards/ST_STM32MP157A_DK1/board.h
index 437e31a1b..3e6331b4b 100644
--- a/os/hal/boards/ST_STM32MP157A_DK1/board.h
+++ b/os/hal/boards/ST_STM32MP157A_DK1/board.h
@@ -33,7 +33,7 @@
 /*
  * Board identifier.
  */
-#define BOARD_ST_STM32L476_DISCOVERY
+#define BOARD_ST_STM32MP157A_DK1
 #define BOARD_NAME                  "STMicroelectronics STM32MP157A-DK1"
 
 /*
@@ -44,6 +44,8 @@
 #define STM32_LSECLK                32768U
 #endif
 
+#define STM32_LSEDRV                (3U << 3U)
+
 #if !defined(STM32_HSECLK)
 #define STM32_HSECLK                24000000U
 #endif
diff --git a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h
index dfce3701a..073341931 100644
--- a/os/hal/ports/STM32/STM32MP1xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32MP1xx/hal_lld.h
@@ -111,6 +111,16 @@
 #define STM32_PLL4SRC_I2S_CKIN   (3 << 0)   /**< PLL4 clock source is I2SCK.*/
 /** @} */
 
+/**
+ * @name    RCC_MSSCKSELR register bits definitions
+ * @{
+ */
+#define STM32_MCUSSRC_HSI        (0 << 0)   /**< MCU clock source is HSI.  */
+#define STM32_MCUSSRC_HSE        (1 << 0)   /**< MCU clock source is HSE.  */
+#define STM32_MCUSSRC_CSI        (2 << 0)   /**< MCU clock source is CSI.  */
+#define STM32_MCUSSRC_PLL3P      (3 << 0)   /**< MCU clock source is PLL3P.*/
+/** @} */
+
 /**
  * @name    RCC_CPERCKSELR register bits definitions
  * @{
@@ -190,7 +200,7 @@
 
 /**
  * @brief   Enables or disables the HSI64 clock source.
- * @note    This initialization is performed only if TZEN=0
+ * @note    This initialization is performed only if TZEN=0 or MCKPROT=0
  *          otherwise the setting must match the initialization performed
  *          on the Cortex-A side.
  */
@@ -210,7 +220,7 @@
 
 /**
  * @brief   Enables or disables the HSE clock source.
- * @note    This initialization is performed only if TZEN=0
+ * @note    This initialization is performed only if TZEN=0 or MCKPROT=0
  *          otherwise the setting must match the initialization performed
  *          on the Cortex-A side.
  */
@@ -347,7 +357,7 @@
  *          on the Cortex-A side.
  */
 #if !defined(STM32_MCUSSRC) || defined(__DOXYGEN__)
-#define STM32_MCUSSRC                       2222222222
+#define STM32_MCUSSRC                       STM32_MCUSSRC_PLL3P
 #endif
 
 /**
@@ -652,6 +662,28 @@
 /* Inclusion of PLL-related checks and calculations.*/
 #include <stm32_pll3.inc>
 
+/**
+ * @brief   MCU system clock source.
+ */
+#if STM32_NO_INIT || defined(__DOXYGEN__)
+  #define STM32_MCUSS_CK             STM32_CSICLK
+
+#elif (STM32_MCUSSRC == STM32_MCUSSRC_HSI)
+  #define STM32_MCUSS_CK             STM32_HSI64CLK
+
+#elif (STM32_MCUSSRC == STM32_MCUSSRC_HSE)
+  #define STM32_MCUSS_CK             STM32_HSECLK
+
+#elif (STM32_MCUSSRC == STM32_MCUSSRC_CSI)
+  #define STM32_MCUSS_CK             STM32_CSICLK
+
+#elif (STM32_MCUSSRC == STM32_MCUSSRC_PLL3P)
+  #define STM32_MCUSS_CK             STM32_PLL3_P_CLKOUT
+
+#else
+  #error "invalid STM32_MCUSSRC value specified"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/