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Added complementary capability to TIM channel 4, some devices support it. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13402 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-03-08 09:03:05 +00:00
parent 8f040bb81c
commit aea0b62a26
2 changed files with 11 additions and 0 deletions
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10
os/hal/ports/STM32/LLD/TIMv1/hal_pwm_lld.c
View File

@ -953,6 +953,16 @@ void pwm_lld_start(PWMDriver *pwmp) {
default: default:
; ;
} }
switch (pwmp->config->channels[3].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
ccer |= STM32_TIM_CCER_CC4NP;
/* Falls through.*/
case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
ccer |= STM32_TIM_CCER_CC4NE;
/* Falls through.*/
default:
;
}
} }
#endif /* STM32_PWM_USE_ADVANCED*/ #endif /* STM32_PWM_USE_ADVANCED*/

1
os/hal/ports/STM32/LLD/TIMv1/stm32_tim.h
View File

@ -279,6 +279,7 @@
#define STM32_TIM_CCER_CC3NP (1U << 11) #define STM32_TIM_CCER_CC3NP (1U << 11)
#define STM32_TIM_CCER_CC4E (1U << 12) #define STM32_TIM_CCER_CC4E (1U << 12)
#define STM32_TIM_CCER_CC4P (1U << 13) #define STM32_TIM_CCER_CC4P (1U << 13)
#define STM32_TIM_CCER_CC4NE (1U << 14)
#define STM32_TIM_CCER_CC4NP (1U << 15) #define STM32_TIM_CCER_CC4NP (1U << 15)
#define STM32_TIM_CCER_CC5E (1U << 16) #define STM32_TIM_CCER_CC5E (1U << 16)
#define STM32_TIM_CCER_CC5P (1U << 17) #define STM32_TIM_CCER_CC5P (1U << 17)