git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@257 35acf78f-673a-0410-8e92-d51de3d6d3f4

demos/ARMCM3-STM32F103-GCC/board.c

@@ -21,15 +21,56 @@
 
 #include "board.h"
 
+/*
+ * Wait states setting is a function of the system clock. Those are the
+ * recommended values, there should not be need to change them.
+ */
+#if SYSCLK <= 24000000
+#define FLASHBITS 0x00000010
+#else
+#if SYSCLK <= 48000000
+#define FLASHBITS 0x00000011
+#else
+#define FLASHBITS 0x00000012
+#endif
+#endif
+
 /*
  * Hardware initialization goes here.
  * NOTE: Interrupts are still disabled.
  */
 void hwinit(void) {
 
+  /*
+   * Clocks and PLL initialization.
+   */
+  // HSI setup.
+  RCC->CR = 0x00000083;         // Enforces a known state (HSI ON).
+  while (!(RCC->CR & (1 << 1)))
+    ;                           // Waits until HSI stable, it should already be.
+  // HSE setup.
+  RCC->CR |= (1 << 16);         // HSE ON.
+  while (!(RCC->CR & (1 << 17)))
+    ;                           // Waits until HSE stable.
+  // PLL setup.
+  RCC->CFGR |= PLLPREBITS | PLLMULBITS | PLLSRCBITS;
+  RCC->CR |= (1 << 24);         // PLL ON.
+  while (!(RCC->CR & (1 << 25)))
+    ;                           // Waits until PLL stable.
+  // Clock sources.
+  RCC->CFGR |= AHBBITS | PPRE1BITS | PPRE2BITS | ADCPREBITS |
+               USBPREBITS | MCOSRCBITS;
+
+  /*
+   * Flash setup and final clock selection.
+   */
+  FLASH->ACR = FLASHBITS;       // Flash wait states depending on clock.
+  RCC->CFGR |= SYSSRCBITS;      // Switches on the PLL clock.
+
   /*
    * I/O ports initialization as specified in board.h.
    */
+  RCC->APB2ENR = 0x0000003D;    // Ports A-D enabled, AFIO enabled.
   GPIOA->CRL = VAL_GPIOACRL;
   GPIOA->CRH = VAL_GPIOACRH;
   GPIOA->ODR = VAL_GPIOAODR;
@@ -45,4 +86,9 @@ void hwinit(void) {
   GPIOD->CRL = VAL_GPIODCRL;
   GPIOD->CRH = VAL_GPIODCRH;
   GPIOD->ODR = VAL_GPIODODR;
+
+  /*
+   * NVIC/SCB setup.
+   */
+  SCB->AIRCR = (0x5FA << 16) | (0x5 << 8);      // PRIGROUP = 5 (2:6).
 }

demos/ARMCM3-STM32F103-GCC/board.h

@@ -28,11 +28,47 @@
 
 #define BOARD_OLIMEX_STM32_P103
 
+/*
+ * Uncomment this if you want a 48MHz system clock, else it will be 72MHz.
+ */
+//#define SYSCLK_48
+
+/*
+ * NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
+ */
 #define LSECLK          32768
 #define HSECLK          8000000
-#define PLLDIV          1
+#define HSICLK          8000000
+#define PLLPRE          1
+#ifdef SYSCLK_48
+#define PLLMUL          6
+#else
 #define PLLMUL          9
-#define PLLCLK          ((HSECLK / PLLDIV) * PLLMUL)
+#endif
+#define PLLCLK          ((HSECLK / PLLPRE) * PLLMUL)
+#define SYSCLK          PLLCLK
+#define APB1CLK         (SYSCLK / 2)
+#define APB2CLK         (SYSCLK / 2)
+#define AHB1CLK         (SYSCLK / 1)
+
+/*
+ * Various clock settings.
+ */
+#define SYSSRCBITS      (0x2 << 0)      // PLLCLK is SYSCLK (do not change)
+#define AHBBITS         (0x0 << 4)      // Divided by 1
+#define PPRE1BITS       (0x4 << 8)      // Divided by 2 (must be <= 36MHz)
+#define PPRE2BITS       (0x4 << 11)     // Divided by 2
+#define ADCPREBITS      (0x3 << 14)     // Divided by 8
+#define PLLSRCBITS      (0x1 << 16)     // PLL source is HSE/1
+#define PLLPREBITS      ((PLLPRE - 1) << 17)
+#define PLLMULBITS      ((PLLMUL - 2) << 18)
+#ifdef SYSCLK_48
+#define USBPREBITS      (0x1 << 22)     // Divided by 1
+#else
+#define USBPREBITS      (0x0 << 22)     // Divided by 1.5
+#endif
+#define MCOSRCBITS      (0x0 << 24)     // No MCO output.
+
 
 #define GPIOA_BUTTON    (1 << 0)
 

readme.txt

@@ -63,6 +63,8 @@ Win32-MinGW            - ChibiOS/RT simulator and demo into a WIN32 process,
 *** Releases                                                              ***
 *****************************************************************************
 
+*** 0.6.3 ***
+
 *** 0.6.2 ***
 - NEW: Added C++ wrapper around the ChibiOS/RT core APIs, now it is possible
   to use the OS in a fully object oriented application. The wrapper offers