git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13476 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -46,12 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing RTC clock source impossible without resetting
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* of the whole BKP domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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static inline void bd_init(void) {
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
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@ -79,7 +74,7 @@ static void hal_lld_backup_domain_init(void) {
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static void flash_ws_init(uint32_t bits) {
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FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | bits;
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while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
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while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (bits & FLASH_ACR_LATENCY_Msk)) {
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}
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}
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@ -98,9 +93,6 @@ static void flash_ws_init(uint32_t bits) {
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*/
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void hal_lld_init(void) {
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/* Initializes the backup domain.*/
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hal_lld_backup_domain_init();
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/* DMA subsystems initialization.*/
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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@ -191,7 +183,7 @@ void stm32_clock_init(void) {
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RCC->CCIPR2 = ccipr2;
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}
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/* Set flash WS's for SYSCLK source */
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/* Wait states if SYSCLK requires more wait states than MSICLK.*/
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if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
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flash_ws_init(STM32_FLASHBITS);
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}
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@ -204,16 +196,19 @@ void stm32_clock_init(void) {
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;
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#endif
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/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */
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/* Wait states if SYSCLK requires less wait states than MSICLK.*/
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if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
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flash_ws_init(STM32_FLASHBITS);
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}
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#endif /* STM32_NO_INIT */
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/* Backup domain.*/
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bd_init();
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
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#endif /* STM32_NO_INIT */
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}
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/** @} */
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