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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13476 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2020-03-24 20:55:40 +00:00
parent e76f2c7fe9
commit b04a748788
1 changed files with 8 additions and 13 deletions
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21
os/hal/ports/STM32/STM32L5xx/hal_lld.c
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@ -46,12 +46,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
/** static inline void bd_init(void) {
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without resetting
* of the whole BKP domain.
*/
static void hal_lld_backup_domain_init(void) {
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
@ -79,7 +74,7 @@ static void hal_lld_backup_domain_init(void) {
static void flash_ws_init(uint32_t bits) { static void flash_ws_init(uint32_t bits) {
FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | bits; FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | bits;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) { while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (bits & FLASH_ACR_LATENCY_Msk)) {
} }
} }
@ -98,9 +93,6 @@ static void flash_ws_init(uint32_t bits) {
*/ */
void hal_lld_init(void) { void hal_lld_init(void) {
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
/* DMA subsystems initialization.*/ /* DMA subsystems initialization.*/
#if defined(STM32_DMA_REQUIRED) #if defined(STM32_DMA_REQUIRED)
dmaInit(); dmaInit();
@ -191,7 +183,7 @@ void stm32_clock_init(void) {
RCC->CCIPR2 = ccipr2; RCC->CCIPR2 = ccipr2;
} }
/* Set flash WS's for SYSCLK source */ /* Wait states if SYSCLK requires more wait states than MSICLK.*/
if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) { if (STM32_FLASHBITS > STM32_MSI_FLASHBITS) {
flash_ws_init(STM32_FLASHBITS); flash_ws_init(STM32_FLASHBITS);
} }
@ -204,16 +196,19 @@ void stm32_clock_init(void) {
; ;
#endif #endif
/* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */ /* Wait states if SYSCLK requires less wait states than MSICLK.*/
if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) { if (STM32_FLASHBITS < STM32_MSI_FLASHBITS) {
flash_ws_init(STM32_FLASHBITS); flash_ws_init(STM32_FLASHBITS);
} }
#endif /* STM32_NO_INIT */ /* Backup domain.*/
bd_init();
/* SYSCFG clock enabled here because it is a multi-functional unit shared /* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/ among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true); rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
#endif /* STM32_NO_INIT */
} }
/** @} */ /** @} */