Re-added the lost revisions (8103 and 8104).
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8103 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
577f267dda
commit
b05e7e8c44
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@ -33,7 +33,7 @@
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<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
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<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
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<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
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<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="r0-(format)" val="4"/><content id="r1-(format)" val="4"/><content id="r3-(format)" val="4"/><content id="r4-(format)" val="4"/><content id="r6-(format)" val="4"/><content id="cpsr-(format)" val="4"/><content id="lr_abt-(format)" val="4"/><content id="spsr_und-(format)" val="4"/></contentList>"/>
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<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList><content id="spsr_und-(format)" val="4"/><content id="lr_abt-(format)" val="4"/><content id="cpsr-(format)" val="4"/><content id="r6-(format)" val="4"/><content id="r4-(format)" val="4"/><content id="r3-(format)" val="4"/><content id="r1-(format)" val="4"/><content id="r0-(format)" val="4"/></contentList>"/>
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||||
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
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<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
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<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
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@ -56,7 +56,7 @@
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* The value one is not valid, timeouts are rounded up to
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* this value.
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*/
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#define CH_CFG_ST_TIMEDELTA 2
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#define CH_CFG_ST_TIMEDELTA 0
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/** @} */
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@ -132,7 +132,7 @@
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* @brief Enables the SERIAL subsystem.
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*/
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#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
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#define HAL_USE_SERIAL TRUE
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#define HAL_USE_SERIAL FALSE
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#endif
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/**
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@ -52,7 +52,7 @@ int main(void) {
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/*
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* Activates the serial driver 2 using the driver default configuration.
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*/
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sdStart(&SD2, NULL);
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// sdStart(&SD2, NULL);
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/*
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* Creates the blinker thread.
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@ -64,8 +64,8 @@ int main(void) {
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* sleeping in a loop and check the button state.
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*/
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while (true) {
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if (!palReadPad(GPIOC, GPIOC_BUTTON))
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TestThread(&SD2);
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// if (!palReadPad(GPIOC, GPIOC_BUTTON))
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// TestThread(&SD2);
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chThdSleepMilliseconds(500);
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}
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}
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@ -30,17 +30,13 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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#if defined(STM32L1XX)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
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#if defined(STM32L0XX) || defined(STM32L1XX)
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#define AHB_EN_MASK STM32_GPIO_EN_MASK
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#define AHB_LPEN_MASK AHB_EN_MASK
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#elif defined(STM32F0XX)
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#define AHB_EN_MASK STM32_GPIO_EN_MASK
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#elif defined(STM32F3XX) || defined(STM32F37X)
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#elif defined(STM32F0XX) || defined(STM32F3XX) || defined(STM32F37X)
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#define AHB_EN_MASK STM32_GPIO_EN_MASK
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#define AHB_LPEN_MASK 0
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#elif defined(STM32F2XX) || defined(STM32F4XX)
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#define AHB1_EN_MASK STM32_GPIO_EN_MASK
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@ -94,7 +90,10 @@ void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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#if defined(STM32L1XX)
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#if defined(STM32L0XX)
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rccEnableAHB(AHB_EN_MASK, TRUE);
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RCC->IOPSMENR |= AHB_LPEN_MASK;
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#elif defined(STM32L1XX)
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rccEnableAHB(AHB_EN_MASK, TRUE);
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RCC->AHBLPENR |= AHB_LPEN_MASK;
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#elif defined(STM32F0XX)
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@ -15,13 +15,15 @@
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*/
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/**
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* @file STM32F0xx/hal_lld.c
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* @brief STM32F0xx HAL subsystem low level driver source.
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* @file STM32L0xx/hal_lld.c
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* @brief STM32L0xx HAL subsystem low level driver source.
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*
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* @addtogroup HAL
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* @{
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*/
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/* TODO: LSEBYP like in F3. Disable HSI16 if not used.*/
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#include "hal.h"
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/*===========================================================================*/
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@ -34,7 +36,7 @@
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/**
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* @brief CMSIS system core clock variable.
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* @note It is declared in system_stm32f0xx.h.
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* @note It is declared in system_stm32l0xx.h.
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*/
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uint32_t SystemCoreClock = STM32_SYSCLK;
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@ -48,8 +50,6 @@ uint32_t SystemCoreClock = STM32_SYSCLK;
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing clock source impossible without resetting
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* of the whole BKP domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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@ -57,34 +57,28 @@ static void hal_lld_backup_domain_init(void) {
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PWR->CR |= PWR_CR_DBP;
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
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if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
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/* Backup domain reset.*/
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RCC->BDCR = RCC_BDCR_BDRST;
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RCC->BDCR = 0;
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RCC->CSR |= RCC_CSR_RTCRST;
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RCC->CSR &= ~RCC_CSR_RTCRST;
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}
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/* If enabled then the LSE is started.*/
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#if STM32_LSE_ENABLED
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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#endif
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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RCC->CSR |= RCC_CSR_LSEON;
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while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
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; /* Waits until LSE is stable. */
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#endif
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#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
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/* If the backup domain hasn't been initialized yet then proceed with
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initialization.*/
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
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if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
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/* Selects clock source.*/
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RCC->BDCR |= STM32_RTCSEL;
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RCC->CSR |= STM32_RTCSEL;
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/* RTC clock enabled.*/
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RCC->BDCR |= RCC_BDCR_RTCEN;
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RCC->CSR |= RCC_CSR_RTCEN;
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}
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#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
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}
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@ -105,9 +99,9 @@ static void hal_lld_backup_domain_init(void) {
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void hal_lld_init(void) {
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/* Reset of all peripherals.*/
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rccResetAHB(0xFFFFFFFF);
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rccResetAPB1(0xFFFFFFFF);
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rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
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rccResetAHB(~RCC_AHBRSTR_MIFRST);
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rccResetAPB1(~RCC_APB1RSTR_PWRRST);
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rccResetAPB2(~0);
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/* PWR clock enabled.*/
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rccEnablePWRInterface(FALSE);
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@ -126,60 +120,55 @@ void hal_lld_init(void) {
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}
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/**
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* @brief STM32 clocks and PLL initialization.
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* @brief STM32L1xx voltage, clocks and PLL initialization.
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* @note All the involved constants come from the file @p board.h.
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* @note This function should be invoked just after the system reset.
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*
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* @special
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*/
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/**
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* @brief Clocks and internal voltage initialization.
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*/
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* HSI setup, it enforces the reset situation in order to handle possible
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problems with JTAG probes and re-initializations.*/
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RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; /* Wait until HSI is stable. */
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/* PWR clock enable.*/
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RCC->APB1ENR = RCC_APB1ENR_PWREN;
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/* HSI is selected as new source without touching the other fields in
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CFGR. Clearing the register has to be postponed after HSI is the
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new source.*/
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RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */
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RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
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; /* Wait until HSI is selected. */
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/* Core voltage setup.*/
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while ((PWR->CSR & PWR_CSR_VOSF) != 0)
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; /* Waits until regulator is stable. */
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PWR->CR = STM32_VOS;
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while ((PWR->CSR & PWR_CSR_VOSF) != 0)
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; /* Waits until regulator is stable. */
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/* Registers finally cleared to reset values.*/
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RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
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RCC->CFGR = 0; /* CFGR reset value. */
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/* Initial clocks setup and wait for MSI stabilization, the MSI clock is
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always enabled because it is the fallback clock when PLL the fails.
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Trim fields are not altered from reset values.*/
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RCC->CFGR = 0;
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RCC->ICSCR = (RCC->ICSCR & ~STM32_MSIRANGE_MASK) | STM32_MSIRANGE;
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RCC->CR = RCC_CR_MSION;
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while ((RCC->CR & RCC_CR_MSIRDY) == 0)
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; /* Waits until MSI is stable. */
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#if STM32_HSI16_ENABLED
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/* HSI activation.*/
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RCC->CR |= RCC_CR_HSION;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0)
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; /* Waits until HSI16 is stable. */
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#endif
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#if STM32_HSE_ENABLED
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/* HSE activation.*/
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#if defined(STM32_HSE_BYPASS)
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/* HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
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#else
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/* No HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEBYP;
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#endif
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/* HSE activation.*/
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RCC->CR |= RCC_CR_HSEON;
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#endif
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while (!(RCC->CR & RCC_CR_HSERDY))
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while ((RCC->CR & RCC_CR_HSERDY) == 0)
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; /* Waits until HSE is stable. */
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#endif
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#if STM32_HSI14_ENABLED
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/* HSI14 activation.*/
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RCC->CR2 |= RCC_CR2_HSI14ON;
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while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
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; /* Waits until HSI14 is stable. */
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#endif
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#if STM32_HSI48_ENABLED
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/* HSI48 activation.*/
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RCC->CR2 |= RCC_CR2_HSI48ON;
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while (!(RCC->CR2 & RCC_CR2_HSI48RDY))
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; /* Waits until HSI48 is stable. */
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#endif
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR |= RCC_CSR_LSION;
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@ -187,35 +176,50 @@ void stm32_clock_init(void) {
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; /* Waits until LSI is stable. */
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#endif
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/* Clock settings.*/
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RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
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STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
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RCC->CFGR2 = STM32_PREDIV;
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RCC->CFGR3 = STM32_ADCSW | STM32_USBSW | STM32_CECSW |
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STM32_I2C1SW | STM32_USART1SW;
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#if STM32_LSE_ENABLED
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/* LSE activation, have to unlock the register.*/
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if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
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PWR->CR |= PWR_CR_DBP;
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RCC->CSR |= RCC_CSR_LSEON;
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PWR->CR &= ~PWR_CR_DBP;
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}
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while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
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; /* Waits until LSE is stable. */
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->CFGR |= STM32_PLLDIV | STM32_PLLMUL | STM32_PLLSRC;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#endif
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/* Flash setup and final clock selection. */
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FLASH->ACR = STM32_FLASHBITS;
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CR |= STM32_RTCPRE;
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RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
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STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
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RCC->CSR |= STM32_RTCSEL;
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/* Switching to the configured clock source if it is different from HSI.*/
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#if (STM32_SW != STM32_SW_HSI)
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/* Switches clock source.*/
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RCC->CFGR |= STM32_SW;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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; /* Waits selection complete. */
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/* Flash setup and final clock selection.*/
|
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#if defined(STM32_FLASHBITS)
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FLASH->ACR = STM32_FLASHBITS;
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#endif
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/* Switching to the configured clock source if it is different from MSI.*/
|
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#if (STM32_SW != STM32_SW_MSI)
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RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
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;
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#endif
|
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#endif /* STM32_NO_INIT */
|
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|
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/* Peripherals clock sources setup.*/
|
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RCC->CCIPR = STM32_HSI48SEL;
|
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|
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
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among multiple drivers.*/
|
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rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
|
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#endif /* !STM32_NO_INIT */
|
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}
|
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|
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/** @} */
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|
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@ -73,6 +73,14 @@
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#endif
|
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/** @} */
|
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|
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/**
|
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* @brief Sub-family identifier.
|
||||
*/
|
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#if !defined(STM32L0XX) || defined(__DOXYGEN__)
|
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#define STM32L0XX
|
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#endif
|
||||
/** @} */
|
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|
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/**
|
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* @name Internal clock sources
|
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* @{
|
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|
|
@ -249,8 +257,8 @@
|
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#define STM32_I2C3SEL_HSI16 (2 << 16) /**< I2C3 clock is HSI16. */
|
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|
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#define STM32_HSI48SEL_MASK (1 << 27) /**< HSI48SEL clock source mask.*/
|
||||
#define STM32_HSI48SEL_USBPLL (0 << 27) /**< HSI48 clock is USB PLL. */
|
||||
#define STM32_HSI48SEL_RC48 (1 << 27) /**< HSI48 clock is RC28. */
|
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#define STM32_HSI48SEL_USBPLL (0 << 27) /**< USB48 clock is PLL/2. */
|
||||
#define STM32_HSI48SEL_HSI48 (1 << 27) /**< USB48 clock is HSI48. */
|
||||
/** @} */
|
||||
|
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/*===========================================================================*/
|
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|
|
@ -424,7 +432,7 @@
|
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* @brief RTC/LCD clock source.
|
||||
*/
|
||||
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSE
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
|
@ -433,6 +441,13 @@
|
|||
#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCPRE STM32_RTCPRE_DIV2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @bief USB/RNG clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSI48SEL) || defined(__DOXYGEN__)
|
||||
#define STM32_HSI48SEL STM32_HSI48SEL_HSI48
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -768,24 +783,6 @@
|
|||
#error "invalid STM32_MSIRANGE value specified"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock source.
|
||||
*/
|
||||
|
|
@ -883,10 +880,12 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO divider clock.
|
||||
* @brief MCO selector clock.
|
||||
*/
|
||||
#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
|
||||
#define STM32_MCODIVCLK 0
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
|
||||
#define STM32_MCODIVCLK STM32_SYSCLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
|
||||
#define STM32_MCODIVCLK STM32_HSI16CLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_MSI
|
||||
|
|
@ -899,6 +898,8 @@
|
|||
#define STM32_MCODIVCLK STM32_LSICLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_LSE
|
||||
#define STM32_MCODIVCLK STM32_LSECLK
|
||||
#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
|
||||
#define STM32_MCODIVCLK STM32_HSI48CLK
|
||||
#else
|
||||
#error "invalid STM32_MCOSEL value specified"
|
||||
#endif
|
||||
|
|
@ -951,12 +952,18 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief USB frequency.
|
||||
* @brief USB/RNG frequency.
|
||||
*/
|
||||
#if (STM32_HSI48SEL == STM32_HSI48SEL_HSI48) || defined(__DOXYGEN__)
|
||||
#define STM32_USBCLK STM32_HSI48CLK
|
||||
#elif STM32_HSI48SEL == STM32_HSI48SEL_USBPLL
|
||||
#define STM32_USBCLK (STM32_PLLVCO / 2)
|
||||
#else
|
||||
#error "invalid STM32_HSI48SEL value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Timers 2, 3, 4, 6, 7 clock.
|
||||
* @brief Timers LPTIM1, TIM2, TIM6 clock.
|
||||
*/
|
||||
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
|
||||
|
|
@ -965,7 +972,7 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief Timers 9, 10, 11 clock.
|
||||
* @brief Timers TIM21, TIM22 clock.
|
||||
*/
|
||||
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
|
||||
|
|
@ -977,10 +984,11 @@
|
|||
* @brief Flash settings.
|
||||
*/
|
||||
#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
|
||||
#define STM32_FLASHBITS1 0x00000000
|
||||
#define STM32_FLASHBITS 0
|
||||
#else
|
||||
#define STM32_FLASHBITS1 0x00000004
|
||||
#define STM32_FLASHBITS2 0x00000007
|
||||
#define STM32_FLASHBITS (FLASH_ACR_PRE_READ | \
|
||||
FLASH_ACR_PRFTEN | \
|
||||
FLASH_ACR_LATENCY)
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
@ -997,8 +1005,8 @@
|
|||
|
||||
/* Various helpers.*/
|
||||
#include "nvic.h"
|
||||
#include "stm32_isr.h"
|
||||
#include "stm32_dma.h"
|
||||
//#include "stm32_isr.h"
|
||||
//#include "stm32_dma.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -0,0 +1,692 @@
|
|||
/*
|
||||
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32L0xx/stm32_rcc.h
|
||||
* @brief RCC helper driver header.
|
||||
* @note This file requires definitions from the ST header file
|
||||
* @p stm32l0xx.h.
|
||||
*
|
||||
* @addtogroup STM32L1xx_RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_RCC_
|
||||
#define _STM32_RCC_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Generic RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAPB1(mask, lp) { \
|
||||
RCC->APB1ENR |= (mask); \
|
||||
if (lp) \
|
||||
RCC->APB1SMENR |= (mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAPB1(mask, lp) { \
|
||||
RCC->APB1ENR &= ~(mask); \
|
||||
if (lp) \
|
||||
RCC->APB1SMENR &= ~(mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the APB1 bus.
|
||||
*
|
||||
* @param[in] mask APB1 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAPB1(mask) { \
|
||||
RCC->APB1RSTR |= (mask); \
|
||||
RCC->APB1RSTR = 0; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAPB2(mask, lp) { \
|
||||
RCC->APB2ENR |= (mask); \
|
||||
if (lp) \
|
||||
RCC->APB2SMENR |= (mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAPB2(mask, lp) { \
|
||||
RCC->APB2ENR &= ~(mask); \
|
||||
if (lp) \
|
||||
RCC->APB2SMENR &= ~(mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the APB2 bus.
|
||||
*
|
||||
* @param[in] mask APB2 peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAPB2(mask) { \
|
||||
RCC->APB2RSTR |= (mask); \
|
||||
RCC->APB2RSTR = 0; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the clock of one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableAHB(mask, lp) { \
|
||||
RCC->AHBENR |= (mask); \
|
||||
if (lp) \
|
||||
RCC->AHBSMENR |= (mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the clock of one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableAHB(mask, lp) { \
|
||||
RCC->AHBENR &= ~(mask); \
|
||||
if (lp) \
|
||||
RCC->AHBSMENR &= ~(mask); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resets one or more peripheral on the AHB bus.
|
||||
*
|
||||
* @param[in] mask AHB peripherals mask
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetAHB(mask) { \
|
||||
RCC->AHBRSTR |= (mask); \
|
||||
RCC->AHBRSTR = 0; \
|
||||
}
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ADC peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the ADC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the ADC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the ADC1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DAC peripheral specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the DAC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the DAC1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the DAC1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DMA peripheral specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the DMA1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the DMA1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the DMA1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PWR interface specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the PWR interface clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables PWR interface clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the PWR interface.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the I2C1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the I2C1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the I2C1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the I2C2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the I2C2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the SPI1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the SPI1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the SPI1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the SPI2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the SPI2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the SPI2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name TIM peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the TIM2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM3 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM4 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM4 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM4 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM9 peripheral clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM9 peripheral clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM9 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM10 peripheral clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM10 peripheral clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM10 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the TIM10 peripheral clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the TIM11 peripheral clock.
|
||||
* @note The @p lp parameter is ignored in this family.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the TIM11 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST)
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name USART/UART peripherals specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the USART1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USART1 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USART1 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the USART2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USART2 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USART2 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
|
||||
|
||||
/**
|
||||
* @brief Enables the USART3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USART3 peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USART3 peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name USB peripheral specific RCC operations
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Enables the USB peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the USB peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Resets the USB peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32_RCC_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -77,11 +77,11 @@
|
|||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
|
||||
RCC_IOPENR_GPIOBEN | \
|
||||
RCC_IOPENR_GPIOCEN | \
|
||||
RCC_IOPENR_GPIODEN | \
|
||||
RCC_IOPENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
|
|
@ -233,11 +233,11 @@
|
|||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
|
||||
RCC_IOPENR_GPIOBEN | \
|
||||
RCC_IOPENR_GPIOCEN | \
|
||||
RCC_IOPENR_GPIODEN | \
|
||||
RCC_IOPENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
|
|
@ -393,11 +393,11 @@
|
|||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \
|
||||
RCC_IOPENR_GPIOBEN | \
|
||||
RCC_IOPENR_GPIOCEN | \
|
||||
RCC_IOPENR_GPIODEN | \
|
||||
RCC_IOPENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
|
|
|
|||
|
|
@ -77,6 +77,12 @@
|
|||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOEEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
|
|
@ -248,6 +254,14 @@
|
|||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
|
||||
RCC_AHBENR_GPIOBEN | \
|
||||
RCC_AHBENR_GPIOCEN | \
|
||||
RCC_AHBENR_GPIODEN | \
|
||||
RCC_AHBENR_GPIOEEN | \
|
||||
RCC_AHBENR_GPIOFEN | \
|
||||
RCC_AHBENR_GPIOGEN | \
|
||||
RCC_AHBENR_GPIOHEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
|
|
|
|||
Loading…
Reference in New Issue