Removed old style initializers from the STM32 DACv1 driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9090 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -83,65 +83,65 @@ DACDriver DACD4;
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#if STM32_DAC_USE_DAC1_CH1 == TRUE
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static const dacparams_t dma1_ch1_params = {
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dac: DAC1,
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dataoffset: 0U,
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regshift: 0U,
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regmask: 0xFFFF0000U,
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dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC_DAC1_CH1_IRQ_PRIORITY
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.dac = DAC1,
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.dataoffset = 0U,
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.regshift = 0U,
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.regmask = 0xFFFF0000U,
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.dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH1_DMA_STREAM),
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.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC1_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC1_CH1_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC1_CH2 == TRUE
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static const dacparams_t dma1_ch2_params = {
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dac: DAC1,
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dataoffset: CHANNEL_DATA_OFFSET,
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regshift: 16U,
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regmask: 0x0000FFFFU,
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dma: STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC_DAC1_CH2_IRQ_PRIORITY
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.dac = DAC1,
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.dataoffset = CHANNEL_DATA_OFFSET,
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.regshift = 16U,
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.regmask = 0x0000FFFFU,
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.dma = STM32_DMA_STREAM(STM32_DAC_DAC1_CH2_DMA_STREAM),
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.dmamode = STM32_DMA_CR_CHSEL(DAC1_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC1_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC1_CH2_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC2_CH1 == TRUE
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static const dacparams_t dma2_ch1_params = {
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dac: DAC2,
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dataoffset: 0U,
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regshift: 0U,
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regmask: 0xFFFF0000U,
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dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC_DAC2_CH1_IRQ_PRIORITY
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.dac = DAC2,
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.dataoffset = 0U,
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.regshift = 0U,
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.regmask = 0xFFFF0000U,
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.dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH1_DMA_STREAM),
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.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH1_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC2_CH1_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC2_CH1_IRQ_PRIORITY
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};
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#endif
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#if STM32_DAC_USE_DAC2_CH2 == TRUE
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static const dacparams_t dma1_ch2_params = {
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dac: DAC2,
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dataoffset: CHANNEL_DATA_OFFSET,
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regshift: 16U,
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regmask: 0x0000FFFFU,
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dma: STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
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dmamode: STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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dmairqprio: STM32_DAC_DAC2_CH2_IRQ_PRIORITY
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.dac = DAC2,
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.dataoffset = CHANNEL_DATA_OFFSET,
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.regshift = 16U,
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.regmask = 0x0000FFFFU,
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.dma = STM32_DMA_STREAM(STM32_DAC_DAC2_CH2_DMA_STREAM),
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.dmamode = STM32_DMA_CR_CHSEL(DAC2_CH2_DMA_CHANNEL) |
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STM32_DMA_CR_PL(STM32_DAC_DAC2_CH2_DMA_PRIORITY) |
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STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_DIR_M2P |
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STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | STM32_DMA_CR_HTIE |
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STM32_DMA_CR_TCIE,
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.dmairqprio = STM32_DAC_DAC2_CH2_IRQ_PRIORITY
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};
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#endif
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