git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@147 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
2c91f58d0f
commit
b1bba5833e
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@ -62,14 +62,13 @@ UDEFS =
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UADEFS =
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# List ARM-mode C source files here
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ASRC = chcore.c \
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ASRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \
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../../ports/ARM7-LPC214x/GCC/vic.c \
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../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \
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../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \
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../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \
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../../src/chserial.c \
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../../ports/ARM7-LPC214x/GCC/vic.c \
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main.c
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board.c main.c
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# List THUMB-mode C sources here
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# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is
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@ -77,7 +76,7 @@ ASRC = chcore.c \
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TSRC =
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# List ASM source files here
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ASMSRC = crt0.s chcore2.s
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ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC
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@ -160,7 +159,7 @@ $(TOBJS) : %.o : %.c
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$(ASMOBJS) : %.o : %.s
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@echo
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$(AS) -c $(ASFLAGS) $< -o $@
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$(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@
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%elf: $(OBJS)
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@echo
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@ -67,16 +67,16 @@ ASRC =
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# List THUMB-mode C sources here
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# NOTE: If any module is compiled in thumb mode then -mthumb-interwork is
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# enabled for all modules and that lowers performance.
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TSRC = chcore.c \
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TSRC = ../../ports/ARM7-LPC214x/GCC/chcore.c \
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../../ports/ARM7-LPC214x/GCC/vic.c \
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../../src/chinit.c ../../src/chdebug.c ../../src/chlists.c ../../src/chdelta.c \
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../../src/chschd.c ../../src/chthreads.c ../../src/chsem.c ../../src/chmtx.c \
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../../src/chevents.c ../../src/chmsg.c ../../src/chsleep.c ../../src/chqueues.c \
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../../src/chserial.c \
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../../ports/ARM7-LPC214x/GCC/vic.c \
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main.c
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board.c main.c
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# List ASM source files here
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ASMSRC = crt0.s chcore2.s
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ASMSRC = ../../ports/ARM7-LPC214x/GCC/crt0.s
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# List all user directories here
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UINCDIR = ../../src/include ../../src/lib ../../ports/ARM7-LPC214x/GCC
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@ -159,7 +159,7 @@ $(TOBJS) : %.o : %.c
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$(ASMOBJS) : %.o : %.s
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@echo
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$(AS) -c $(ASFLAGS) $< -o $@
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$(AS) -c $(ASFLAGS) -I . $(INCDIR) $< -o $@
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%elf: $(OBJS)
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@echo
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@ -1,203 +0,0 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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#include "lpc214x.h"
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#include "vic.h"
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//#include "lpc214x_serial.h"
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//#include "lpc214x_ssp.h"
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//#include "mmcsd.h"
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//#include "buzzer.h"
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extern void IrqHandler(void);
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extern void T0IrqHandler(void);
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#define VAL_TC0_PRESCALER 0
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/*
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* Pins configuration for Olimex LPC-P2148.
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*
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* PINSEL0
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* P0 P0 P0 P0 P0 P0 RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD
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* 15 14 13 12 11 10 1 1 L0 I0 O0 0 0 0 0 0
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* 00 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01
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* IN IN OUT OUT OUT OUT -- -- -- -- -- -- -- -- -- --
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* 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0
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*
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* PINSEL1
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* P0 AD P0 P0 -- -- AO -- VB P0 P0 P0 MOS MIS SCK P0
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* 31 03 29 28 -- -- UT -- US 22 21 20 I1 O1 1 16
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* 00 01 00 00 00 00 10 00 01 00 00 00 10 10 10 00
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* OUT -- OUT OUT -- -- -- -- -- OUT OUT OUT -- -- -- IN
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* 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0
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*
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* PINSEL2
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* -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP DBG --
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* -- -- -- -- -- -- -- -- -- -- -- -- -- -- IO --
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* 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0 1 00
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* -- -- -- -- -- -- -- -- -- -- -- -- -- -- IN -- --
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*/
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#define VAL_PINSEL0 0x00055555
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#define VAL_PINSEL1 0x100840A8
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#define VAL_PINSEL2 0x00000004
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#define VAL_FIO0DIR 0xB0703C00
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#define VAL_FIO1DIR 0x00000000
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/*
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* Hardware initialization goes here.
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* NOTE: Interrupts are still disabled.
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*/
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void hwinit(void) {
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/*
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* All peripherals clock disabled by default in order to save power.
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*/
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PCONP = PCRTC | PCTIM0;
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/*
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* MAM setup.
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*/
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MAMTIM = 0x3; /* 3 cycles for flash accesses. */
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MAMCR = 0x2; /* MAM fully enabled. */
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/*
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* PLL setup for Fosc=12MHz and CCLK=48MHz.
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* P=2 M=3.
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*/
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PLL *pll = PLLBase;
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pll->PLL0_CFG = 0x23; /* P and M values. */
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pll->PLL0_CON = 0x1; /* Enalbles the PLL 0. */
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pll->PLL0_FEED = 0xAA;
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pll->PLL0_FEED = 0x55;
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while (!(pll->PLL0_STAT & 0x400))
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; /* Wait for PLL lock. */
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pll->PLL0_CON = 0x3; /* Connects the PLL. */
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pll->PLL0_FEED = 0xAA;
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pll->PLL0_FEED = 0x55;
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/*
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* VPB setup.
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* PCLK = CCLK / 4.
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*/
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VPBDIV = VPD_D4;
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/*
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* I/O pins configuration.
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*/
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PINSEL0 = VAL_PINSEL0;
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PINSEL1 = VAL_PINSEL1;
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PINSEL2 = VAL_PINSEL2;
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IO0DIR = VAL_FIO0DIR;
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IO0SET = 0xFFFFFFFF;
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IO1DIR = VAL_FIO1DIR;
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IO1SET = 0xFFFFFFFF;
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/*
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* Interrupt vectors assignment.
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*/
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InitVIC();
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VICDefVectAddr = (IOREG32)IrqHandler;
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/*
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* System Timer initialization, 1ms intervals.
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*/
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SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
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VICIntEnable = INTMASK(SOURCE_Timer0);
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TC *timer = T0Base;
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timer->TC_PR = VAL_TC0_PRESCALER;
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timer->TC_MR0 = (PCLK / CH_FREQUENCY) / (VAL_TC0_PRESCALER + 1);
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timer->TC_MCR = 3; /* Interrupt and clear TC on match MR0. */
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timer->TC_TCR = 2; /* Reset counter and prescaler. */
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timer->TC_TCR = 1; /* Timer enabled. */
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/*
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* Other subsystems.
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*/
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// InitSerial(1, 2);
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// InitSSP();
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// InitMMC();
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// InitBuzzer();
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}
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/*
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* System idle thread loop.
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*/
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void _IdleThread(void *p) {
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while (TRUE) {
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// Note, it is disabled because it causes trouble with the JTAG probe.
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// Enable it in the final code only.
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// PCON = 1;
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}
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}
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/*
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* System console message (not implemented).
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*/
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void chSysPuts(char *msg) {
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}
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/*
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* Non-vectored IRQs handling here.
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*/
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__attribute__((naked, weak))
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void IrqHandler(void) {
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asm(".code 32 \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t");
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#ifdef THUMB
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t");
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VICVectAddr = 0;
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asm("ldr r0, =IrqCommon \n\t" \
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"bx r0 \n\t");
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#else
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VICVectAddr = 0;
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asm("b IrqCommon \n\t");
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#endif
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}
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/*
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* Timer 0 IRQ handling here.
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*/
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__attribute__((naked, weak))
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void T0IrqHandler(void) {
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asm(".code 32 \n\t" \
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"stmfd sp!, {r0-r3, r12, lr} \n\t");
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#ifdef THUMB
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asm("add r0, pc, #1 \n\t" \
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"bx r0 \n\t" \
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".code 16 \n\t");
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T0IR = 1; /* Clear interrupt on match MR0. */
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chSysTimerHandlerI();
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VICVectAddr = 0;
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asm("ldr r0, =IrqCommon \n\t" \
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"bx r0 \n\t");
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#else
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T0IR = 1; /* Clear interrupt on match MR0. */
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chSysTimerHandlerI();
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VICVectAddr = 0;
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asm("b IrqCommon \n\t");
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#endif
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}
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@ -1,116 +0,0 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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|
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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/*
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* The following values are implementation dependent. You may change them in
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* order to match your HW.
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*/
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#define FOSC 12000000
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#define CCLK 48000000
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#define PCLK 12000000
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typedef void *regarm;
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/*
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* Interrupt saved context.
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*/
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struct extctx {
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regarm spsr_irq;
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regarm lr_irq;
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regarm r0;
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regarm r1;
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regarm r2;
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regarm r3;
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regarm r12;
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};
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/*
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* System saved context.
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*/
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struct intctx {
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regarm r4;
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regarm r5;
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regarm r6;
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#ifndef CH_CURRP_REGISTER_CACHE
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regarm r7;
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#endif
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regarm r8;
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regarm r9;
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regarm r10;
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regarm r11;
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regarm lr;
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};
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/*
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* Port dependent part of the Thread structure, you may add fields in
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* this structure.
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*/
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typedef struct {
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struct intctx *r13;
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} Context;
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/*
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* Platform dependent part of the \p chThdCreate() API.
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*/
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#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
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tp->p_ctx.r13 = (struct intctx *)((BYTE8 *)workspace + \
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wsize - \
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sizeof(struct intctx)); \
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tp->p_ctx.r13->r4 = pf; \
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tp->p_ctx.r13->r5 = arg; \
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tp->p_ctx.r13->lr = threadstart; \
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}
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#ifdef THUMB
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extern void chSysLock(void);
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extern void chSysUnlock(void);
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#else /* !THUMB */
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#define chSysLock() asm("msr CPSR_c, #0x9F")
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#define chSysUnlock() asm("msr CPSR_c, #0x1F")
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#endif /* THUMB */
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#ifdef THUMB
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#define INT_REQUIRED_STACK 0x10
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#else /* !THUMB */
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#define INT_REQUIRED_STACK 0
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#endif /* THUMB */
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#define StackAlign(n) ((((n) - 1) | 3) + 1)
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#define UserStackSize(n) StackAlign(sizeof(Thread) + \
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sizeof(struct intctx) + \
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sizeof(struct extctx) + \
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(n) + \
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INT_REQUIRED_STACK)
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#define WorkingArea(s, n) ULONG32 s[UserStackSize(n) >> 2];
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|
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/* It requires zero bytes, but better be safe.*/
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#define IDLE_THREAD_STACK_SIZE 8
|
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void _IdleThread(void *p) __attribute__((noreturn));
|
||||
|
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void chSysHalt(void) __attribute__((noreturn));
|
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void chSysSwitchI(Context *oldp, Context *newp);
|
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void chSysPuts(char *msg);
|
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void threadstart(void);
|
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void DefFiqHandler(void);
|
||||
void DefIrqHandler(void);
|
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void SpuriousHandler(void);
|
||||
|
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#endif /* _CHCORE_H_ */
|
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|
|
@ -1,206 +0,0 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "chconf.h"
|
||||
|
||||
.set MODE_USR, 0x10
|
||||
.set MODE_FIQ, 0x11
|
||||
.set MODE_IRQ, 0x12
|
||||
.set MODE_SVC, 0x13
|
||||
.set MODE_ABT, 0x17
|
||||
.set MODE_UND, 0x1B
|
||||
.set MODE_SYS, 0x1F
|
||||
|
||||
.equ I_BIT, 0x80
|
||||
.equ F_BIT, 0x40
|
||||
|
||||
.text
|
||||
.code 32
|
||||
.balign 4
|
||||
|
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.globl threadstart
|
||||
threadstart:
|
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msr CPSR_c, #MODE_SYS
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||||
#ifndef THUMB_NO_INTERWORKING
|
||||
mov r0, r5
|
||||
mov lr, pc
|
||||
bx r4
|
||||
bl chThdExit
|
||||
#else
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||||
add r0, pc, #1
|
||||
bx r0
|
||||
.code 16
|
||||
mov r0, r5
|
||||
bl jmpr4
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||||
bl chThdExit
|
||||
jmpr4: bx r4
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||||
.code 32
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||||
#endif
|
||||
|
||||
.weak UndHandler
|
||||
.globl UndHandler
|
||||
UndHandler:
|
||||
|
||||
.weak SwiHandler
|
||||
.globl SwiHandler
|
||||
SwiHandler:
|
||||
|
||||
.weak PrefetchHandler
|
||||
.globl PrefetchHandler
|
||||
PrefetchHandler:
|
||||
|
||||
.weak AbortHandler
|
||||
.globl AbortHandler
|
||||
AbortHandler:
|
||||
|
||||
.weak FiqHandler
|
||||
.globl FiqHandler
|
||||
FiqHandler:
|
||||
b halt32
|
||||
|
||||
.weak chSysHalt
|
||||
#ifdef THUMB_NO_INTERWORKING
|
||||
.code 16
|
||||
.globl chSysHalt
|
||||
chSysHalt:
|
||||
mov r0, pc
|
||||
bx r0
|
||||
.code 32
|
||||
#else
|
||||
.globl chSysHalt
|
||||
chSysHalt:
|
||||
#endif
|
||||
halt32:
|
||||
mrs r0, CPSR
|
||||
orr r0, #I_BIT | F_BIT
|
||||
msr CPSR_c, r0
|
||||
.loop: b .loop
|
||||
|
||||
#ifdef THUMB
|
||||
.globl chSysLock
|
||||
chSysLock:
|
||||
msr CPSR_c, #0x9F
|
||||
bx lr
|
||||
|
||||
.globl chSysUnlock
|
||||
chSysUnlock:
|
||||
msr CPSR_c, #0x1F
|
||||
bx lr
|
||||
#endif
|
||||
|
||||
.globl chSysSwitchI
|
||||
chSysSwitchI:
|
||||
#ifdef CH_CURRP_REGISTER_CACHE
|
||||
stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
|
||||
str sp, [r0, #0]
|
||||
ldr sp, [r1, #0]
|
||||
#ifdef THUMB
|
||||
ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
|
||||
bx lr
|
||||
#else
|
||||
ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc}
|
||||
#endif
|
||||
#else
|
||||
stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
|
||||
str sp, [r0, #0]
|
||||
ldr sp, [r1, #0]
|
||||
#ifdef THUMB
|
||||
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
|
||||
bx lr
|
||||
#else
|
||||
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
|
||||
#endif
|
||||
#endif /* CH_CURRP_REGISTER_CACHE */
|
||||
|
||||
/*
|
||||
* Common exit point for all IRQ routines, it performs the rescheduling if
|
||||
* required.
|
||||
* System stack frame structure after a context switch in the
|
||||
* interrupt handler:
|
||||
*
|
||||
* High +------------+
|
||||
* | LR_USR | -+
|
||||
* | R12 | |
|
||||
* | R3 | |
|
||||
* | R2 | | External context: IRQ handler frame
|
||||
* | R1 | |
|
||||
* | R0 | |
|
||||
* | LR_IRQ | | (user code return address)
|
||||
* | SPSR | -+ (user code status)
|
||||
* | .... | <- mk_DoRescheduleI() stack frame, optimize it for space
|
||||
* | LR | -+ (system code return address)
|
||||
* | R11 | |
|
||||
* | R10 | |
|
||||
* | R9 | |
|
||||
* | R8 | | Internal context: mk_SwitchI() frame
|
||||
* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
|
||||
* | R6 | |
|
||||
* | R5 | |
|
||||
* SP-> | R4 | -+
|
||||
* Low +------------+
|
||||
*/
|
||||
#ifdef THUMB_NO_INTERWORKING
|
||||
.code 16
|
||||
.globl IrqCommon
|
||||
IrqCommon:
|
||||
bl chSchRescRequiredI
|
||||
mov lr, pc
|
||||
bx lr
|
||||
.code 32
|
||||
#else
|
||||
.globl IrqCommon
|
||||
IrqCommon:
|
||||
bl chSchRescRequiredI
|
||||
#endif
|
||||
cmp r0, #0 // Simply returns if a
|
||||
ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not
|
||||
subeqs pc, lr, #4 // required.
|
||||
|
||||
// Saves the IRQ mode registers in the system stack.
|
||||
ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty.
|
||||
msr CPSR_c, #MODE_SYS | I_BIT
|
||||
stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack.
|
||||
msr CPSR_c, #MODE_IRQ | I_BIT
|
||||
mrs r0, SPSR
|
||||
mov r1, lr
|
||||
msr CPSR_c, #MODE_SYS | I_BIT
|
||||
stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
|
||||
|
||||
// Context switch.
|
||||
#ifdef THUMB_NO_INTERWORKING
|
||||
add r0, pc, #1
|
||||
bx r0
|
||||
.code 16
|
||||
bl chSchDoRescheduleI
|
||||
mov lr, pc
|
||||
bx lr
|
||||
.code 32
|
||||
#else
|
||||
bl chSchDoRescheduleI
|
||||
#endif
|
||||
|
||||
// Re-establish the IRQ conditions again.
|
||||
ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
|
||||
msr CPSR_c, #MODE_IRQ | I_BIT
|
||||
msr SPSR_fsxc, r0
|
||||
mov lr, r1
|
||||
msr CPSR_c, #MODE_SYS | I_BIT
|
||||
ldmfd sp!, {r0-r3, r12, lr}
|
||||
msr CPSR_c, #MODE_IRQ | I_BIT
|
||||
subs pc, lr, #4
|
||||
|
|
@ -1,149 +0,0 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Generic ARM startup file for ChibiOS/RT.
|
||||
*/
|
||||
|
||||
.extern _main
|
||||
|
||||
.set MODE_USR, 0x10
|
||||
.set MODE_FIQ, 0x11
|
||||
.set MODE_IRQ, 0x12
|
||||
.set MODE_SVC, 0x13
|
||||
.set MODE_ABT, 0x17
|
||||
.set MODE_UND, 0x1B
|
||||
.set MODE_SYS, 0x1F
|
||||
|
||||
.equ I_BIT, 0x80
|
||||
.equ F_BIT, 0x40
|
||||
|
||||
.text
|
||||
.code 32
|
||||
.balign 4
|
||||
/*
|
||||
* System entry points.
|
||||
*/
|
||||
_start:
|
||||
b ResetHandler
|
||||
ldr pc, _undefined
|
||||
ldr pc, _swi
|
||||
ldr pc, _prefetch
|
||||
ldr pc, _abort
|
||||
nop
|
||||
ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */
|
||||
ldr pc, _fiq
|
||||
|
||||
_undefined:
|
||||
.word UndHandler
|
||||
_swi:
|
||||
.word SwiHandler
|
||||
_prefetch:
|
||||
.word PrefetchHandler
|
||||
_abort:
|
||||
.word AbortHandler
|
||||
_fiq:
|
||||
.word FiqHandler
|
||||
.word 0
|
||||
.word 0
|
||||
|
||||
/*
|
||||
* Reset handler.
|
||||
*/
|
||||
ResetHandler:
|
||||
/*
|
||||
* Stack pointers initialization.
|
||||
*/
|
||||
ldr r0, =__ram_end__
|
||||
/* Undefined */
|
||||
msr CPSR_c, #MODE_UND | I_BIT | F_BIT
|
||||
mov sp, r0
|
||||
ldr r1, =__und_stack_size__
|
||||
sub r0, r0, r1
|
||||
/* Abort */
|
||||
msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
|
||||
mov sp, r0
|
||||
ldr r1, =__abt_stack_size__
|
||||
sub r0, r0, r1
|
||||
/* FIQ */
|
||||
msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
|
||||
mov sp, r0
|
||||
ldr r1, =__fiq_stack_size__
|
||||
sub r0, r0, r1
|
||||
/* IRQ */
|
||||
msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
|
||||
mov sp, r0
|
||||
ldr r1, =__irq_stack_size__
|
||||
sub r0, r0, r1
|
||||
/* Supervisor */
|
||||
msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
|
||||
mov sp, r0
|
||||
ldr r1, =__svc_stack_size__
|
||||
sub r0, r0, r1
|
||||
/* System */
|
||||
msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
|
||||
mov sp, r0
|
||||
// ldr r1, =__sys_stack_size__
|
||||
// sub r0, r0, r1
|
||||
/*
|
||||
* Data initialization.
|
||||
* NOTE: It assumes that the DATA size is a multiple of 4.
|
||||
*/
|
||||
ldr r1, =_textdata
|
||||
ldr r2, =_data
|
||||
ldr r3, =_edata
|
||||
dataloop:
|
||||
cmp r2, r3
|
||||
ldrlo r0, [r1], #4
|
||||
strlo r0, [r2], #4
|
||||
blo dataloop
|
||||
/*
|
||||
* BSS initialization.
|
||||
* NOTE: It assumes that the BSS size is a multiple of 4.
|
||||
*/
|
||||
mov r0, #0
|
||||
ldr r1, =_bss_start
|
||||
ldr r2, =_bss_end
|
||||
bssloop:
|
||||
cmp r1, r2
|
||||
strlo r0, [r1], #4
|
||||
blo bssloop
|
||||
/*
|
||||
* Application-provided HW initialization routine.
|
||||
*/
|
||||
#ifndef THUMB_NO_INTERWORKING
|
||||
bl hwinit
|
||||
/*
|
||||
* main(0, NULL).
|
||||
*/
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
bl main
|
||||
bl chSysHalt
|
||||
#else
|
||||
add r0, pc, #1
|
||||
bx r0
|
||||
.code 16
|
||||
bl hwinit
|
||||
mov r0, #0
|
||||
mov r1, r0
|
||||
bl main
|
||||
bl chSysHalt
|
||||
.code 32
|
||||
#endif
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _CHTYPES_H_
|
||||
#define _CHTYPES_H_
|
||||
|
||||
/*
|
||||
* Generic types often dependant on the compiler.
|
||||
*/
|
||||
#define BOOL char
|
||||
#define BYTE8 unsigned char
|
||||
#define SBYTE8 char
|
||||
#define WORD16 short
|
||||
#define UWORD16 unsigned short
|
||||
#define LONG32 int
|
||||
#define ULONG32 unsigned int
|
||||
|
||||
typedef BYTE8 t_tmode;
|
||||
typedef BYTE8 t_tstate;
|
||||
typedef UWORD16 t_tid;
|
||||
typedef ULONG32 t_prio;
|
||||
typedef LONG32 t_msg;
|
||||
typedef LONG32 t_eventid;
|
||||
typedef ULONG32 t_eventmask;
|
||||
typedef ULONG32 t_time;
|
||||
typedef LONG32 t_cnt;
|
||||
typedef ULONG32 t_size;
|
||||
|
||||
#define INLINE inline
|
||||
|
||||
#endif /* _CHTYPES_H_ */
|
||||
Loading…
Reference in New Issue