From b36f9f55856979ae773c8c676c0f6723440e52a1 Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Mon, 23 May 2016 16:34:18 +0000 Subject: [PATCH] Fixed Bug #742 git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9507 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F4xx/hal_lld.h | 16 +++++----------- os/hal/ports/STM32/STM32F7xx/hal_lld.h | 6 ------ readme.txt | 1 + 3 files changed, 6 insertions(+), 17 deletions(-) diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index ade9e8b40..5883c99e4 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -425,17 +425,11 @@ #define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ #define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ -#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */ -#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */ -#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ -#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ - -#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ -#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ -#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ -#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable - prescaler used as RTC clock*/ +#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */ +#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */ +#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */ /** * @name RCC_PLLI2SCFGR register bits definitions diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index 913b7fce8..804119fda 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -270,12 +270,6 @@ #define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */ #define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */ -#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */ -#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */ -#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */ -#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable - prescaler used as RTC clock*/ - /** * @name RCC_PLLI2SCFGR register bits definitions * @{ diff --git a/readme.txt b/readme.txt index 11eded309..15646af5e 100644 --- a/readme.txt +++ b/readme.txt @@ -113,6 +113,7 @@ - RT: Merged RT4. - NIL: Merged NIL2. - NIL: Added STM32F7 demo. +- HAL: Removed unused macros in STM32F7xx and STM32F4xx hal_lld.h (bug #742). - HAL: Fixed Doxygen related macros in STM32F7xx, STM32L0xx and STM32L4xx lld files (bug #741). - HAL: Fixed bug in VREF enable/disable functions in ADCv3 driver