RCC fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13012 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
aaba157f93
commit
b384098490
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@ -314,27 +314,50 @@
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* @{
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*/
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/**
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* @brief Enables the ADC1/ADC2/ADC3 peripheral clock.
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* @brief Enables the ADC1/ADC2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC123(lp) rccEnableAHB2(RCC_AHB2ENR_ADCEN, lp)
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#define rccEnableADC12(lp) rccEnableAHB2(RCC_AHB2ENR_ADC12EN, lp)
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/**
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* @brief Disables the ADC1/ADC2/ADC3 peripheral clock.
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* @brief Disables the ADC1/ADC2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableADC123() rccDisableAHB2(RCC_AHB2ENR_ADCEN)
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#define rccDisableADC12() rccDisableAHB2(RCC_AHB2ENR_ADC12EN)
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/**
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* @brief Resets the ADC1/ADC2/ADC3 peripheral.
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* @brief Resets the ADC1/ADC2 peripheral.
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*
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* @api
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*/
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#define rccResetADC123() rccResetAHB2(RCC_AHB2RSTR_ADCRST)
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#define rccResetADC12() rccResetAHB2(RCC_AHB2RSTR_ADC12RST)
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/**
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* @brief Enables the ADC3/ADC4/ADC5 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableADC345(lp) rccEnableAHB2(RCC_AHB2ENR_ADC345EN, lp)
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/**
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* @brief Disables the ADC3/ADC4/ADC5 peripheral clock.
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*
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* @api
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*/
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#define rccDisableADC345() rccDisableAHB2(RCC_AHB2ENR_ADC345EN)
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/**
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* @brief Resets the ADC3/ADC4/ADC5 peripheral.
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*
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* @api
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*/
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#define rccResetADC345() rccResetAHB2(RCC_AHB2RSTR_ADC345RST)
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/** @} */
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/**
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@ -348,21 +371,90 @@
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*
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* @api
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*/
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#define rccEnableDAC1(lp) rccEnableAPB1R1(RCC_APB1ENR1_DAC1EN, lp)
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#define rccEnableDAC1(lp) rccEnableAHB2(RCC_AHB2ENR_DAC1EN, lp)
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/**
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* @brief Disables the DAC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC1() rccDisableAPB1R1(RCC_APB1ENR1_DAC1EN)
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#define rccDisableDAC1() rccDisableAHB2(RCC_AHB2ENR_DAC1EN)
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/**
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* @brief Resets the DAC1 peripheral.
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*
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* @api
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*/
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#define rccResetDAC1() rccResetAPB1R1(RCC_APB1RSTR1_DAC1RST)
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#define rccResetDAC1() rccResetAHB2(RCC_AHB2RSTR_DAC1RST)
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/**
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* @brief Enables the DAC2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDAC2(lp) rccEnableAHB2(RCC_AHB2ENR_DAC2EN, lp)
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/**
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* @brief Disables the DAC2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC2() rccDisableAHB2(RCC_AHB2ENR_DAC2EN)
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/**
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* @brief Resets the DAC2 peripheral.
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*
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* @api
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*/
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#define rccResetDAC2() rccResetAHB2(RCC_AHB2RSTR_DAC2RST)
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/**
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* @brief Enables the DAC3 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDAC3(lp) rccEnableAHB2(RCC_AHB2ENR_DAC3EN, lp)
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/**
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* @brief Disables the DAC3 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC3() rccDisableAHB2(RCC_AHB2ENR_DAC3EN)
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/**
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* @brief Resets the DAC3 peripheral.
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*
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* @api
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*/
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#define rccResetDAC3() rccResetAHB2(RCC_AHB2RSTR_DAC3RST)
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/**
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* @brief Enables the DAC4 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDAC4(lp) rccEnableAHB2(RCC_AHB2ENR_DAC4EN, lp)
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/**
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* @brief Disables the DAC4 peripheral clock.
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*
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* @api
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*/
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#define rccDisableDAC4() rccDisableAHB2(RCC_AHB2ENR_DAC4EN)
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/**
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* @brief Resets the DAC4 peripheral.
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*
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* @api
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*/
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#define rccResetDAC4() rccResetAHB2(RCC_AHB2RSTR_DAC4RST)
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/** @} */
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/**
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@ -416,34 +508,6 @@
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#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
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/** @} */
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/**
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* @name DMAMUX peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DMAMUX peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
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/**
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* @brief Disables the DMAMUX peripheral clock.
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*
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* @api
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*/
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#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
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/**
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* @brief Resets the DMAMUX peripheral.
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*
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* @api
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*/
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#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
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/** @} */
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/**
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* @name PWR interface specific RCC operations
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* @{
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@ -473,54 +537,31 @@
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/** @} */
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/**
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* @name CAN peripherals specific RCC operations
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* @name FDCAN peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the CAN1 peripheral clock.
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* @brief Enables the FDCAN1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_CAN1EN, lp)
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#define rccEnableFDCAN1(lp) rccEnableAPB1R1(RCC_APB1ENR1_FDCANEN, lp)
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/**
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* @brief Disables the CAN1 peripheral clock.
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* @brief Disables the FDCAN1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableCAN1() rccDisableAPB1R1(RCC_APB1ENR1_CAN1EN)
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#define rccDisableFDCAN1() rccDisableAPB1R1(RCC_APB1ENR1_FDCANEN)
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/**
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* @brief Resets the CAN1 peripheral.
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* @brief Resets the FDCAN1 peripheral.
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*
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* @api
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*/
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#define rccResetCAN1() rccResetAPB1R1(RCC_APB1RSTR1_CAN1RST)
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/**
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* @brief Enables the CAN2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableCAN2(lp) rccEnableAPB1R1(RCC_APB1ENR1_CAN2EN, lp)
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/**
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* @brief Disables the CAN2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableCAN2() rccDisableAPB1R1(RCC_APB1ENR1_CAN2EN)
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/**
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* @brief Resets the CAN2 peripheral.
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*
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* @api
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*/
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#define rccResetCAN2() rccResetAPB1R1(RCC_APB1RSTR1_CAN2RST)
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#define rccResetFDCAN1() rccResetAPB1R1(RCC_APB1RSTR1_FDCANRST)
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/** @} */
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/**
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@ -621,82 +662,31 @@
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/** @} */
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/**
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* @name OTG peripherals specific RCC operations
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* @name QUADSPI peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the OTG_FS peripheral clock.
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* @brief Enables the QUADSPI1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp)
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#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
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/**
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* @brief Disables the OTG_FS peripheral clock.
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* @brief Disables the QUADSPI1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableOTG_FS() rccDisableAHB2(RCC_AHB2ENR_OTGFSEN)
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#define rccDisableQUADSPI1() rccDisableAHB3(RCC_AHB3ENR_QSPIEN)
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/**
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* @brief Resets the OTG_FS peripheral.
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* @brief Resets the QUADSPI1 peripheral.
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*
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* @api
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*/
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#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
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/** @} */
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/**
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* @name OCTOSPI peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the OCTOSPI1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableOCTOSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_OSPI1EN, lp)
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/**
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* @brief Disables the OCTOSPI1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableOCTOSPI1() rccDisableAHB3(RCC_AHB3ENR_OSPI1EN)
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/**
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* @brief Resets the OCTOSPI1 peripheral.
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*
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* @api
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*/
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#define rccResetOCTOSPI1() rccResetAHB3(RCC_AHB3RSTR_OSPI1RST)
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/**
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* @brief Enables the OCTOSPI2 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableOCTOSPI2(lp) rccEnableAHB3(RCC_AHB3ENR_OSPI2EN, lp)
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/**
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* @brief Disables the OCTOSPI2 peripheral clock.
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*
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* @api
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*/
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#define rccDisableOCTOSPI2() rccDisableAHB3(RCC_AHB3ENR_OSPI2EN)
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/**
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* @brief Resets the OCTOSPI1 peripheral.
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*
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* @api
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*/
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#define rccResetOCTOSPI2() rccResetAHB3(RCC_AHB3RSTR_OSPI2RST)
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#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
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/** @} */
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/**
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@ -727,34 +717,6 @@
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#define rccResetRNG() rccResetAHB2(RCC_AHB2RSTR_RNGRST)
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/** @} */
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/**
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* @name SDMMC peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the SDMMC1 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp)
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/**
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* @brief Disables the SDMMC1 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSDMMC1() rccDisableAPB2(RCC_APB2ENR_SDMMC1EN)
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/**
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* @brief Resets the SDMMC1 peripheral.
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*
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* @api
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*/
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#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST)
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/** @} */
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/**
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* @name SPI peripherals specific RCC operations
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* @{
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@ -827,6 +789,29 @@
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* @api
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*/
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#define rccResetSPI3() rccResetAPB1R1(RCC_APB1RSTR1_SPI3RST)
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/**
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* @brief Enables the SPI4 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp)
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/**
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* @brief Disables the SPI4 peripheral clock.
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*
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* @api
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*/
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#define rccDisableSPI4() rccDisableAPB2(RCC_APB2ENR_SPI4EN)
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/**
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* @brief Resets the SPI4 peripheral.
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*
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* @api
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*/
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#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST)
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/** @} */
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/**
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@ -1085,6 +1070,29 @@
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* @api
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*/
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#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
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/**
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* @brief Enables the TIM20 peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableTIM20(lp) rccEnableAPB2(RCC_APB2ENR_TIM20EN, lp)
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/**
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* @brief Disables the TIM20 peripheral clock.
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*
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* @api
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*/
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#define rccDisableTIM20() rccDisableAPB2(RCC_APB2ENR_TIM20EN)
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/**
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* @brief Resets the TIM20 peripheral.
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*
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* @api
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*/
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#define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST)
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/** @} */
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/**
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@ -1241,21 +1249,21 @@
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*
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* @api
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*/
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#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBFSEN, lp)
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#define rccEnableUSB(lp) rccEnableAPB1R1(RCC_APB1ENR1_USBEN, lp)
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/**
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* @brief Disables the USB peripheral clock.
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*
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* @api
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*/
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#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBFSEN)
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#define rccDisableUSB() rccDisableAPB1R1(RCC_APB1ENR1_USBEN)
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/**
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* @brief Resets the USB peripheral.
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*
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* @api
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*/
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#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBFSRST)
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#define rccResetUSB() rccResetAPB1R1(RCC_APB1RSTR1_USBRST)
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/** @} */
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/**
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@ -1286,62 +1294,6 @@
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#define rccResetCRC() rccResetAHB1(RCC_AHB1RSTR_CRCRST)
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/** @} */
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/**
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* @name FSMC peripherals specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the FSMC peripheral clock.
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*
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* @param[in] lp low power enable flag
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*
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* @api
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*/
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#define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp)
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/**
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* @brief Disables the FSMC peripheral clock.
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*
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* @api
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*/
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#define rccDisableFSMC() rccDisableAHB3(RCC_AHB3ENR_FMCEN)
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/**
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* @brief Resets the FSMC peripheral.
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*
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* @api
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*/
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#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
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/** @} */
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/**
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* @name DCMI peripheral specific RCC operations
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* @{
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*/
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/**
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* @brief Enables the DCMI peripheral clock.
|
||||
*
|
||||
* @param[in] lp low power enable flag
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccEnableDCMI(lp) rccEnableAHB2(RCC_AHB2ENR_DCMIEN, lp)
|
||||
|
||||
/**
|
||||
* @brief Disables the DCMI peripheral clock.
|
||||
+ *
|
||||
+ * @api
|
||||
*/
|
||||
#define rccDisableDCMI() rccDisableAHB2(RCC_AHB2ENR_DCMIEN)
|
||||
|
||||
/**
|
||||
* @brief Resets the DCMI peripheral.
|
||||
*
|
||||
* @api
|
||||
*/
|
||||
#define rccResetDCMI() rccResetAHB2(RCC_AHB2RSTR_DCMIRST)
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue