diff --git a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c index 7878a1e09..228d5c56d 100644 --- a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c +++ b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.c @@ -48,56 +48,56 @@ * @details This table keeps the association between an unique channel * identifier and the involved physical registers. * @note Don't use this array directly, use the appropriate wrapper macros - * instead: @p STM32_DMA1_CHANNEL1, @p STM32_DMA1_CHANNEL2 etc. + * instead: @p STM32_GPDMA1_CHANNEL1, @p STM32_GPDMA1_CHANNEL2 etc. */ const stm32_gpdma_channel_t __stm32_gpdma_channels[STM32_GPDMA_CHANNELS] = { #if STM32_GPDMA1_NUM_CHANNELS > 0 - {GPDMA1_Channel0}, + {GPDMA1_Channel0, STM32_GPDMA1_CH0_NUMBER}, #endif #if STM32_GPDMA1_NUM_CHANNELS > 1 - {GPDMA1_Channel1}, + {GPDMA1_Channel1, STM32_GPDMA1_CH1_NUMBER}, #endif #if STM32_GPDMA1_NUM_CHANNELS > 2 - {GPDMA1_Channel2}, + {GPDMA1_Channel2, STM32_GPDMA1_CH2_NUMBER}, #endif #if STM32_GPDMA1_NUM_CHANNELS > 3 - {GPDMA1_Channel3}, + {GPDMA1_Channel3, STM32_GPDMA1_CH3_NUMBER}, #endif #if STM32_GPDMA1_NUM_CHANNELS > 4 - {GPDMA1_Channel4}, + {GPDMA1_Channel4, STM32_GPDMA1_CH4_NUMBER}, #endif #if STM32_GPDMA1_NUM_CHANNELS > 5 - {GPDMA1_Channel5}, + {GPDMA1_Channel5, STM32_GPDMA1_CH5_NUMBER}, #endif #if STM32_GPDMA1_NUM_CHANNELS > 6 - {GPDMA1_Channel6}, + {GPDMA1_Channel6, STM32_GPDMA1_CH6_NUMBER}, #endif #if STM32_GPDMA1_NUM_CHANNELS > 7 - {GPDMA1_Channel7}, + {GPDMA1_Channel7, STM32_GPDMA1_CH7_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 0 - {GPDMA2_Channel0}, + {GPDMA2_Channel0, STM32_GPDMA2_CH0_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 1 - {GPDMA2_Channel1}, + {GPDMA2_Channel1, STM32_GPDMA2_CH1_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 2 - {GPDMA2_Channel2}, + {GPDMA2_Channel2, STM32_GPDMA2_CH2_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 3 - {GPDMA2_Channel3}, + {GPDMA2_Channel3, STM32_GPDMA2_CH3_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 4 - {GPDMA2_Channel4}, + {GPDMA2_Channel4, STM32_GPDMA2_CH4_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 5 - {GPDMA2_Channel5}, + {GPDMA2_Channel5, STM32_GPDMA2_CH5_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 6 - {GPDMA2_Channel6}, + {GPDMA2_Channel6, STM32_GPDMA2_CH6_NUMBER}, #endif #if STM32_GPDMA2_NUM_CHANNELS > 7 - {GPDMA2_Channel7}, + {GPDMA2_Channel7, STM32_GPDMA2_CH7_NUMBER}, #endif }; @@ -173,10 +173,10 @@ void dmaInit(void) { * * @iclass */ -const stm32_gpdma_channel_t *dmaChannelAllocI(uint32_t cmask, - uint32_t irqprio, - stm32_gpdmaisr_t func, - void *param) { +const stm32_gpdma_channel_t *gpdmaChannelAllocI(uint32_t cmask, + uint32_t irqprio, + stm32_gpdmaisr_t func, + void *param) { unsigned i; uint32_t available; @@ -190,42 +190,33 @@ const stm32_gpdma_channel_t *dmaChannelAllocI(uint32_t cmask, uint32_t mask = (uint32_t)(1U << i); if ((available & mask) == 0U) { /* Channel found.*/ - const stm32_dma_channel_t *dmachp = STM32_DMA_CHANNEL(i); + const stm32_gpdma_channel_t *dmachp = STM32_GPDMA_CHANNEL(i); /* Installs the DMA handler.*/ - dma.channels[i].func = func; - dma.channels[i].param = param; - dma.allocated_mask |= mask; + gpdma.channels[i].func = func; + gpdma.channels[i].param = param; + gpdma.allocated_mask |= mask; /* Enabling DMA clocks required by the current channels set.*/ - if ((STM32_DMA1_CHANNELS_MASK & mask) != 0U) { + if ((STM32_GPDMA1_MASK_ANY & mask) != 0U) { rccEnableDMA1(true); } #if STM32_GPDMA2_NUM_CHANNELS > 0 - if ((STM32_DMA2_CHANNELS_MASK & mask) != 0U) { + if ((STM32_GPDMA2_MASK_ANY & mask) != 0U) { rccEnableDMA2(true); } #endif -#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(rccEnableDMAMUX) - /* Enabling DMAMUX if present.*/ - if (dma.allocated_mask != 0U) { - rccEnableDMAMUX(true); - } -#endif - /* Enables the associated IRQ vector if not already enabled and if a callback is defined.*/ if (func != NULL) { - if ((dma.isr_mask & dmachp->cmask) == 0U) { - nvicEnableVector(dmachp->vector, priority); - } - dma.isr_mask |= mask; + /* Could be already enabled but no problem.*/ + nvicEnableVector(dmachp->vector, irqprio); } /* Putting the channel in a known state.*/ - dmaStreamDisable(dmachp); - dmachp->channel->CCR = STM32_DMA_CCR_RESET_VALUE; + gpdmaStreamDisable(dmachp); + dmachp->channel->CCR = 0U; return dmachp; } @@ -250,14 +241,14 @@ const stm32_gpdma_channel_t *dmaChannelAllocI(uint32_t cmask, * * @api */ -const stm32_dma_channel_t *dmaStreamAlloc(uint32_t id, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { - const stm32_dma_channel_t *dmachp; +const stm32_gpdma_channel_t *gpdmaChannelAlloc(uint32_t cmask, + uint32_t irqprio, + stm32_gpdmaisr_t func, + void *param) { + const stm32_gpdma_channel_t *dmachp; osalSysLock(); - dmachp = dmaStreamAllocI(id, priority, func, param); + dmachp = gpdmaChannelAllocI(cmask, irqprio, func, param); osalSysUnlock(); return dmachp; @@ -273,44 +264,34 @@ const stm32_dma_channel_t *dmaStreamAlloc(uint32_t id, * * @iclass */ -void dmaStreamFreeI(const stm32_dma_channel_t *dmachp) { - uint32_t selfindex = (uint32_t)dmachp->selfindex; +void gpdmaChannelFreeI(const stm32_gpdma_channel_t *dmachp) { + uint32_t selfindex = (uint32_t)(dmachp - __stm32_gpdma_channels); osalDbgCheck(dmachp != NULL); /* Check if the channels is not taken.*/ - osalDbgAssert((dma.allocated_mask & (1 << selfindex)) != 0U, + osalDbgAssert((gpdma.allocated_mask & (1U << selfindex)) != 0U, "not allocated"); /* Marks the channel as not allocated.*/ - dma.allocated_mask &= ~(1U << selfindex); - dma.isr_mask &= ~(1U << selfindex); + gpdma.allocated_mask &= ~(1U << selfindex); /* Disables the associated IRQ vector if it is no more in use.*/ - if ((dma.isr_mask & dmachp->cmask) == 0U) { - nvicDisableVector(dmachp->vector); - } + nvicDisableVector(dmachp->vector); /* Removes the DMA handler.*/ - dma.channels[selfindex].func = NULL; - dma.channels[selfindex].param = NULL; + gpdma.channels[selfindex].func = NULL; + gpdma.channels[selfindex].param = NULL; /* Shutting down clocks that are no more required, if any.*/ - if ((dma.allocated_mask & STM32_DMA1_CHANNELS_MASK) == 0U) { + if ((gpdma.allocated_mask & STM32_GPDMA1_MASK_ANY) == 0U) { rccDisableDMA1(); } #if STM32_GPDMA2_NUM_CHANNELS > 0 - if ((dma.allocated_mask & STM32_DMA2_CHANNELS_MASK) == 0U) { + if ((gpdma.allocated_mask & STM32_GPDMA2_MASK_ANY) == 0U) { rccDisableDMA2(); } #endif - -#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && defined(rccDisableDMAMUX) - /* Shutting down DMAMUX if present.*/ - if (dma.allocated_mask == 0U) { - rccDisableDMAMUX(); - } -#endif } /** @@ -323,7 +304,7 @@ void dmaStreamFreeI(const stm32_dma_channel_t *dmachp) { * * @api */ -void dmaStreamFree(const stm32_dma_channel_t *dmachp) { +void gpdmaChannelFree(const stm32_gpdma_channel_t *dmachp) { osalSysLock(); dmaStreamFreeI(dmachp); @@ -341,7 +322,7 @@ void dmaServeInterrupt(const stm32_dma_channel_t *dmachp) { uint32_t flags; uint32_t selfindex = (uint32_t)dmachp->selfindex; - flags = (dmachp->dma->ISR >> dmachp->shift) & STM32_DMA_ISR_MASK; + flags = (dmachp->dma->ISR >> dmachp->shift) & STM32_GPDMA_ISR_MASK; if (flags & dmachp->channel->CCR) { dmachp->dma->IFCR = flags << dmachp->shift; if (dma.channels[selfindex].func) { diff --git a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h index 475a7dda5..d075007d3 100644 --- a/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h +++ b/os/hal/ports/STM32/LLD/GPDMAv1/stm32_gpdma.h @@ -34,7 +34,7 @@ /** * @brief Maximum number of transfers in a single operation. */ -#define STM32_DMA_MAX_TRANSFER 65535 +#define STM32_GPDMA_MAX_TRANSFER 65535 /** * @brief Checks if a GPDMA priority is within the valid range. @@ -44,7 +44,7 @@ * @retval false invalid GPDMA priority. * @retval true correct GPDMA priority. */ -#define STM32_DMA_IS_VALID_PRIORITY(prio) \ +#define STM32_GPDMA_IS_VALID_PRIORITY(prio) \ (((prio) >= 0U) && ((prio) <= 3U)) /** @@ -54,7 +54,7 @@ * @param[in] ch the channel number * @return An unique numeric channel identifier. */ -#define STM32_DMA_CHANNEL_ID(dma, ch) \ +#define STM32_GPDMA_CHANNEL_ID(dma, ch) \ ((((dma) - 1U) * STM32_GPDMA1_NUM_CHANNELS) + (ch)) /** @@ -65,8 +65,8 @@ * @param[in] ch the channel number * @return A channel mask. */ -#define STM32_DMA_CHANNEL_ID_MSK(dma, ch) \ - (1U << STM32_DMA_CHANNEL_ID(dma, ch)) +#define STM32_GPDMA_CHANNEL_ID_MSK(dma, ch) \ + (1U << STM32_GPDMA_CHANNEL_ID(dma, ch)) /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -175,6 +175,7 @@ typedef void (*stm32_gpdmaisr_t)(void *p, uint32_t csr); */ typedef struct { DMA_Channel_TypeDef *channel; /**< @brief Associated channel. */ + uint8_t vector; /**< @brief Associated IRQ vector. */ } stm32_gpdma_channel_t; /*===========================================================================*/ @@ -269,7 +270,7 @@ typedef struct { * @special */ #define dmaStreamEnable(dmastp) { \ - (dmastp)->channel->CCR |= STM32_DMA_CR_EN; \ + (dmastp)->channel->CCR |= STM32_GPDMA_CR_EN; \ } /** @@ -287,8 +288,8 @@ typedef struct { * @special */ #define dmaStreamDisable(dmastp) { \ - (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \ + (dmastp)->channel->CCR &= ~(STM32_GPDMA_CR_TCIE | STM32_GPDMA_CR_HTIE | \ + STM32_GPDMA_CR_TEIE | STM32_GPDMA_CR_EN); \ dmaStreamClearInterrupt(dmastp); \ } @@ -303,7 +304,7 @@ typedef struct { * @special */ #define dmaStreamClearInterrupt(dmastp) { \ - (dmastp)->dma->IFCR = STM32_DMA_ISR_MASK << (dmastp)->shift; \ + (dmastp)->dma->IFCR = STM32_GPDMA_ISR_MASK << (dmastp)->shift; \ } /** @@ -316,10 +317,10 @@ typedef struct { * @param[in] dmastp pointer to a stm32_gpdma_channel_t structure * @param[in] mode value to be written in the CCR register, this value * is implicitly ORed with: - * - @p STM32_DMA_CR_MINC - * - @p STM32_DMA_CR_PINC - * - @p STM32_DMA_CR_DIR_M2M - * - @p STM32_DMA_CR_EN + * - @p STM32_GPDMA_CR_MINC + * - @p STM32_GPDMA_CR_PINC + * - @p STM32_GPDMA_CR_DIR_M2M + * - @p STM32_GPDMA_CR_EN * . * @param[in] src source address * @param[in] dst destination address @@ -330,8 +331,8 @@ typedef struct { dmaStreamSetMemory0(dmastp, dst); \ dmaStreamSetTransactionSize(dmastp, n); \ dmaStreamSetMode(dmastp, (mode) | \ - STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ + STM32_GPDMA_CR_MINC | STM32_GPDMA_CR_PINC | \ + STM32_GPDMA_CR_DIR_M2M | STM32_GPDMA_CR_EN); \ } /** @@ -360,17 +361,17 @@ extern const stm32_gpdma_channel_t _stm32_gpdma_channels[STM32_GPDMA_CHANNELS]; extern "C" { #endif void dmaInit(void); - const stm32_gpdma_channel_t *dmaChannelAllocI(uint32_t cmask, - uint32_t irqprio, - stm32_gpdmaisr_t func, - void *param); - const stm32_gpdma_channel_t *dmaChannelAlloc(uint32_t cmask, - uint32_t irqprio, - stm32_gpdmaisr_t func, - void *param); - void dmaChannelFreeI(const stm32_gpdma_channel_t *dmachp); - void dmaChannelFree(const stm32_gpdma_channel_t *dmachp); - void dmaServeInterrupt(const stm32_gpdma_channel_t *dmachp); + const stm32_gpdma_channel_t *gpdmaChannelAllocI(uint32_t cmask, + uint32_t irqprio, + stm32_gpdmaisr_t func, + void *param); + const stm32_gpdma_channel_t *gpdmaChannelAlloc(uint32_t cmask, + uint32_t irqprio, + stm32_gpdmaisr_t func, + void *param); + void gpdmaChannelFreeI(const stm32_gpdma_channel_t *dmachp); + void gpdmaChannelFree(const stm32_gpdma_channel_t *dmachp); + void gpdmaServeInterrupt(const stm32_gpdma_channel_t *dmachp); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/STM32/STM32H5xx/stm32_isr.h b/os/hal/ports/STM32/STM32H5xx/stm32_isr.h index cdbcde0a6..cd69b7fbc 100644 --- a/os/hal/ports/STM32/STM32H5xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32H5xx/stm32_isr.h @@ -74,6 +74,43 @@ #define STM32_ADC1_NUMBER 37 +/* + * DMA unit. + */ +#define STM32_GPDMA1_CH0_HANDLER VectorAC +#define STM32_GPDMA1_CH1_HANDLER VectorB0 +#define STM32_GPDMA1_CH2_HANDLER VectorB4 +#define STM32_GPDMA1_CH3_HANDLER VectorB8 +#define STM32_GPDMA1_CH4_HANDLER VectorBC +#define STM32_GPDMA1_CH5_HANDLER VectorC0 +#define STM32_GPDMA1_CH6_HANDLER VectorC4 +#define STM32_GPDMA1_CH7_HANDLER VectorC8 +#define STM32_GPDMA2_CH0_HANDLER Vector190 +#define STM32_GPDMA2_CH1_HANDLER Vector194 +#define STM32_GPDMA2_CH2_HANDLER Vector198 +#define STM32_GPDMA2_CH3_HANDLER Vector19C +#define STM32_GPDMA2_CH4_HANDLER Vector1A0 +#define STM32_GPDMA2_CH5_HANDLER Vector1A4 +#define STM32_GPDMA2_CH6_HANDLER Vector1A8 +#define STM32_GPDMA2_CH7_HANDLER Vector1AC + +#define STM32_GPDMA1_CH0_NUMBER 27 +#define STM32_GPDMA1_CH1_NUMBER 28 +#define STM32_GPDMA1_CH2_NUMBER 29 +#define STM32_GPDMA1_CH3_NUMBER 30 +#define STM32_GPDMA1_CH4_NUMBER 31 +#define STM32_GPDMA1_CH5_NUMBER 32 +#define STM32_GPDMA1_CH6_NUMBER 33 +#define STM32_GPDMA1_CH7_NUMBER 34 +#define STM32_GPDMA2_CH0_NUMBER 90 +#define STM32_GPDMA2_CH1_NUMBER 91 +#define STM32_GPDMA2_CH2_NUMBER 92 +#define STM32_GPDMA2_CH3_NUMBER 93 +#define STM32_GPDMA2_CH4_NUMBER 94 +#define STM32_GPDMA2_CH5_NUMBER 95 +#define STM32_GPDMA2_CH6_NUMBER 96 +#define STM32_GPDMA2_CH7_NUMBER 97 + /* * EXTI unit. */