git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2169 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
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/**
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* @defgroup STM32 STM32 Drivers
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* @brief STM32 specific support.
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* @details The STM32 support includes:
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* - I/O ports driver.
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* - Buffered, interrupt driven, serial driver.
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* - Interrupt driver CAN driver.
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* - DMA capable, high performance, ADC driver.
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* - DMA capable, high performance, SPI driver.
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* - PWM driver.
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* - A demo supporting the kernel test suite.
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* - A demo that demonstrate the FatFs use with the MMC driver.
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* .
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*
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* @ingroup platforms
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*/
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/**
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* @defgroup STM32_HAL STM32 HAL Support
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* @brief HAL support.
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* @details The STM32 HAL support is responsible for system initialization.
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*
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* @section stm32_hal_1 Supported HW resources
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* - PLL1.
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* - PLL2.
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* - RCC.
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* - Flash.
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* .
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* @section stm32_hal_2 STM32 HAL driver implementation features
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* - PLLs startup and stabilization.
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* - Clock tree initialization.
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* - Clock source selection.
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* - Flash wait states initialization based on the selected clock options.
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* - SYSTICK initialization based on current clock and kernel required rate.
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* - DMA support initialization.
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* .
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* @ingroup STM32
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*/
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@ -55,17 +61,30 @@
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*/
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/**
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* @defgroup STM32_PAL STM32 I/O Ports Support
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* @brief I/O Ports peripherals support.
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* @details This module supports the STM3 GPIO controller. The controller
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* supports the following features (see @ref PAL):
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* @defgroup STM32_PAL STM32 GPIO Support
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* @brief GPIO peripherals support.
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*
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* @section stm32_pal_1 Supported HW resources
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* - AFIO.
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* - GPIOA.
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* - GPIOB.
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* - GPIOC.
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* - GPIOD.
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* - GPIOE.
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* - GPIOF.
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* - GPIOG.
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* .
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* @section stm32_pal_2 STM32 PAL driver implementation features
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* The PAL driver implementation fully supports the following hardware
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* capabilities:
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* - 16 bits wide ports.
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* - Atomic set/reset functions.
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* - Atomic set+reset function (atomic bus operations).
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* - Output latched regardless of the pad setting.
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* - Direct read of input pads regardless of the pad setting.
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* .
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* <h2>Supported Setup Modes</h2>
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* @section stm32_pal_3 Supported PAL setup modes
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* The STM32 PAL driver supports the following I/O modes:
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* - @p PAL_MODE_RESET.
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* - @p PAL_MODE_UNCONNECTED.
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* - @p PAL_MODE_INPUT.
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@ -74,11 +93,14 @@
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* - @p PAL_MODE_INPUT_ANALOG.
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* - @p PAL_MODE_OUTPUT_PUSHPULL.
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* - @p PAL_MODE_OUTPUT_OPENDRAIN.
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* - @p PAL_MODE_STM32_ALTERNATE_PUSHPULL (non standard).
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* - @p PAL_MODE_STM32_ALTERNATE_OPENDRAIN (non standard).
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* .
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* Any attempt to setup an invalid mode is ignored.
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*
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* <h2>Suboptimal Behavior</h2>
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* Some GPIO features are less than optimal:
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* @section stm32_pal_4 Suboptimal behavior
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* The GPIO is less than optimal in several areas, the limitations should
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* be taken in account while using the PAL driver:
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* - Pad/port toggling operations are not atomic.
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* - Pad/group mode setup is not atomic.
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* - Writing on pads/groups/ports programmed as input with pull-up/down
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@ -90,28 +112,63 @@
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/**
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* @defgroup STM32_SERIAL STM32 USART Support (buffered)
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* @brief USART peripherals support.
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* @details The serial driver supports the STM32 USARTs in asynchronous
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* mode.
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* @brief UART/USART peripherals support.
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*
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* @section stm32_serial_1 Supported HW resources
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* The serial driver can support any of the following hardware resources:
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* - USART1.
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* - USART2.
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* - USART3.
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* - UART4.
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* - UART5.
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* .
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* @section stm32_serial_2 STM32 Serial driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each UART/USART can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Fully interrupt driven.
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* - Programmable priority levels for each UART/USART.
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* .
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* @ingroup STM32
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*/
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/**
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* @defgroup STM32_UART STM32 USART Support (unbuffered)
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* @brief USART peripherals support.
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* @details The UART driver supports the STM32 USARTs using DMA channels for
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* improved performance.
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* @brief UART/USART peripherals support.
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*
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* @section stm32_uart_1 Supported HW resources
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* The UART driver can support any of the following hardware resources:
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* - USART1.
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* - USART2.
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* - USART3.
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* .
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* @section stm32_uart_2 STM32 UART driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each UART/USART can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable interrupt priority levels for each UART/USART.
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* - DMA is used for receiving and transmitting.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - Programmable DMA error hook for each DMA channel.
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* .
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* @ingroup STM32
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*/
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/**
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* @defgroup STM32_DMA STM32 DMA Support
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* @brief DMA support.
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* @details The DMA helper driver allows to stop the DMA clock when no other
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* driver requires its services.
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* @brief DMA helper driver.
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*
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* @section stm32_dma_1 Supported HW resources
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* The DMA driver can support any of the following hardware resources:
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* - DMA1.
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* - DMA2.
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* .
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* @section stm32_dma_2 STM32 DMA driver implementation features
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* - Automatic DMA clock stop when not in use by other drivers.
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* - Exports helper functions/macros to the other drivers that share the
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* DMA resource.
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* .
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* @ingroup STM32
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*/
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* @details The ADC driver supports the STM32 ADCs using DMA channels for
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* improved performance.
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*
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* @section stm32_adc_1 Supported HW resources
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* - ADC1.
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* .
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* @section stm32_adc_2 STM32 ADC driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Streaming conversion using DMA for maximum performance.
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* - Programmable ADC interrupt priority level.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - Programmable DMA error hook for each DMA channel.
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* .
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* @ingroup STM32
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*/
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/**
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* @defgroup STM32_CAN STM32 CAN Support
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* @brief CAN peripheral support.
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* @details The CAN driver supports the STM32 bxCAN unit.
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*
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* @section stm32_can_1 Supported HW resources
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* - bxCAN1.
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* .
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* @section stm32_can_2 STM32 CAN driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Support for bxCAN sleep mode.
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* - Programmable bxCAN interrupts priority level.
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* .
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* @ingroup STM32
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*/
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/**
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* @defgroup STM32_PWM STM32 PWM Support
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* @brief TIMx peripherals as PWM generators support.
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* @details The PWM driver supports the STM32 TIMx units as PWM generators.
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*
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* @section stm32_pwm_1 Supported HW resources
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* - TIM1.
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* - TIM2.
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* - TIM3.
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* - TIM4.
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* .
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* @section stm32_pwm_2 STM32 PWM driver implementation features
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* - Each timer can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Four independent PWM channels per timer.
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* - Programmable TIMx interrupts priority level.
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* .
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* @ingroup STM32
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*/
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* @details The SPI driver supports the STM32 SPIs using DMA channels for
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* improved performance.
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*
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* @section stm32_spi_1 Supported HW resources
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* - SPI1.
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* - SPI2.
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* - SPI3.
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* .
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* @section stm32_spi_2 STM32 SPI driver implementation features
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* - Clock stop for reduced power usage when the driver is in stop state.
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* - Each SPI can be independently enabled and programmed. Unused
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* peripherals are left in low power mode.
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* - Programmable interrupt priority levels for each SPI.
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* - DMA is used for receiving and transmitting.
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* - Programmable DMA bus priority for each DMA channel.
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* - Programmable DMA interrupt priority for each DMA channel.
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* - Programmable DMA error hook for each DMA channel.
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* .
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* @ingroup STM32
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*/
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