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I2C. Some fields from I2CSlaveConfig moved to driver. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3066 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
barthess 2011-06-21 18:30:50 +00:00
parent 30c130dc10
commit b54133ab1b
8 changed files with 92 additions and 85 deletions
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11
os/hal/include/i2c.h
View File

@ -143,8 +143,8 @@ struct I2CSlaveConfig{
*/
i2cerrorcallback_t id_err_callback;
size_t txbytes; /*!< Number of bytes to transmitted. */
size_t rxbytes; /*!< Number of bytes to received. */
// size_t txbytes; /*!< Number of bytes to transmitted. */
// size_t rxbytes; /*!< Number of bytes to received. */
i2cblock_t *rxbuf; /*!< Pointer to receive buffer. */
i2cblock_t *txbuf; /*!< Pointer to transmit buffer.*/
/**
@ -157,8 +157,7 @@ struct I2CSlaveConfig{
* Bits 10-14 unused.
*/
uint16_t slave_addr;
i2cflags_t errors; /*!< Error flags.*/
i2cflags_t flags; /*!< State flags.*/
/* Status Change @p EventSource.*/
EventSource sevent;
};
@ -241,8 +240,8 @@ extern "C" {
void i2cObjectInit(I2CDriver *i2cp);
void i2cStart(I2CDriver *i2cp, const I2CConfig *config);
void i2cStop(I2CDriver *i2cp);
void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg);
void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, size_t txbytes, size_t rxbytes);
void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, size_t rxbytes);
void i2cMasterStart(I2CDriver *i2cp);
void i2cMasterStop(I2CDriver *i2cp);
void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask);

66
os/hal/platforms/STM32/i2c_lld.c
View File

@ -48,13 +48,13 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
switch(i2c_get_event(i2cp)) {
case I2C_EV5_MASTER_MODE_SELECT:
i2cp->id_slave_config->flags &= ~I2C_FLG_HEADER_SENT;
i2cp->flags &= ~I2C_FLG_HEADER_SENT;
dp->DR = i2cp->slave_addr1;
break;
case I2C_EV9_MASTER_ADDR_10BIT:
if(i2cp->id_slave_config->flags & I2C_FLG_MASTER_RECEIVER) {
if(i2cp->flags & I2C_FLG_MASTER_RECEIVER) {
i2cp->slave_addr1 |= 0x01;
i2cp->id_slave_config->flags |= I2C_FLG_HEADER_SENT;
i2cp->flags |= I2C_FLG_HEADER_SENT;
// i2cp->id_i2c->CR1 = (i2cp->id_i2c->CR1 & (~I2C_CR1_ACK)) | I2C_CR1_STOP;
}
dp->DR = i2cp->slave_addr2;
@ -65,7 +65,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
// Master Transmitter ----------------------------------------------------
//------------------------------------------------------------------------
case I2C_EV6_MASTER_TRA_MODE_SELECTED:
if(i2cp->id_slave_config->flags & I2C_FLG_HEADER_SENT){
if(i2cp->flags & I2C_FLG_HEADER_SENT){
dp->CR1 |= I2C_CR1_START; // re-send the start in 10-Bit address mode
break;
}
@ -73,20 +73,20 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
txBuffp = (uint8_t*)i2cp->id_slave_config->txbuf;
datap = txBuffp;
txBuffp++;
i2cp->id_slave_config->txbytes--;
i2cp->txbytes--;
/* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */
if(i2cp->id_slave_config->txbytes == 0) {
if(i2cp->txbytes == 0) {
dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
}
//EV8_1 write the first data
dp->DR = *datap;
break;
case I2C_EV8_MASTER_BYTE_TRANSMITTING:
if(i2cp->id_slave_config->txbytes > 0) {
if(i2cp->txbytes > 0) {
datap = txBuffp;
txBuffp++;
i2cp->id_slave_config->txbytes--;
if(i2cp->id_slave_config->txbytes == 0) {
i2cp->txbytes--;
if(i2cp->txbytes == 0) {
/* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */
dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
}
@ -95,7 +95,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
break;
case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
/* if nothing to read then generate stop */
if (i2cp->id_slave_config->rxbytes == 0){
if (i2cp->rxbytes == 0){
dp->CR1 |= I2C_CR1_STOP; // stop generation
/* Disable ITEVT In order to not have again a BTF IT */
dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
@ -106,7 +106,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
/* Disable ITEVT In order to not have again a BTF IT */
dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
/* send restart and begin reading operations */
i2c_lld_master_receive(i2cp);
i2c_lld_master_receive(i2cp, i2cp->rxbytes);
}
break;
@ -116,7 +116,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
//------------------------------------------------------------------------
case I2C_EV6_MASTER_REC_MODE_SELECTED:
chSysLockFromIsr();
switch(i2cp->id_slave_config->flags & EV6_SUBEV_MASK) {
switch(i2cp->flags & EV6_SUBEV_MASK) {
case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: // only an single byte to receive
/* Clear ACK */
dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
@ -135,16 +135,16 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
rxBuffp = i2cp->id_slave_config->rxbuf;
break;
case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
if(i2cp->id_slave_config->rxbytes != 3) {
if(i2cp->rxbytes != 3) {
/* Read the data register */
*rxBuffp = dp->DR;
rxBuffp++;
i2cp->id_slave_config->rxbytes--;
switch(i2cp->id_slave_config->rxbytes){
i2cp->rxbytes--;
switch(i2cp->rxbytes){
case 3:
/* Disable the ITBUF in order to have only the BTF interrupt */
dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
i2cp->id_slave_config->flags |= I2C_FLG_3BTR;
i2cp->flags |= I2C_FLG_3BTR;
break;
case 0:
/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
@ -155,7 +155,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
// when remaining 3 bytes do nothing, wait until RXNE and BTF are set (until 2 bytes are received)
break;
case I2C_EV7_MASTER_REC_BYTE_QUEUED:
switch(i2cp->id_slave_config->flags & EV7_SUBEV_MASK) {
switch(i2cp->flags & EV7_SUBEV_MASK) {
case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS:
// DataN-2 and DataN-1 are received
chSysLockFromIsr();
@ -172,8 +172,8 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
chSysUnlockFromIsr();
rxBuffp++;
/* Decrement the number of readed bytes */
i2cp->id_slave_config->rxbytes -= 2;
i2cp->id_slave_config->flags = 0;
i2cp->rxbytes -= 2;
i2cp->flags = 0;
// ready for read DataN on the next EV7
break;
case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS: // only for case of two bytes to be received
@ -187,8 +187,8 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
rxBuffp++;
/* Read the DataN*/
*rxBuffp = dp->DR;
i2cp->id_slave_config->rxbytes = 0;
i2cp->id_slave_config->flags = 0;
i2cp->rxbytes = 0;
i2cp->flags = 0;
/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
_i2c_isr_code(i2cp, i2cp->id_slave_config);
break;
@ -516,7 +516,9 @@ void i2c_lld_stop(I2CDriver *i2cp) {
* @param[in] i2cp pointer to the @p I2CDriver object
*
*/
void i2c_lld_master_transmit(I2CDriver *i2cp) {
void i2c_lld_master_transmit(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) {
i2cp->txbytes = txbytes;
i2cp->rxbytes = rxbytes;
// enable ERR, EVT & BUF ITs
i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
@ -535,8 +537,8 @@ void i2c_lld_master_transmit(I2CDriver *i2cp) {
i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr <<1) & 0x00FE);
}
i2cp->id_slave_config->flags = 0;
i2cp->id_slave_config->errors = 0;
i2cp->flags = 0;
i2cp->errors = 0;
i2cp->id_i2c->CR1 |= I2C_CR1_START; // send start bit
@ -556,7 +558,9 @@ void i2c_lld_master_transmit(I2CDriver *i2cp) {
* @param[in] i2cp pointer to the @p I2CDriver object
*
*/
void i2c_lld_master_receive(I2CDriver *i2cp){
void i2c_lld_master_receive(I2CDriver *i2cp, size_t rxbytes){
i2cp->rxbytes = rxbytes;
// enable ERR, EVT & BUF ITs
i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
i2cp->id_i2c->CR1 |= I2C_CR1_ACK; // acknowledge returned
@ -575,16 +579,16 @@ void i2c_lld_master_receive(I2CDriver *i2cp){
i2cp->slave_addr1 = ((i2cp->id_slave_config->slave_addr <<1) | 0x01);
}
i2cp->id_slave_config->flags = I2C_FLG_MASTER_RECEIVER;
i2cp->id_slave_config->errors = 0;
i2cp->flags = I2C_FLG_MASTER_RECEIVER;
i2cp->errors = 0;
// Only one byte to be received
if(i2cp->id_slave_config->rxbytes == 1) {
i2cp->id_slave_config->flags |= I2C_FLG_1BTR;
if(i2cp->rxbytes == 1) {
i2cp->flags |= I2C_FLG_1BTR;
}
// Only two bytes to be received
else if(i2cp->id_slave_config->rxbytes == 2) {
i2cp->id_slave_config->flags |= I2C_FLG_2BTR;
else if(i2cp->rxbytes == 2) {
i2cp->flags |= I2C_FLG_2BTR;
i2cp->id_i2c->CR1 |= I2C_CR1_POS; // Acknowledge Position
}

10
os/hal/platforms/STM32/i2c_lld.h
View File

@ -166,6 +166,11 @@ struct I2CDriver{
uint8_t slave_addr1; /*!< 7-bit address of the slave with r\w bit.*/
uint8_t slave_addr2; /*!< used in 10-bit address mode. */
size_t rxbytes;
size_t txbytes;
i2cflags_t errors; /*!< Error flags.*/
i2cflags_t flags; /*!< State flags.*/
/*********** End of the mandatory fields. **********************************/
@ -217,9 +222,8 @@ void i2c_lld_set_opmode(I2CDriver *i2cp);
void i2c_lld_set_own_address(I2CDriver *i2cp);
void i2c_lld_start(I2CDriver *i2cp);
void i2c_lld_stop(I2CDriver *i2cp);
void i2c_lld_master_transmit(I2CDriver *i2cp);
void i2c_lld_master_receive(I2CDriver *i2cp);
void i2c_lld_master_transceive(I2CDriver *i2cp);
void i2c_lld_master_transmit(I2CDriver *i2cp, size_t txbytes, size_t rxbytes);
void i2c_lld_master_receive(I2CDriver *i2cp, size_t rxbytes);
#ifdef __cplusplus
}

30
os/hal/src/i2c.c
View File

@ -137,10 +137,10 @@ void i2cStop(I2CDriver *i2cp) {
* @param[in] i2cscfg pointer to the @p I2C slave config
*
*/
void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, size_t txbytes, size_t rxbytes) {
chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) &&\
(i2cscfg->txbytes > 0) &&\
(txbytes > 0) &&\
(i2cscfg->txbuf != NULL),
"i2cMasterTransmit");
@ -162,7 +162,7 @@ void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
"i2cMasterTransmit(), #1", "not ready");
i2cp->id_state = I2C_ACTIVE;
i2c_lld_master_transmit(i2cp);
i2c_lld_master_transmit(i2cp, txbytes, rxbytes);
_i2c_wait_s(i2cp);
#if !I2C_USE_WAIT
i2c_lld_wait_bus_free(i2cp);
@ -179,10 +179,10 @@ void i2cMasterTransmit(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
* @param[in] i2cscfg pointer to the @p I2C slave config
*
*/
void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg, size_t rxbytes){
chDbgCheck((i2cp != NULL) && (i2cscfg != NULL) &&\
(i2cscfg->rxbytes > 0) && \
(rxbytes > 0) && \
(i2cscfg->rxbuf != NULL),
"i2cMasterReceive");
@ -204,7 +204,7 @@ void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
"i2cMasterReceive(), #1", "not ready");
i2cp->id_state = I2C_ACTIVE;
i2c_lld_master_receive(i2cp);
i2c_lld_master_receive(i2cp, rxbytes);
_i2c_wait_s(i2cp);
#if !I2C_USE_WAIT
i2c_lld_wait_bus_free(i2cp);
@ -215,11 +215,11 @@ void i2cMasterReceive(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
}
uint16_t i2cSMBusAlertResponse(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
i2cMasterReceive(i2cp, i2cscfg);
return i2cp->id_slave_config->slave_addr;
}
//uint16_t i2cSMBusAlertResponse(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg) {
//
// i2cMasterReceive(i2cp, i2cscfg);
// return i2cp->id_slave_config->slave_addr;
//}
/**
@ -236,7 +236,7 @@ void i2cAddFlagsI(I2CDriver *i2cp, i2cflags_t mask) {
chDbgCheck(i2cp != NULL, "i2cAddFlagsI");
i2cp->id_slave_config->errors |= mask;
i2cp->errors |= mask;
chEvtBroadcastI(&i2cp->id_slave_config->sevent);
}
@ -255,8 +255,8 @@ i2cflags_t i2cGetAndClearFlags(I2CDriver *i2cp) {
chDbgCheck(i2cp != NULL, "i2cGetAndClearFlags");
chSysLock();
mask = i2cp->id_slave_config->errors;
i2cp->id_slave_config->errors = I2CD_NO_ERROR;
mask = i2cp->errors;
i2cp->errors = I2CD_NO_ERROR;
chSysUnlock();
return mask;
}
@ -279,7 +279,7 @@ void i2cAcquireBus(I2CDriver *i2cp) {
chDbgCheck(i2cp != NULL, "i2cAcquireBus");
#if CH_USE_MUTEXES
chMtxLock(&i2cp->mutex);
chMtxLock(&i2cp->id_mutex);
#elif CH_USE_SEMAPHORES
chSemWait(&i2cp->id_semaphore);
#endif

8
testhal/STM32/I2C/Makefile
View File

@ -77,9 +77,11 @@ CSRC = $(PORTSRC) \
$(CHIBIOS)/os/various/syscalls.c \
main.c \
i2c_pns.c \
lis3.c\
max1236.c\
tmp75.c\
tmp75.c\
max1236.c\
lis3.c\
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.

21
testhal/STM32/I2C/lis3.c
View File

@ -30,13 +30,9 @@ static void i2c_lis3_error_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
static I2CSlaveConfig lis3 = {
NULL,
i2c_lis3_error_cb,
0,
0,
accel_rx_data,
accel_tx_data,
0b0011101,
0,
0,
{NULL},
};
@ -109,20 +105,23 @@ int init_lis3(void){
while (i2c_accel_tp == NULL)
chThdSleepMilliseconds(1);
lis3.rxbytes = 0; //set to 0 because we need only transmit
#define RXBYTES 0 //set to 0 because we need only transmit
#define TXBYTES 4
/* configure accelerometer */
lis3.txbytes = 4;
lis3.txbuf[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT; // register address
lis3.txbuf[1] = 0b11100111;
lis3.txbuf[2] = 0b01000001;
lis3.txbuf[3] = 0b00000000;
/* sending */
i2cMasterTransmit(&I2CD1, &lis3);
i2cMasterTransmit(&I2CD1, &lis3, TXBYTES, RXBYTES);
chThdSleepMilliseconds(1);
lis3.id_callback = i2c_lis3_cb;
#undef RXBYTES
#undef TXBYTES
return 0;
}
@ -130,11 +129,13 @@ int init_lis3(void){
*
*/
void request_acceleration_data(void){
#define RXBYTES 6
#define TXBYTES 1
lis3.txbuf[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT; // register address
lis3.txbytes = 1;
lis3.rxbytes = 6;
i2cAcquireBus(&I2CD1);
i2cMasterTransmit(&I2CD1, &lis3);
i2cMasterTransmit(&I2CD1, &lis3, TXBYTES, RXBYTES);
i2cReleaseBus(&I2CD1);
#undef RXBYTES
#undef TXBYTES
}

21
testhal/STM32/I2C/max1236.c
View File

@ -42,13 +42,9 @@ static void i2c_max1236_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
static I2CSlaveConfig max1236 = {
NULL,
i2c_max1236_error_cb,
0,
0,
max1236_rx_data,
max1236_tx_data,
0b0110100,
0,
0,
{NULL},
};
@ -59,29 +55,34 @@ static I2CSlaveConfig max1236 = {
*/
void init_max1236(void){
/* this data we must send via IC to setup ADC */
max1236.rxbytes = 0;
max1236.txbytes = 2; // total 2 bytes to be sent
#define RXBYTES 0
#define TXBYTES 2
max1236.txbuf[0] = 0b10000011; // config register content. Consult datasheet
max1236.txbuf[1] = 0b00000111; // config register content. Consult datasheet
// transmit out 2 bytes
i2cAcquireBus(&I2CD2);
i2cMasterTransmit(&I2CD2, &max1236);
i2cMasterTransmit(&I2CD2, &max1236, TXBYTES, RXBYTES);
while(I2CD2.id_state != I2C_READY){
chThdSleepMilliseconds(1);
}
/* now add pointer to callback function */
max1236.id_callback = i2c_max1236_cb;
i2cReleaseBus(&I2CD2);
#undef RXBYTES
#undef TXBYTES
}
/* Now simply read 8 bytes to get all 4 ADC channels */
void read_max1236(void){
max1236.txbytes = 0;
max1236.rxbytes = 8;
#define TXBYTES 0
#define RXBYTES 8
i2cAcquireBus(&I2CD2);
i2cMasterReceive(&I2CD2, &max1236);
i2cMasterReceive(&I2CD2, &max1236, RXBYTES);
i2cReleaseBus(&I2CD2);
#undef RXBYTES
#undef TXBYTES
}

10
testhal/STM32/I2C/tmp75.c
View File

@ -37,23 +37,19 @@ static void i2c_tmp75_cb(I2CDriver *i2cp, I2CSlaveConfig *i2cscfg){
static I2CSlaveConfig tmp75 = {
i2c_tmp75_cb,
i2c_tmp75_error_cb,
0,
0,
tmp75_rx_data,
tmp75_tx_data,
0b1001000,
0,
0,
{NULL},
};
/* This is main function. */
void request_temperature(void){
tmp75.txbytes = 0; // set to zero because we need only reading
tmp75.rxbytes = 2; // we need to read 2 bytes
#define TXBYTES 0 // set to zero because we need only reading
#define RXBYTES 2 // we need to read 2 bytes
i2cAcquireBus(&I2CD2);
i2cMasterReceive(&I2CD2, &tmp75);
i2cMasterReceive(&I2CD2, &tmp75, RXBYTES);
i2cReleaseBus(&I2CD2);
}