git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6749 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2014-03-03 14:57:32 +00:00
parent 8c4653a413
commit b5650c0457
4 changed files with 51 additions and 8 deletions

View File

@ -163,7 +163,7 @@ extern "C" {
void i2sStart(I2SDriver *i2sp, const I2SConfig *config);
void i2sStop(I2SDriver *i2sp);
void i2sStartExchange(I2SDriver *i2sp);
void i2sStopTransfer(I2SDriver *i2sp);
void i2sStopExchange(I2SDriver *i2sp);
#ifdef __cplusplus
}
#endif

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@ -419,14 +419,22 @@ void i2s_lld_start_exchange(I2SDriver *i2sp) {
*/
void i2s_lld_stop_exchange(I2SDriver *i2sp) {
/* Stop DMAs.*/
if (NULL != i2sp->dmatx)
/* Stop TX DMA, if enabled.*/
if (NULL != i2sp->dmatx) {
dmaStreamDisable(i2sp->dmatx);
/* From the RM: To switch off the I2S, by clearing I2SE, it is mandatory
to wait for TXE = 1 and BSY = 0.*/
while ((i2sp->spi->SR & (SPI_SR_TXE | SPI_SR_BSY)) != SPI_SR_TXE)
;
}
/* Stop SPI/I2S peripheral.*/
i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
/* Stop RX DMA, if enabled.*/
if (NULL != i2sp->dmarx)
dmaStreamDisable(i2sp->dmarx);
/* Stop transfer.*/
i2sp->spi->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
}
#endif /* HAL_USE_I2S */

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@ -17,6 +17,28 @@
#include "ch.h"
#include "hal.h"
#define I2S_BUF_SIZE 256
static uint16_t i2s_rx_buf[I2S_BUF_SIZE];
static void i2scallback(I2SDriver *i2sp, size_t offset, size_t n);
static const I2SConfig i2scfg = {
NULL,
i2s_rx_buf,
I2S_BUF_SIZE,
i2scallback,
0,
16
};
static void i2scallback(I2SDriver *i2sp, size_t offset, size_t n) {
(void)i2sp;
(void)offset;
(void)n;
}
/*
* Application entry point.
*/
@ -33,9 +55,22 @@ int main(void) {
chSysInit();
/*
* Normal main() thread activity, in this demo it does nothing.
* Starting and configuring the I2S driver 2.
*/
i2sStart(&I2SD2, &i2scfg);
/*
* Starting continuous I2S transfer.
*/
i2sStartExchange(&I2SD2);
/*
* Normal main() thread activity, if the button is pressed then the I2s
* transfer is stopped.
*/
while (TRUE) {
if (palReadPad(GPIOA, GPIOA_BUTTON))
i2sStopExchange(&I2SD2);
chThdSleepMilliseconds(500);
}
return 0;

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@ -54,7 +54,7 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
#define STM32_I2SSRC STM32_I2SSRC_CKIN
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SR_VALUE 5
#define STM32_PVD_ENABLE FALSE