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Reworked DAC driver, missing DMAMUX RCC macros for G4. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13092 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-10-07 07:45:49 +00:00
parent 12297967f2
commit b6ad15437b
5 changed files with 62 additions and 21 deletions
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41
os/hal/ports/STM32/LLD/DACv1/hal_dac_lld.c
View File

@ -283,6 +283,7 @@ static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
/* DMA errors handling.*/
dac_lld_stop_conversion(dacp);
_dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
}
else {
@ -431,9 +432,15 @@ void dac_lld_start(DACDriver *dacp) {
/* Enabling DAC in SW triggering mode initially, initializing data to
zero.*/
#if STM32_DAC_DUAL_MODE == FALSE
{
uint32_t cr = dacp->params->dac->CR;
dacp->params->dac->CR = cr;
cr &= dacp->params->regmask;
cr |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
dacp->params->dac->CR &= dacp->params->regmask;
dacp->params->dac->CR |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
dac_lld_put_channel(dacp, channel, dacp->config->init);
}
#else
if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
(dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
@ -645,7 +652,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12R1 +
dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_12BIT_LEFT:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
@ -653,7 +660,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR12L1 +
dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_HWORD;
break;
case DAC_DHRM_8BIT_RIGHT:
osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
@ -661,7 +668,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8R1 +
dacp->params->dataoffset);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_BYTE;
/* In this mode the size of the buffer is halved because two samples
packed in a single dacsample_t element.*/
@ -689,7 +696,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->DHR8RD);
dmamode = dacp->params->dmamode |
STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_HWORD;
n /= 2;
break;
#endif
@ -706,16 +713,17 @@ void dac_lld_start_conversion(DACDriver *dacp) {
dmaStreamEnable(dacp->dma);
/* DAC configuration.*/
cr = dacp->params->dac->CR;
#if STM32_DAC_DUAL_MODE == FALSE
cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr;
dacp->params->dac->CR &= dacp->params->regmask;
dacp->params->dac->CR |= cr << dacp->params->regshift;
cr &= dacp->params->regmask;
cr |= (DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
#else
dacp->params->dac->CR = 0;
cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << DAC_CR_TSEL1_Pos) | DAC_CR_TEN1 | DAC_CR_EN1 | dacp->config->cr
| (dacp->grpp->trigger << DAC_CR_TSEL2_Pos) | DAC_CR_TEN2 | DAC_CR_EN2 | (dacp->config->cr << 16);
dacp->params->dac->CR = cr;
#endif
dacp->params->dac->CR = cr;
}
/**
@ -729,26 +737,31 @@ void dac_lld_start_conversion(DACDriver *dacp) {
* @iclass
*/
void dac_lld_stop_conversion(DACDriver *dacp) {
uint32_t cr;
/* DMA channel disabled and released.*/
dmaStreamDisable(dacp->dma);
dmaStreamFreeI(dacp->dma);
dacp->dma = NULL;
cr = dacp->params->dac->CR;
#if STM32_DAC_DUAL_MODE == FALSE
dacp->params->dac->CR &= dacp->params->regmask;
dacp->params->dac->CR |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
cr &= dacp->params->regmask;
cr |= (DAC_CR_EN1 | dacp->config->cr) << dacp->params->regshift;
#else
if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
(dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
(dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
dacp->params->dac->CR = DAC_CR_EN2 | (dacp->config->cr << 16) |
cr = DAC_CR_EN2 | (dacp->config->cr << 16) |
DAC_CR_EN1 | dacp->config->cr;
}
else {
dacp->params->dac->CR = DAC_CR_EN1 | dacp->config->cr;
cr = DAC_CR_EN1 | dacp->config->cr;
}
#endif
dacp->params->dac->CR = cr;
}
#endif /* HAL_USE_DAC */

28
os/hal/ports/STM32/STM32G4xx/stm32_rcc.h
View File

@ -508,6 +508,34 @@
#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST)
/** @} */
/**
* @name DMAMUX peripheral specific RCC operations
* @{
*/
/**
* @brief Enables the DMAMUX peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMAMUX(lp) rccEnableAHB1(RCC_AHB1ENR_DMAMUX1EN, lp)
/**
* @brief Disables the DMAMUX peripheral clock.
*
* @api
*/
#define rccDisableDMAMUX() rccDisableAHB1(RCC_AHB1ENR_DMAMUX1EN)
/**
* @brief Resets the DMAMUX peripheral.
*
* @api
*/
#define rccResetDMAMUX() rccResetAHB1(RCC_AHB1RSTR_DMAMUX1RST)
/** @} */
/**
* @name PWR interface specific RCC operations
* @{

4
testhal/STM32/multi/DAC/debug/STM32-DAC (Select ELF file)(OpenOCD, Flash and Run).launch
View File

@ -33,9 +33,9 @@
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2
testhal/STM32/multi/DAC/make/stm32g474re_nucleo64.make
View File

@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).

2
testhal/STM32/multi/DAC/make/stm32h743_nucleo144.make
View File

@ -5,7 +5,7 @@
# Compiler options here.
ifeq ($(USE_OPT),)
USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).