RAM vectors support.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15045 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -111,6 +111,14 @@
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#define CRT0_INIT_STACKS TRUE
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#define CRT0_INIT_STACKS TRUE
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#endif
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#endif
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/**
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* @brief Vectors table initialization.
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* @details Vectors are copied in RAM on startup.
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*/
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#if !defined(CRT0_INIT_VECTORS) || defined(__DOXYGEN__)
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#define CRT0_INIT_VECTORS FALSE
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#endif
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/**
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/**
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* @brief DATA segment initialization switch.
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* @brief DATA segment initialization switch.
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*/
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*/
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@ -200,9 +208,9 @@ _crt0_entry:
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msr PSP, r0
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msr PSP, r0
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#if CRT0_VTOR_INIT == TRUE
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#if CRT0_VTOR_INIT == TRUE
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/* Initial VTOR position enforced.*/
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ldr r0, =_vectors
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ldr r0, =_vectors
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movw r1, #SCB_VTOR & 0xFFFF
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ldr r1, =SCB_VTOR
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movt r1, #SCB_VTOR >> 16
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str r0, [r1]
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str r0, [r1]
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#endif
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#endif
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@ -278,9 +286,30 @@ psloop:
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blo psloop
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blo psloop
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#endif
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#endif
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#if CRT0_INIT_VECTORS == TRUE
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/* Vectors initialization. Note, it assumes that the vectors
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size is a multiple of 4 so the linker file must ensure
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this.*/
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ldr r1, =__textvectors_base__
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ldr r2, =__vectors_base__
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ldr r3, =__vectors_end__
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mov r4, r2
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vloop:
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cmp r2, r3
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ittt lo
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ldrlo r0, [r1], #4
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strlo r0, [r2], #4
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blo vloop
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/* VTOR now pointing to the RAM table.*/
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ldr r1, =SCB_VTOR
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str r4, [r1]
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#endif
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#if CRT0_INIT_DATA == TRUE
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#if CRT0_INIT_DATA == TRUE
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/* Data initialization. Note, it assumes that the DATA size
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/* Data initialization. Note, it assumes that the DATA
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is a multiple of 4 so the linker file must ensure this.*/
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size is a multiple of 4 so the linker file must ensure
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this.*/
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ldr r1, =__textdata_base__
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ldr r1, =__textdata_base__
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ldr r2, =__data_base__
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ldr r2, =__data_base__
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ldr r3, =__data_end__
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ldr r3, =__data_end__
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@ -293,8 +322,9 @@ dloop:
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#endif
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#endif
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#if CRT0_INIT_BSS == TRUE
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#if CRT0_INIT_BSS == TRUE
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/* BSS initialization. Note, it assumes that the DATA size
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/* BSS initialization. Note, it assumes that the BSS
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is a multiple of 4 so the linker file must ensure this.*/
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size is a multiple of 4 so the linker file must ensure
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this.*/
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movs r0, #0
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movs r0, #0
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ldr r1, =__bss_base__
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ldr r1, =__bss_base__
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ldr r2, =__bss_end__
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ldr r2, =__bss_end__
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@ -20,7 +20,10 @@ SECTIONS
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{
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{
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.vectors : ALIGN(1024)
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.vectors : ALIGN(1024)
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{
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{
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__textvectors_base__ = LOADADDR(.vectors);
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__vectors_base__ = .;
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KEEP(*(.vectors))
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KEEP(*(.vectors))
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__vectors_end__ = .;
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} > VECTORS_FLASH AT > VECTORS_FLASH_LMA
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} > VECTORS_FLASH AT > VECTORS_FLASH_LMA
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.xtors : ALIGN(4)
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.xtors : ALIGN(4)
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@ -20,8 +20,8 @@ SECTIONS
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{
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{
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PROVIDE(_textdata = LOADADDR(.data));
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PROVIDE(_textdata = LOADADDR(.data));
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PROVIDE(_data = .);
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PROVIDE(_data = .);
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__textdata_base__ = LOADADDR(.data);
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__textdata_base__ = LOADADDR(.data);
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__data_base__ = .;
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__data_base__ = .;
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*(.data)
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*(.data)
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*(.data.*)
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*(.data.*)
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*(.ramtext)
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*(.ramtext)
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91
readme.txt
91
readme.txt
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@ -74,93 +74,4 @@
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*****************************************************************************
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*****************************************************************************
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*** Next ***
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*** Next ***
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- NEW: STM32 ADCv2 now supports return code on start function.
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- NEW: Added option to copy vectors in RAM on startup for GCC ARMv7-M.
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- NEW: Integrated FatFS with lwIP HTTPD, now it is possible to serve files
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using HTTP from a storage device.
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- NEW: Updated FatFS to version 0.14b.
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- NEW: SPIv2 driver has been implemented on: STM32F0, STM32F1, STM32F3,
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STM32F4, STM32F7, STM32G0, STM32G4, STM32L0, STM32L1, STM32L4,
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STM32L4+, STM32H7.
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- NEW: New SPIv2 driver model, it is compatible with the previous SPI driver
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and introduces: better runtime errors handling, slave mode,
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data synchronization function, various other improvements.
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- NEW: Added an alternate port for ARMv7-M, it uses less RAM and it is
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faster at interrupt processing, it is slightly slower at
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thread-to-thread context switch so it is not a full replacement.
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- NEW: Now all xxxStart() functions in HAL are able to report a driver
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activation error.
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- NEW: Support for STM32G031, STM32G041, STM32G0B1, STM32G0C1.
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- NEW: Made STM32H7 non-cacheable memory option also shareable.
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- NEW: EFL driver and demo for STM32F3xx.
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- NEW: New unit test subsystem under /os/test. Now it is officially
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ChibiOS/TEST.
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- FIX: Fixed function nvicSetSystemHandlerPriority() failing with CM0+ cores
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(bug #1199)(backported to 20.3.4)(TBP to 21.6.1).
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- FIX: Fixed several problems in STM32L4xx PLL and GPIO settings (bug #1198)
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(backported to 20.3.4)(TBP to 21.6.1).
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- FIX: Fixed PLLSA1x input frequency calculated incorrectly (bug #1197)
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(TBP to 21.6.1).
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- FIX: Fixed ARMCMx port, MPU not enabled when PORT_ENABLE_GUARD_PAGES is set
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(bug #1195)(backported to 20.3.4)(TBP to 21.6.1).
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- FIX: Fixed removed incorrect ADCv4 checks for MONEN (bug #1194)
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- FIX: Fixed hang in spi_lld_ignore() in SPIv3 on H7 (bug #1193)
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- FIX: Fixed invalid references in e200 port (bug #1192)
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(TBP to 21.6.1)
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- FIX: Fixed NIL invalid references when debug options are enabled (bug #1191)
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(TBP to 21.6.1)
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- FIX: Fixed problem in stm32_pll.inc and stm32_pllv2.inc (bug #1190)
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(TBP to 21.6.1)
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- FIX: Fixed invalid RCC LPUART1 clock enable on STM32G0xx (bug #1189)
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(TBP to 21.6.1)(backported to 20.3.4).
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- FIX: Support for STM32G491 (bug #1187)(TBP to 21.6.1).
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- FIX: Fixes for uart clock rounding, missing DMA streams and timers
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(bug #1186)(TBP).
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- FIX: Fixed invalid check in chVTResetTimeStamp() function (bug #1185)
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(TBP).
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- FIX: Fixed wrong configuration in testex LSM6DSL demos (bug #1184).
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed CH_CFG_NO_IDLE_THREAD option causes compiler errors (bug #1183)
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(backported to 21.6.1).
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- FIX: Fixed STM32 ADCv3 differences in headers (bug #1182)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed DMAv1 compile fail on STM32L011 (bug #1181)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed error in STM32_ADCCLK_MIN for STM32F37x/hal_lld.h (bug #1180)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed direct calls to RT in STM32 RTCv2 and RTCv3 (bug #1179)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed STM32G071 mcuconf.h template not showing TIM14/15/16/17
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(bug #1178)(backported to 21.6.1).
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- FIX: Fixed path ambiguity between STM32 USARTv2 and USARTv3 drivers
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(bug #1177)(backported to 21.6.1).
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- FIX: Fixed invalid DMAMUX settings in DMAv1 for some devices (bug #1176)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed wrong macro in the demo STM32F7xx-SPI-ADXL355 (bug #1175)
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(backported to 21.6.1(backported to 21.6.1).
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- FIX: Fixed problem with RC initialization mask of the GPIO for the
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STM32L4x3 (bug #1174)(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed problem with N25Q driver (bug #1173)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed semaphores broken when CH_CFG_USE_SEMAPHORES_PRIORITY is enabled
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(bug #1172)(backported to 21.6.1).
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- FIX: Fixed idle thread stack area not cleared when CH_DBG_FILL_THREADS
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is enabled (bug #1171)(backported to 21.6.1).
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- FIX: Fixed function chRegNextThread() broken when CH_CFG_USE_DYNAMIC
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is disabled (bug #1170)(backported to 21.6.1).
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- FIX: Fixed insufficient information in RT registry (bug #1169)
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(backported to 21.6.1).
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- FIX: Fixed code base not compatible with -Wcast-align=strict (bug #1168)
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(backported to 21.6.1).
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- FIX: Fixed wrong chconf.h for ADuCM36x demos (bug #1167)
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(backported to 21.6.1).
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- FIX: Fixed missing constant in ADuCM36x hal_lld.c (bug #1166)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed missing chrfcu.c file in rt.mk (bug #1165)
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(backported to 21.6.1).
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- FIX: Fixed invalid STM32 TIM21/TIM22 debug freeze setting (bug #1164)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed missing RTC APB enable on STM32G0xx (bug #1163)
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(backported to 21.6.1)
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- FIX: Fixed I2S-related definitions missing in STM32F3xx registry (bug #1162)
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(backported to 21.6.1)(backported to 20.3.4).
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- FIX: Fixed AVR port broken (bug #1161)(backported to 21.6.1).
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