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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6186 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-08-20 10:18:03 +00:00
parent 2bbf9f1ea0
commit b7f30ecadd
16 changed files with 7042 additions and 6 deletions
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7
demos/ARMCM0-STM32F051-DISCOVERY/Makefile
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@ -59,12 +59,13 @@ PROJECT = ch
# Imported source files and paths
CHIBIOS = ../..
#include $(CHIBIOS)/boards/ST_STM32F0_DISCOVERY/board.mk
#include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/osal/chibios/osal.mk
include $(CHIBIOS)/os/hal/boards/ST_STM32F0_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F0xx/platform.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/rt/ports/ARMCMx/devices/STM32F0xx/port.mk
#include $(CHIBIOS)/test/test.mk
include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F051x8.ld

298
os/hal/platforms/STM32F0xx/adc_lld.c Normal file
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@ -0,0 +1,298 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/adc_lld.c
* @brief STM32F0xx ADC subsystem low level driver source.
*
* @addtogroup ADC
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_ADC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/** @brief ADC1 driver identifier.*/
#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
ADCDriver ADCD1;
#endif
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Stops an ongoing conversion, if any.
*
* @param[in] adc pointer to the ADC registers block
*/
static void adc_lld_stop_adc(ADC_TypeDef *adc) {
if (adc->CR & ADC_CR_ADSTART) {
adc->CR |= ADC_CR_ADSTP;
while (adc->CR & ADC_CR_ADSTP)
;
}
}
/**
* @brief ADC DMA ISR service routine.
*
* @param[in] adcp pointer to the @p ADCDriver object
* @param[in] flags pre-shifted content of the ISR register
*/
static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
/* DMA errors handling.*/
if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
/* DMA, this could help only if the DMA tries to access an unmapped
address space or violates alignment rules.*/
_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
}
else {
/* It is possible that the conversion group has already be reset by the
ADC error handler, in this case this interrupt is spurious.*/
if (adcp->grpp != NULL) {
if ((flags & STM32_DMA_ISR_HTIF) != 0) {
/* Half transfer processing.*/
_adc_isr_half_code(adcp);
}
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
/* Transfer complete processing.*/
_adc_isr_full_code(adcp);
}
}
}
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
/**
* @brief ADC interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector70) {
uint32_t isr;
CH_IRQ_PROLOGUE();
isr = ADC1->ISR;
ADC1->ISR = isr;
/* It could be a spurious interrupt caused by overflows after DMA disabling,
just ignore it in this case.*/
if (ADCD1.grpp != NULL) {
/* Note, an overflow may occur after the conversion ended before the driver
is able to stop the ADC, this is why the DMA channel is checked too.*/
if ((isr & ADC_ISR_OVR) &&
(dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
/* ADC overflow condition, this could happen only if the DMA is unable
to read data fast enough.*/
_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
}
if (isr & ADC_ISR_AWD) {
/* Analog watchdog error.*/
_adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
}
}
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level ADC driver initialization.
*
* @notapi
*/
void adc_lld_init(void) {
#if STM32_ADC_USE_ADC1
/* Driver initialization.*/
adcObjectInit(&ADCD1);
ADCD1.adc = ADC1;
ADCD1.dmastp = STM32_DMA1_STREAM1;
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif
/* The shared vector is initialized on driver initialization and never
disabled.*/
nvicEnableVector(ADC1_COMP_IRQn,
CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
/* Calibration procedure.*/
rccEnableADC1(FALSE);
chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
ADC1->CR |= ADC_CR_ADCAL;
while (ADC1->CR & ADC_CR_ADCAL)
;
rccDisableADC1(FALSE);
}
/**
* @brief Configures and activates the ADC peripheral.
*
* @param[in] adcp pointer to the @p ADCDriver object
*
* @notapi
*/
void adc_lld_start(ADCDriver *adcp) {
/* If in stopped state then enables the ADC and DMA clocks.*/
if (adcp->state == ADC_STOP) {
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp) {
bool_t b;
b = dmaStreamAllocate(adcp->dmastp,
STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
(void *)adcp);
chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccEnableADC1(FALSE);
#if STM32_ADCSW == STM32_ADCSW_HSI14
/* Clock from HSI14, no need for jitter removal.*/
ADC1->CFGR2 = 0x00001000;
#else
#if STM32_ADCPRE == STM32_ADCPRE_DIV2
ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
#else
ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
#endif
#endif
}
#endif /* STM32_ADC_USE_ADC1 */
/* ADC initial setup, starting the analog part here in order to reduce
the latency when starting a conversion.*/
adcp->adc->CR = ADC_CR_ADEN;
while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
;
}
}
/**
* @brief Deactivates the ADC peripheral.
*
* @param[in] adcp pointer to the @p ADCDriver object
*
* @notapi
*/
void adc_lld_stop(ADCDriver *adcp) {
/* If in ready state then disables the ADC clock and analog part.*/
if (adcp->state == ADC_READY) {
dmaStreamRelease(adcp->dmastp);
/* Disabling ADC.*/
if (adcp->adc->CR & ADC_CR_ADEN) {
adc_lld_stop_adc(adcp->adc);
adcp->adc->CR |= ADC_CR_ADDIS;
while (adcp->adc->CR & ADC_CR_ADDIS)
;
}
#if STM32_ADC_USE_ADC1
if (&ADCD1 == adcp)
rccDisableADC1(FALSE);
#endif
}
}
/**
* @brief Starts an ADC conversion.
*
* @param[in] adcp pointer to the @p ADCDriver object
*
* @notapi
*/
void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode;
const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
mode = adcp->dmamode;
if (grpp->circular) {
mode |= STM32_DMA_CR_CIRC;
}
if (adcp->depth > 1) {
/* If the buffer depth is greater than one then the half transfer interrupt
interrupt is enabled in order to allows streaming processing.*/
mode |= STM32_DMA_CR_HTIE;
}
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
(uint32_t)adcp->depth);
dmaStreamSetMode(adcp->dmastp, mode);
dmaStreamEnable(adcp->dmastp);
/* ADC setup, if it is defined a callback for the analog watch dog then it
is enabled.*/
adcp->adc->ISR = adcp->adc->ISR;
adcp->adc->IER = ADC_IER_OVRIE | ADC_IER_AWDIE;
adcp->adc->TR = grpp->tr;
adcp->adc->SMPR = grpp->smpr;
adcp->adc->CHSELR = grpp->chselr;
/* ADC configuration and start.*/
adcp->adc->CFGR1 = grpp->cfgr1 | ADC_CFGR1_CONT | ADC_CFGR1_DMACFG |
ADC_CFGR1_DMAEN;
adcp->adc->CR |= ADC_CR_ADSTART;
}
/**
* @brief Stops an ongoing conversion.
*
* @param[in] adcp pointer to the @p ADCDriver object
*
* @notapi
*/
void adc_lld_stop_conversion(ADCDriver *adcp) {
dmaStreamDisable(adcp->dmastp);
adc_lld_stop_adc(adcp->adc);
}
#endif /* HAL_USE_ADC */
/** @} */

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os/hal/platforms/STM32F0xx/adc_lld.h Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/adc_lld.h
* @brief STM32F0xx ADC subsystem low level driver header.
*
* @addtogroup ADC
* @{
*/
#ifndef _ADC_LLD_H_
#define _ADC_LLD_H_
#if HAL_USE_ADC || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name Sampling rates
* @{
*/
#define ADC_SMPR_SMP_1P5 0 /**< @brief 14 cycles conversion time */
#define ADC_SMPR_SMP_7P5 1 /**< @brief 21 cycles conversion time. */
#define ADC_SMPR_SMP_13P5 2 /**< @brief 28 cycles conversion time. */
#define ADC_SMPR_SMP_28P5 3 /**< @brief 41 cycles conversion time. */
#define ADC_SMPR_SMP_41P5 4 /**< @brief 54 cycles conversion time. */
#define ADC_SMPR_SMP_55P5 5 /**< @brief 68 cycles conversion time. */
#define ADC_SMPR_SMP_71P5 6 /**< @brief 84 cycles conversion time. */
#define ADC_SMPR_SMP_239P5 7 /**< @brief 252 cycles conversion time. */
/** @} */
/**
* @name Resolution
* @{
*/
#define ADC_CFGR1_RES_12BIT (0 << 3)
#define ADC_CFGR1_RES_10BIT (1 << 3)
#define ADC_CFGR1_RES_8BIT (2 << 3)
#define ADC_CFGR1_RES_6BIT (3 << 3)
/** @} */
/**
* @name Threashold register initializer
* @{
*/
#define ADC_TR(low, high) (((uint32_t)(high) << 16) | (uint32_t)(low))
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief ADC1 driver enable switch.
* @details If set to @p TRUE the support for ADC1 is included.
* @note The default is @p FALSE.
*/
#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
#define STM32_ADC_USE_ADC1 FALSE
#endif
/**
* @brief ADC1 DMA priority (0..3|lowest..highest).
*/
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#endif
/**
* @brief ADC interrupt priority level setting.
*/
#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_IRQ_PRIORITY 2
#endif
/**
* @brief ADC1 DMA interrupt priority level setting.
*/
#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
#error "ADC1 not present in the selected device"
#endif
#if !STM32_ADC_USE_ADC1
#error "ADC driver activated but no ADC peripheral assigned"
#endif
#if STM32_ADC_USE_ADC1 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1"
#endif
#if STM32_ADC_USE_ADC1 && \
!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
#error "Invalid IRQ priority assigned to ADC1 DMA"
#endif
#if STM32_ADC_USE_ADC1 && \
!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
#error "Invalid DMA priority assigned to ADC1"
#endif
#if !defined(STM32_DMA_REQUIRED)
#define STM32_DMA_REQUIRED
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief ADC sample data type.
*/
typedef uint16_t adcsample_t;
/**
* @brief Channels number in a conversion group.
*/
typedef uint16_t adc_channels_num_t;
/**
* @brief Possible ADC failure causes.
* @note Error codes are architecture dependent and should not relied
* upon.
*/
typedef enum {
ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
} adcerror_t;
/**
* @brief Type of a structure representing an ADC driver.
*/
typedef struct ADCDriver ADCDriver;
/**
* @brief ADC notification callback type.
*
* @param[in] adcp pointer to the @p ADCDriver object triggering the
* callback
* @param[in] buffer pointer to the most recent samples data
* @param[in] n number of buffer rows available starting from @p buffer
*/
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
/**
* @brief ADC error callback type.
*
* @param[in] adcp pointer to the @p ADCDriver object triggering the
* callback
* @param[in] err ADC error code
*/
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
/**
* @brief Conversion group configuration structure.
* @details This implementation-dependent structure describes a conversion
* operation.
* @note The use of this configuration structure requires knowledge of
* STM32 ADC cell registers interface, please refer to the STM32
* reference manual for details.
*/
typedef struct {
/**
* @brief Enables the circular buffer mode for the group.
*/
bool_t circular;
/**
* @brief Number of the analog channels belonging to the conversion group.
*/
adc_channels_num_t num_channels;
/**
* @brief Callback function associated to the group or @p NULL.
*/
adccallback_t end_cb;
/**
* @brief Error callback or @p NULL.
*/
adcerrorcallback_t error_cb;
/* End of the mandatory fields.*/
/**
* @brief ADC CFGR1 register initialization data.
*/
uint32_t cfgr1;
/**
* @brief ADC TR register initialization data.
*/
uint32_t tr;
/**
* @brief ADC SMPR register initialization data.
*/
uint32_t smpr;
/**
* @brief ADC CHSELR register initialization data.
* @details The number of bits at logic level one in this register must
* be equal to the number in the @p num_channels field.
*/
uint32_t chselr;
} ADCConversionGroup;
/**
* @brief Driver configuration structure.
* @note It could be empty on some architectures.
*/
typedef struct {
uint32_t dummy;
} ADCConfig;
/**
* @brief Structure representing an ADC driver.
*/
struct ADCDriver {
/**
* @brief Driver state.
*/
adcstate_t state;
/**
* @brief Current configuration data.
*/
const ADCConfig *config;
/**
* @brief Current samples buffer pointer or @p NULL.
*/
adcsample_t *samples;
/**
* @brief Current samples buffer depth or @p 0.
*/
size_t depth;
/**
* @brief Current conversion group pointer or @p NULL.
*/
const ADCConversionGroup *grpp;
#if ADC_USE_WAIT || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
Thread *thread;
#endif
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
/**
* @brief Mutex protecting the peripheral.
*/
Mutex mutex;
#elif CH_USE_SEMAPHORES
Semaphore semaphore;
#endif
#endif /* ADC_USE_MUTUAL_EXCLUSION */
#if defined(ADC_DRIVER_EXT_FIELDS)
ADC_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief Pointer to the ADCx registers block.
*/
ADC_TypeDef *adc;
/**
* @brief Pointer to associated DMA channel.
*/
const stm32_dma_stream_t *dmastp;
/**
* @brief DMA mode bit mask.
*/
uint32_t dmamode;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Changes the value of the ADC CCR register.
* @details Use this function in order to enable or disable the internal
* analog sources. See the documentation in the STM32F0xx Reference
* Manual.
*/
#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
extern ADCDriver ADCD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void adc_lld_init(void);
void adc_lld_start(ADCDriver *adcp);
void adc_lld_stop(ADCDriver *adcp);
void adc_lld_start_conversion(ADCDriver *adcp);
void adc_lld_stop_conversion(ADCDriver *adcp);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_ADC */
#endif /* _ADC_LLD_H_ */
/** @} */

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os/hal/platforms/STM32F0xx/ext_lld_isr.c Normal file
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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/ext_lld_isr.c
* @brief STM32F0xx EXT subsystem low level driver ISR code.
*
* @addtogroup EXT
* @{
*/
#include "ch.h"
#include "hal.h"
#if HAL_USE_EXT || defined(__DOXYGEN__)
#include "ext_lld_isr.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief EXTI[0]...EXTI[1] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector54) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 0) | (1 << 1));
EXTI->PR = pr;
if (pr & (1 << 0))
EXTD1.config->channels[0].cb(&EXTD1, 0);
if (pr & (1 << 1))
EXTD1.config->channels[1].cb(&EXTD1, 1);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[2]...EXTI[3] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector58) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 2) | (1 << 3));
EXTI->PR = pr;
if (pr & (1 << 2))
EXTD1.config->channels[2].cb(&EXTD1, 2);
if (pr & (1 << 3))
EXTD1.config->channels[3].cb(&EXTD1, 3);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[4]...EXTI[15] interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector5C) {
uint32_t pr;
CH_IRQ_PROLOGUE();
pr = EXTI->PR & ((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) |
(1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
(1 << 14) | (1 << 15));
EXTI->PR = pr;
if (pr & (1 << 4))
EXTD1.config->channels[4].cb(&EXTD1, 4);
if (pr & (1 << 5))
EXTD1.config->channels[5].cb(&EXTD1, 5);
if (pr & (1 << 6))
EXTD1.config->channels[6].cb(&EXTD1, 6);
if (pr & (1 << 7))
EXTD1.config->channels[7].cb(&EXTD1, 7);
if (pr & (1 << 8))
EXTD1.config->channels[8].cb(&EXTD1, 8);
if (pr & (1 << 9))
EXTD1.config->channels[9].cb(&EXTD1, 9);
if (pr & (1 << 10))
EXTD1.config->channels[10].cb(&EXTD1, 10);
if (pr & (1 << 11))
EXTD1.config->channels[11].cb(&EXTD1, 11);
if (pr & (1 << 12))
EXTD1.config->channels[12].cb(&EXTD1, 12);
if (pr & (1 << 13))
EXTD1.config->channels[13].cb(&EXTD1, 13);
if (pr & (1 << 14))
EXTD1.config->channels[14].cb(&EXTD1, 14);
if (pr & (1 << 15))
EXTD1.config->channels[15].cb(&EXTD1, 15);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[16] interrupt handler (PVD).
*
* @isr
*/
CH_IRQ_HANDLER(Vector44) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 16);
EXTD1.config->channels[16].cb(&EXTD1, 16);
CH_IRQ_EPILOGUE();
}
/**
* @brief EXTI[17] interrupt handler (RTC).
*
* @isr
*/
CH_IRQ_HANDLER(Vector48) {
CH_IRQ_PROLOGUE();
EXTI->PR = (1 << 17);
EXTD1.config->channels[17].cb(&EXTD1, 17);
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Enables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_enable(void) {
nvicEnableVector(EXTI0_1_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY));
nvicEnableVector(EXTI2_3_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY));
nvicEnableVector(EXTI4_15_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY));
nvicEnableVector(PVD_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
nvicEnableVector(RTC_IRQn,
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
}
/**
* @brief Disables EXTI IRQ sources.
*
* @notapi
*/
void ext_lld_exti_irq_disable(void) {
nvicDisableVector(EXTI0_1_IRQn);
nvicDisableVector(EXTI2_3_IRQn);
nvicDisableVector(EXTI4_15_IRQn);
nvicDisableVector(PVD_IRQn);
nvicDisableVector(RTC_IRQn);
}
#endif /* HAL_USE_EXT */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/ext_lld_isr.h
* @brief STM32F0xx EXT subsystem low level driver ISR header.
*
* @addtogroup EXT
* @{
*/
#ifndef _EXT_LLD_ISR_H_
#define _EXT_LLD_ISR_H_
#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief EXTI0..1 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI0_1_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI2..3 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI2_3_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI4..15 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI4_15_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI16 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI16_IRQ_PRIORITY 3
#endif
/**
* @brief EXTI17 interrupt priority level setting.
*/
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void ext_lld_exti_irq_enable(void);
void ext_lld_exti_irq_disable(void);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EXT */
#endif /* _EXT_LLD_ISR_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/hal_lld.c
* @brief STM32F0xx HAL subsystem low level driver source.
*
* @addtogroup HAL
* @{
*/
#include "ch.h"
#include "hal.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing clock source impossible without resetting
* of the whole BKP domain.
*/
static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/
PWR->CR |= PWR_CR_DBP;
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
}
/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
#if defined(STM32_LSE_BYPASS)
/* LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
#else
/* No LSE Bypass.*/
RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON;
#endif
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
RCC->BDCR |= STM32_RTCSEL;
/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level HAL driver initialization.
*
* @notapi
*/
void hal_lld_init(void) {
/* Reset of all peripherals.*/
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
/* SysTick initialization using the system clock.*/
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
/* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
#if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
/* Programmable voltage detector enable.*/
#if STM32_PVD_ENABLE
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
#endif /* STM32_PVD_ENABLE */
}
/**
* @brief STM32 clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
* @special
*/
void stm32_clock_init(void) {
#if !STM32_NO_INIT
/* HSI setup, it enforces the reset situation in order to handle possible
problems with JTAG probes and re-initializations.*/
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
while (!(RCC->CR & RCC_CR_HSIRDY))
; /* Wait until HSI is stable. */
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
RCC->CFGR = 0; /* CFGR reset value. */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
; /* Waits until HSI is selected. */
#if STM32_HSE_ENABLED
/* HSE activation.*/
#if defined(STM32_HSE_BYPASS)
/* HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#else
/* No HSE Bypass.*/
RCC->CR |= RCC_CR_HSEON;
#endif
while (!(RCC->CR & RCC_CR_HSERDY))
; /* Waits until HSE is stable. */
#endif
#if STM32_HSE14_ENABLED
/* HSI14 activation.*/
RCC->CR2 |= RCC_CR2_HSI14ON;
while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
; /* Waits until HSI14 is stable. */
#endif
#if STM32_LSI_ENABLED
/* LSI activation.*/
RCC->CSR |= RCC_CSR_LSION;
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
; /* Waits until LSI is stable. */
#endif
/* Clock settings.*/
RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE | STM32_HPRE;
RCC->CFGR2 = STM32_PREDIV;
RCC->CFGR3 = STM32_ADCSW | STM32_CECSW | STM32_I2C1SW |
STM32_USART1SW;
#if STM32_ACTIVATE_PLL
/* PLL activation.*/
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL is stable. */
#endif
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS;
/* Switching to the configured clock source if it is different from HSI.*/
#if (STM32_SW != STM32_SW_HSI)
/* Switches clock source.*/
RCC->CFGR |= STM32_SW;
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
; /* Waits selection complete. */
#endif
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
#endif /* !STM32_NO_INIT */
}
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/hal_lld.h
* @brief STM32F0xx HAL subsystem low level driver header.
* @pre This module requires the following macros to be defined in the
* @p board.h file:
* - STM32_LSECLK.
* - STM32_LSEDRV.
* - STM32_LSE_BYPASS (optionally).
* - STM32_HSECLK.
* - STM32_HSE_BYPASS (optionally).
* .
* One of the following macros must also be defined:
* - STM32F0XX for Entry Level devices.
* .
*
* @addtogroup HAL
* @{
*/
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
#include "stm32.h"
#include "stm32_registry.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Defines the support for realtime counters in the HAL.
*/
#define HAL_IMPLEMENTS_COUNTERS FALSE
/**
* @name Platform identification
* @{
*/
#define PLATFORM_NAME "STM32F05x Entry Level"
/** @} */
/**
* @name Absolute Maximum Ratings
* @{
*/
/**
* @brief Maximum system clock frequency.
*/
#define STM32_SYSCLK_MAX 48000000
/**
* @brief Maximum HSE clock frequency.
*/
#define STM32_HSECLK_MAX 32000000
/**
* @brief Minimum HSE clock frequency.
*/
#define STM32_HSECLK_MIN 1000000
/**
* @brief Maximum LSE clock frequency.
*/
#define STM32_LSECLK_MAX 1000000
/**
* @brief Minimum LSE clock frequency.
*/
#define STM32_LSECLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
*/
#define STM32_PLLIN_MAX 25000000
/**
* @brief Minimum PLLs input clock frequency.
*/
#define STM32_PLLIN_MIN 1000000
/**
* @brief Maximum PLL output clock frequency.
*/
#define STM32_PLLOUT_MAX 48000000
/**
* @brief Minimum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 16000000
/**
* @brief Maximum APB clock frequency.
*/
#define STM32_PCLK_MAX 48000000
/**
* @brief Maximum ADC clock frequency.
*/
#define STM32_ADCCLK_MAX 14000000
/** @} */
/**
* @name Internal clock sources
* @{
*/
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
#define STM32_HSI14CLK 14000000 /**< 14MHz speed internal clock.*/
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
/** @} */
/**
* @name PWR_CR register bits definitions
* @{
*/
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
/** @} */
/**
* @name RCC_CFGR register bits definitions
* @{
*/
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define STM32_PPRE_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define STM32_PPRE_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define STM32_PPRE_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define STM32_PPRE_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define STM32_PPRE_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define STM32_ADCPRE_DIV2 (0 << 14) /**< PCLK divided by 2. */
#define STM32_ADCPRE_DIV4 (1 << 14) /**< PCLK divided by 4. */
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCOSEL_HSI14 (3 << 24) /**< HSI14 clock on MCO pin. */
#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
/** @} */
/**
* @name RCC_BDCR register bits definitions
* @{
*/
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 32 used as
RTC clock. */
/** @} */
/**
* @name RCC_CFGR3 register bits definitions
* @{
*/
#define STM32_USART1SW_MASK (3 << 0) /**< USART1 clock source mask. */
#define STM32_USART1SW_PCLK (0 << 0) /**< USART1 clock is PCLK. */
#define STM32_USART1SW_SYSCLK (1 << 0) /**< USART1 clock is SYSCLK. */
#define STM32_USART1SW_LSE (2 << 0) /**< USART1 clock is LSE. */
#define STM32_USART1SW_HSI (3 << 0) /**< USART1 clock is HSI. */
#define STM32_I2C1SW_MASK (1 << 4) /**< I2C clock source mask. */
#define STM32_I2C1SW_HSI (0 << 4) /**< I2C clock is HSI. */
#define STM32_I2C1SW_SYSCLK (1 << 4) /**< I2C clock is SYSCLK. */
#define STM32_CECSW_MASK (1 << 6) /**< CEC clock source mask. */
#define STM32_CECSW_HSI (0 << 6) /**< CEC clock is HSI/244. */
#define STM32_CECSW_LSE (1 << 6) /**< CEC clock is LSE. */
#define STM32_ADCSW_MASK (1 << 8) /**< ADC clock source mask. */
#define STM32_ADCSW_HSI14 (0 << 8) /**< ADC clock is HSI14. */
#define STM32_ADCSW_PCLK (1 << 8) /**< ADC clock is PCLK/2|4. */
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name Configuration options
* @{
*/
/**
* @brief Disables the PWR/RCC initialization in the HAL.
*/
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
#define STM32_NO_INIT FALSE
#endif
/**
* @brief Enables or disables the programmable voltage detector.
*/
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
#define STM32_PVD_ENABLE FALSE
#endif
/**
* @brief Sets voltage level for programmable voltage detector.
*/
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
#define STM32_PLS STM32_PLS_LEV0
#endif
/**
* @brief Enables or disables the HSI clock source.
*/
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSI_ENABLED TRUE
#endif
/**
* @brief Enables or disables the HSI14 clock source.
*/
#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSI14_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSI clock source.
*/
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
#define STM32_LSI_ENABLED FALSE
#endif
/**
* @brief Enables or disables the HSE clock source.
*/
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
#define STM32_HSE_ENABLED TRUE
#endif
/**
* @brief Enables or disables the LSE clock source.
*/
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
#define STM32_LSE_ENABLED FALSE
#endif
/**
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not
* initialized and started.
* @note The default value is calculated for a 48MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_SW) || defined(__DOXYGEN__)
#define STM32_SW STM32_SW_PLL
#endif
/**
* @brief Clock source for the PLL.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
* @note The default value is calculated for a 48MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLSRC STM32_PLLSRC_HSE
#endif
/**
* @brief Crystal PLL pre-divider.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
* @note The default value is calculated for a 72MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
#define STM32_PREDIV_VALUE 1
#endif
/**
* @brief PLL multiplier value.
* @note The allowed range is 2...16.
* @note The default value is calculated for a 48MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLMUL_VALUE 6
#endif
/**
* @brief AHB prescaler value.
* @note The default value is calculated for a 48MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
#define STM32_HPRE STM32_HPRE_DIV1
#endif
/**
* @brief APB1 prescaler value.
*/
#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
#define STM32_PPRE STM32_PPRE_DIV1
#endif
/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#endif
/**
* @brief ADC prescaler value.
*/
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#endif
/**
* @brief ADC clock source.
*/
#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
#define STM32_ADCSW STM32_ADCSW_HSI14
#endif
/**
* @brief CEC clock source.
*/
#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
#define STM32_CECSW STM32_CECSW_HSI
#endif
/**
* @brief I2C1 clock source.
*/
#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
#define STM32_I2C1SW STM32_I2C1SW_HSI
#endif
/**
* @brief USART1 clock source.
*/
#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
#define STM32_USART1SW STM32_USART1SW_PCLK
#endif
/**
* @brief RTC clock source.
*/
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSI
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*
* Configuration-related checks.
*/
#if !defined(STM32F0xx_MCUCONF)
#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
#endif
/*
* HSI related checks.
*/
#if STM32_HSI_ENABLED
#else /* !STM32_HSI_ENABLED */
#if STM32_SW == STM32_SW_HSI
#error "HSI not enabled, required by STM32_SW"
#endif
#if STM32_CECSW == STM32_CECSW_HSI
#error "HSI not enabled, required by STM32_CECSW"
#endif
#if STM32_I2C1SW == STM32_I2C1SW_HSI
#error "HSI not enabled, required by STM32_I2C1SW"
#endif
#if STM32_USART1SW == STM32_USART1SW_HSI
#error "HSI not enabled, required by STM32_USART1SW"
#endif
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
(STM32_PLLSRC == STM32_PLLSRC_HSI))
#error "HSI not enabled, required by STM32_MCOSEL"
#endif
#endif /* !STM32_HSI_ENABLED */
/*
* HSI14 related checks.
*/
#if STM32_HSI14_ENABLED
#else /* !STM32_HSI14_ENABLED */
#if STM32_MCOSEL == STM32_MCOSEL_HSI14
#error "HSI14 not enabled, required by STM32_MCOSEL"
#endif
#if STM32_ADCSW == STM32_ADCSW_HSI14
#error "HSI14 not enabled, required by STM32_ADCSW"
#endif
#endif /* !STM32_HSI14_ENABLED */
/*
* HSE related checks.
*/
#if STM32_HSE_ENABLED
#if STM32_HSECLK == 0
#error "HSE frequency not defined"
#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
#endif
#else /* !STM32_HSE_ENABLED */
#if STM32_SW == STM32_SW_HSE
#error "HSE not enabled, required by STM32_SW"
#endif
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
#endif
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#error "HSE not enabled, required by STM32_RTCSEL"
#endif
#endif /* !STM32_HSE_ENABLED */
/*
* LSI related checks.
*/
#if STM32_LSI_ENABLED
#else /* !STM32_LSI_ENABLED */
#if STM32_RTCSEL == STM32_RTCSEL_LSI
#error "LSI not enabled, required by STM32_RTCSEL"
#endif
#endif /* !STM32_LSI_ENABLED */
/*
* LSE related checks.
*/
#if STM32_LSE_ENABLED
#if (STM32_LSECLK == 0)
#error "LSE frequency not defined"
#endif
#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
#endif
#if !defined(STM32_LSEDRV)
#error "STM32_LSEDRV not defined"
#endif
#if (STM32_LSEDRV >> 3) > 3
#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
#endif
#if STM32_CECSW == STM32_CECSW_LSE
#error "LSE not enabled, required by STM32_CECSW"
#endif
#if STM32_USART1SW == STM32_USART1SW_LSE
#error "LSE not enabled, required by STM32_USART1SW"
#endif
#else /* !STM32_LSE_ENABLED */
#if STM32_RTCSEL == STM32_RTCSEL_LSE
#error "LSE not enabled, required by STM32_RTCSEL"
#endif
#endif /* !STM32_LSE_ENABLED */
/* PLL activation conditions.*/
#if (STM32_SW == STM32_SW_PLL) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
*/
#define STM32_ACTIVATE_PLL TRUE
#else
#define STM32_ACTIVATE_PLL FALSE
#endif
/* HSE prescaler setting check.*/
#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
#define STM32_PREDIV ((STM32_PREDIV_VALUE - 1) << 0)
#else
#error "invalid STM32_PREDIV value specified"
#endif
/**
* @brief PLLMUL field.
*/
#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
defined(__DOXYGEN__)
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
#else
#error "invalid STM32_PLLMUL_VALUE value specified"
#endif
/**
* @brief PLL input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PREDIV_VALUE)
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
#else
#error "invalid STM32_PLLSRC value specified"
#endif
/* PLL input frequency range check.*/
#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/**
* @brief PLL output clock frequency.
*/
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
/* PLL output frequency range check.*/
#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
#endif
/**
* @brief System clock source.
*/
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
#define STM32_SYSCLK STM32_PLLCLKOUT
#elif (STM32_SW == STM32_SW_HSI)
#define STM32_SYSCLK STM32_HSICLK
#elif (STM32_SW == STM32_SW_HSE)
#define STM32_SYSCLK STM32_HSECLK
#else
#error "invalid STM32_SW value specified"
#endif
/* Check on the system clock.*/
#if STM32_SYSCLK > STM32_SYSCLK_MAX
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
#endif
/**
* @brief AHB frequency.
*/
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
#define STM32_HCLK (STM32_SYSCLK / 1)
#elif STM32_HPRE == STM32_HPRE_DIV2
#define STM32_HCLK (STM32_SYSCLK / 2)
#elif STM32_HPRE == STM32_HPRE_DIV4
#define STM32_HCLK (STM32_SYSCLK / 4)
#elif STM32_HPRE == STM32_HPRE_DIV8
#define STM32_HCLK (STM32_SYSCLK / 8)
#elif STM32_HPRE == STM32_HPRE_DIV16
#define STM32_HCLK (STM32_SYSCLK / 16)
#elif STM32_HPRE == STM32_HPRE_DIV64
#define STM32_HCLK (STM32_SYSCLK / 64)
#elif STM32_HPRE == STM32_HPRE_DIV128
#define STM32_HCLK (STM32_SYSCLK / 128)
#elif STM32_HPRE == STM32_HPRE_DIV256
#define STM32_HCLK (STM32_SYSCLK / 256)
#elif STM32_HPRE == STM32_HPRE_DIV512
#define STM32_HCLK (STM32_SYSCLK / 512)
#else
#error "invalid STM32_HPRE value specified"
#endif
/* AHB frequency check.*/
#if STM32_HCLK > STM32_SYSCLK_MAX
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
#endif
/**
* @brief APB frequency.
*/
#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
#define STM32_PCLK (STM32_HCLK / 1)
#elif STM32_PPRE == STM32_PPRE_DIV2
#define STM32_PCLK (STM32_HCLK / 2)
#elif STM32_PPRE == STM32_PPRE_DIV4
#define STM32_PCLK (STM32_HCLK / 4)
#elif STM32_PPRE == STM32_PPRE_DIV8
#define STM32_PCLK (STM32_HCLK / 8)
#elif STM32_PPRE == STM32_PPRE_DIV16
#define STM32_PCLK (STM32_HCLK / 16)
#else
#error "invalid STM32_PPRE value specified"
#endif
/* APB frequency check.*/
#if STM32_PCLK > STM32_PCLK_MAX
#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
#endif
/**
* @brief RTC clock.
*/
#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
#define STM32_RTCCLK STM32_LSECLK
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
#define STM32_RTCCLK STM32_LSICLK
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#define STM32_RTCCLK (STM32_HSECLK / 32)
#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
#define STM32_RTCCLK 0
#else
#error "invalid source selected for RTC clock"
#endif
/**
* @brief ADC frequency.
*/
#if STM32_ADCSW == STM32_ADCSW_HSI14
#define STM32_ADCCLK STM32_HSI14CLK
#elif STM32_ADCSW == STM32_ADCSW_PCLK
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
#define STM32_ADCCLK (STM32_PCLK / 2)
#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
#define STM32_ADCCLK (STM32_PCLK / 4)
#else
#error "invalid STM32_ADCPRE value specified"
#endif
#else
#error "invalid source selected for ADC clock"
#endif
/* ADC frequency check.*/
#if STM32_ADCCLK > STM32_ADCCLK_MAX
#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
#endif
/**
* @brief CEC frequency.
*/
#if STM32_CECSW == STM32_CECSW_HSI
#define STM32_CECCLK STM32_HSICLK
#elif STM32_CECSW == STM32_CECSW_LSE
#define STM32_CECCLK STM32_LSECLK
#else
#error "invalid source selected for CEC clock"
#endif
/**
* @brief I2C1 frequency.
*/
#if STM32_I2CSW == STM32_I2C1SW_HSI
#define STM32_I2C1CLK STM32_HSICLK
#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
#define STM32_I2C1CLK STM32_SYSCLK
#else
#error "invalid source selected for I2C1 clock"
#endif
/**
* @brief USART1 frequency.
*/
#if STM32_USART1SW == STM32_USART1SW_PCLK
#define STM32_USART1CLK STM32_PCLK
#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK
#elif STM32_USART1SW == STM32_USART1SW_LSECLK
#define STM32_USART1CLK STM32_LSECLK
#elif STM32_USART1SW == STM32_USART1SW_HSICLK
#define STM32_USART1CLK STM32_HSICLK
#else
#error "invalid source selected for USART1 clock"
#endif
/**
* @brief USART2 frequency.
*/
#define STM32_USART2CLK STM32_PCLK
/**
* @brief Timers clock.
*/
#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
#define STM32_TIMCLK1 (STM32_PCLK * 1)
#define STM32_TIMCLK2 (STM32_PCLK * 1)
#else
#define STM32_TIMCLK1 (STM32_PCLK * 2)
#define STM32_TIMCLK2 (STM32_PCLK * 2)
#endif
/**
* @brief Flash settings.
*/
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
#define STM32_FLASHBITS 0x00000010
#else
#define STM32_FLASHBITS 0x00000011
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/* STM32 ISR, DMA and RCC helpers.*/
#include "stm32_isr.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
#ifdef __cplusplus
extern "C" {
#endif
void hal_lld_init(void);
void stm32_clock_init(void);
#ifdef __cplusplus
}
#endif
#endif /* _HAL_LLD_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @defgroup STM32F0xx_DRIVERS STM32F0xx Drivers
* @details This section describes all the supported drivers on the STM32F0xx
* platform and the implementation details of the single drivers.
*
* @ingroup platforms
*/
/**
* @defgroup STM32F0xx_HAL STM32F0xx Initialization Support
* @details The STM32F0xx HAL support is responsible for system initialization.
*
* @section stm32f0xx_hal_1 Supported HW resources
* - PLL1.
* - RCC.
* - Flash.
* .
* @section stm32f0xx_hal_2 STM32F0xx HAL driver implementation features
* - PLL startup and stabilization.
* - Clock tree initialization.
* - Clock source selection.
* - Flash wait states initialization based on the selected clock options.
* - SYSTICK initialization based on current clock and kernel required rate.
* - DMA support initialization.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_ADC STM32F0xx ADC Support
* @details The STM32F0xx ADC driver supports the ADC peripherals using DMA
* channels for maximum performance.
*
* @section stm32f0xx_adc_1 Supported HW resources
* - ADC1.
* - DMA1.
* .
* @section stm32f0xx_adc_2 STM32F0xx ADC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Streaming conversion using DMA for maximum performance.
* - Programmable ADC interrupt priority level.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - DMA errors detection.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_EXT STM32F0xx EXT Support
* @details The STM32F0xx EXT driver uses the EXTI peripheral.
*
* @section stm32f0xx_ext_1 Supported HW resources
* - EXTI.
* .
* @section stm32f0xx_ext_2 STM32F0xx EXT driver implementation features
* - Each EXTI channel can be independently enabled and programmed.
* - Programmable EXTI interrupts priority level.
* - Capability to work as event sources (WFE) rather than interrupt sources.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_GPT STM32F0xx GPT Support
* @details The STM32F0xx GPT driver uses the TIMx peripherals.
*
* @section stm32f0xx_gpt_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* .
* @section stm32f0xx_gpt_2 STM32F0xx GPT driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_ICU STM32F0xx ICU Support
* @details The STM32F0xx ICU driver uses the TIMx peripherals.
*
* @section stm32f0xx_icu_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* .
* @section stm32f0xx_icu_2 STM32F0xx ICU driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_PAL STM32F0xx PAL Support
* @details The STM32F0xx PAL driver uses the GPIO peripherals.
*
* @section stm32f0xx_pal_1 Supported HW resources
* - GPIOA.
* - GPIOB.
* - GPIOC.
* - GPIOD.
* - GPIOF.
* .
* @section stm32f0xx_pal_2 STM32F0xx PAL driver implementation features
* The PAL driver implementation fully supports the following hardware
* capabilities:
* - 16 bits wide ports.
* - Atomic set/reset functions.
* - Atomic set+reset function (atomic bus operations).
* - Output latched regardless of the pad setting.
* - Direct read of input pads regardless of the pad setting.
* .
* @section stm32f0xx_pal_3 Supported PAL setup modes
* The STM32F0xx PAL driver supports the following I/O modes:
* - @p PAL_MODE_RESET.
* - @p PAL_MODE_UNCONNECTED.
* - @p PAL_MODE_INPUT.
* - @p PAL_MODE_INPUT_PULLUP.
* - @p PAL_MODE_INPUT_PULLDOWN.
* - @p PAL_MODE_INPUT_ANALOG.
* - @p PAL_MODE_OUTPUT_PUSHPULL.
* - @p PAL_MODE_OUTPUT_OPENDRAIN.
* - @p PAL_MODE_ALTERNATE (non standard).
* .
* Any attempt to setup an invalid mode is ignored.
*
* @section stm32f0xx_pal_4 Suboptimal behavior
* The STM32F0xx GPIO is less than optimal in several areas, the limitations
* should be taken in account while using the PAL driver:
* - Pad/port toggling operations are not atomic.
* - Pad/group mode setup is not atomic.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_PWM STM32F0xx PWM Support
* @details The STM32F0xx PWM driver uses the TIMx peripherals.
*
* @section stm32f0xx_pwm_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* .
* @section stm32f0xx_pwm_2 STM32F0xx PWM driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Four independent PWM channels per timer.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_SERIAL STM32F0xx Serial Support
* @details The STM32F0xx Serial driver uses the USART/UART peripherals in a
* buffered, interrupt driven, implementation.
*
* @section stm32f0xx_serial_1 Supported HW resources
* The serial driver can support any of the following hardware resources:
* - USART1.
* - USART2.
* .
* @section stm32f0xx_serial_2 STM32F0xx Serial driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Fully interrupt driven.
* - Programmable priority levels for each UART/USART.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_SPI STM32F0xx SPI Support
* @details The SPI driver supports the STM32F0xx SPI peripherals using DMA
* channels for maximum performance.
*
* @section stm32f0xx_spi_1 Supported HW resources
* - SPI1.
* - SPI2.
* - DMA1.
* .
* @section stm32f0xx_spi_2 STM32F0xx SPI driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each SPI can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable interrupt priority levels for each SPI.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_UART STM32F0xx UART Support
* @details The UART driver supports the STM32F0xx USART peripherals using DMA
* channels for maximum performance.
*
* @section stm32f0xx_uart_1 Supported HW resources
* The UART driver can support any of the following hardware resources:
* - USART1.
* - USART2.
* - DMA1.
* .
* @section stm32f0xx_uart_2 STM32F0xx UART driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable interrupt priority levels for each UART/USART.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_PLATFORM_DRIVERS STM32F0xx Platform Drivers
* @details Platform support drivers. Platform drivers do not implement HAL
* standard driver templates, their role is to support platform
* specific functionalities.
*
* @ingroup STM32F0xx_DRIVERS
*/
/**
* @defgroup STM32F0xx_DMA STM32F0xx DMA Support
* @details This DMA helper driver is used by the other drivers in order to
* access the shared DMA resources in a consistent way.
*
* @section stm32f0xx_dma_1 Supported HW resources
* The DMA driver can support any of the following hardware resources:
* - DMA1.
* - DMA2 (where present).
* .
* @section stm32f0xx_dma_2 STM32F0xx DMA driver implementation features
* - Exports helper functions/macros to the other drivers that share the
* DMA resource.
* - Automatic DMA clock stop when not in use by any driver.
* - DMA streams and interrupt vectors sharing among multiple drivers.
* .
* @ingroup STM32F0xx_PLATFORM_DRIVERS
*/
/**
* @defgroup STM32F0xx_ISR STM32F0xx ISR Support
* @details This ISR helper driver is used by the other drivers in order to
* map ISR names to physical vector names.
*
* @ingroup STM32F0xx_PLATFORM_DRIVERS
*/
/**
* @defgroup STM32F0xx_RCC STM32F0xx RCC Support
* @details This RCC helper driver is used by the other drivers in order to
* access the shared RCC resources in a consistent way.
*
* @section stm32f0xx_rcc_1 Supported HW resources
* - RCC.
* .
* @section stm32f0xx_rcc_2 STM32F0xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
* - Peripherals clock disable.
* .
* @ingroup STM32F0xx_PLATFORM_DRIVERS
*/

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# List of all the STM32F0xx platform files.
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
${CHIBIOS}/os/hal/platforms/STM32 \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \
${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
${CHIBIOS}/os/hal/platforms/STM32/USARTv2

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/stm32_dma.c
* @brief DMA helper driver code.
*
* @addtogroup STM32F0xx_DMA
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
* shared resource, this driver allows to allocate and free DMA
* streams at runtime in order to allow all the other device
* drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
* ISRs when allocating streams.
* @{
*/
#include "ch.h"
#include "hal.h"
/* The following macro is only defined if some driver requiring DMA services
has been enabled.*/
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/**
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
*/
#define STM32_DMA1_STREAMS_MASK 0x0000007F
/**
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
*/
#define STM32_DMA2_STREAMS_MASK 0x00000F80
/**
* @brief Post-reset value of the stream CCR register.
*/
#define STM32_DMA_CCR_RESET_VALUE 0x00000000
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief DMA streams descriptors.
* @details This table keeps the association between an unique stream
* identifier and the involved physical registers.
* @note Don't use this array directly, use the appropriate wrapper macros
* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
*/
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
{DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
{DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_3_IRQn},
{DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel2_3_IRQn},
{DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_5_IRQn},
{DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel4_5_IRQn}
};
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief DMA ISR redirector type.
*/
typedef struct {
stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
void *dma_param; /**< @brief DMA callback parameter. */
} dma_isr_redir_t;
/**
* @brief Mask of the allocated streams.
*/
static uint32_t dma_streams_mask;
/**
* @brief DMA IRQ redirectors.
*/
static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/**
* @brief DMA1 stream 1 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector64) {
uint32_t flags;
CH_IRQ_PROLOGUE();
flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
if (dma_isr_redir[0].dma_func)
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 streams 2 and 3 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector68) {
uint32_t flags;
CH_IRQ_PROLOGUE();
/* Check on channel 2.*/
flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
if (flags & STM32_DMA_ISR_MASK) {
DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
if (dma_isr_redir[1].dma_func)
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
}
/* Check on channel 3.*/
flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
if (flags & STM32_DMA_ISR_MASK) {
DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
if (dma_isr_redir[2].dma_func)
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
}
CH_IRQ_EPILOGUE();
}
/**
* @brief DMA1 streams 4 and 5 shared interrupt handler.
*
* @isr
*/
CH_IRQ_HANDLER(Vector6C) {
uint32_t flags;
CH_IRQ_PROLOGUE();
/* Check on channel 4.*/
flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
if (flags & STM32_DMA_ISR_MASK) {
DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
if (dma_isr_redir[3].dma_func)
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
}
/* Check on channel 5.*/
flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
if (flags & STM32_DMA_ISR_MASK) {
DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
if (dma_isr_redir[4].dma_func)
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
}
CH_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief STM32 DMA helper initialization.
*
* @init
*/
void dmaInit(void) {
int i;
dma_streams_mask = 0;
for (i = 0; i < STM32_DMA_STREAMS; i++) {
_stm32_dma_streams[i].channel->CCR = 0;
dma_isr_redir[i].dma_func = NULL;
}
DMA1->IFCR = 0xFFFFFFFF;
}
/**
* @brief Allocates a DMA stream.
* @details The stream is allocated and, if required, the DMA clock enabled.
* The function also enables the IRQ vector associated to the stream
* and initializes its priority.
* @pre The stream must not be already in use or an error is returned.
* @post The stream is allocated and the default ISR handler redirected
* to the specified function.
* @post The stream ISR vector is enabled and its priority configured.
* @post The stream must be freed using @p dmaStreamRelease() before it can
* be reused with another peripheral.
* @post The stream is in its post-reset state.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] priority IRQ priority mask for the DMA stream
* @param[in] func handling function pointer, can be @p NULL
* @param[in] param a parameter to be passed to the handling function
* @return The operation status.
* @retval FALSE no error, stream taken.
* @retval TRUE error, stream already taken.
*
* @special
*/
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
uint32_t priority,
stm32_dmaisr_t func,
void *param) {
chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
/* Checks if the stream is already taken.*/
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
return TRUE;
/* Marks the stream as allocated.*/
dma_isr_redir[dmastp->selfindex].dma_func = func;
dma_isr_redir[dmastp->selfindex].dma_param = param;
dma_streams_mask |= (1 << dmastp->selfindex);
/* Enabling DMA clocks required by the current streams set.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
rccEnableDMA1(FALSE);
/* Putting the stream in a safe state.*/
dmaStreamDisable(dmastp);
dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
/* Enables the associated IRQ vector if a callback is defined.*/
if (func != NULL)
nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
return FALSE;
}
/**
* @brief Releases a DMA stream.
* @details The stream is freed and, if required, the DMA clock disabled.
* Trying to release a unallocated stream is an illegal operation
* and is trapped if assertions are enabled.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post The stream is again available.
* @note This function can be invoked in both ISR or thread context.
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
chDbgCheck(dmastp != NULL, "dmaStreamRelease");
/* Check if the streams is not taken.*/
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
"dmaStreamRelease(), #1", "not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
/* Marks the stream as not allocated.*/
dma_streams_mask &= ~(1 << dmastp->selfindex);
/* Shutting down clocks that are no more required, if any.*/
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
rccDisableDMA1(FALSE);
}
#endif /* STM32_DMA_REQUIRED */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/stm32_dma.h
* @brief DMA helper driver header.
* @note This file requires definitions from the ST header file stm32f0xx.h.
* @note This driver uses the new naming convention used for the STM32F2xx
* so the "DMA channels" are referred as "DMA streams".
*
* @addtogroup STM32F0xx_DMA
* @{
*/
#ifndef _STM32_DMA_H_
#define _STM32_DMA_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Total number of DMA streams.
* @note This is the total number of streams among all the DMA units.
*/
#define STM32_DMA_STREAMS 5
/**
* @brief Mask of the ISR bits passed to the DMA callback functions.
*/
#define STM32_DMA_ISR_MASK 0x0F
/**
* @brief Returns the channel associated to the specified stream.
*
* @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
* @param[in] c a stream/channel association word, one channel per
* nibble, not associated channels must be set to 0xF
* @return Always zero, in this platform there is no dynamic
* association between streams and channels.
*/
#define STM32_DMA_GETCHANNEL(n, c) 0
/**
* @brief Checks if a DMA priority is within the valid range.
* @param[in] prio DMA priority
*
* @retval The check result.
* @retval FALSE invalid DMA priority.
* @retval TRUE correct DMA priority.
*/
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
/**
* @brief Returns an unique numeric identifier for a DMA stream.
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return An unique numeric stream identifier.
*/
#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)
/**
* @brief Returns a DMA stream identifier mask.
*
*
* @param[in] dma the DMA unit number
* @param[in] stream the stream number
* @return A DMA stream identifier mask.
*/
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
(1 << STM32_DMA_STREAM_ID(dma, stream))
/**
* @brief Checks if a DMA stream unique identifier belongs to a mask.
* @param[in] id the stream numeric identifier
* @param[in] mask the stream numeric identifiers mask
*
* @retval The check result.
* @retval FALSE id does not belong to the mask.
* @retval TRUE id belongs to the mask.
*/
#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
/**
* @name DMA streams identifiers
* @{
*/
/**
* @brief Returns a pointer to a stm32_dma_stream_t structure.
*
* @param[in] id the stream numeric identifier
* @return A pointer to the stm32_dma_stream_t constant structure
* associated to the DMA stream.
*/
#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
/** @} */
/**
* @name CR register constants common to all DMA types
* @{
*/
#define STM32_DMA_CR_EN DMA_CCR_EN
#define STM32_DMA_CR_TEIE DMA_CCR_TEIE
#define STM32_DMA_CR_HTIE DMA_CCR_HTIE
#define STM32_DMA_CR_TCIE DMA_CCR_TCIE
#define STM32_DMA_CR_DIR_MASK (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
#define STM32_DMA_CR_DIR_P2M 0
#define STM32_DMA_CR_DIR_M2P DMA_CCR_DIR
#define STM32_DMA_CR_DIR_M2M DMA_CCR_MEM2MEM
#define STM32_DMA_CR_CIRC DMA_CCR_CIRC
#define STM32_DMA_CR_PINC DMA_CCR_PINC
#define STM32_DMA_CR_MINC DMA_CCR_MINC
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR_PSIZE
#define STM32_DMA_CR_PSIZE_BYTE 0
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR_PSIZE_0
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR_PSIZE_1
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR_MSIZE
#define STM32_DMA_CR_MSIZE_BYTE 0
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR_MSIZE_0
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR_MSIZE_1
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
STM32_DMA_CR_MSIZE_MASK)
#define STM32_DMA_CR_PL_MASK DMA_CCR_PL
#define STM32_DMA_CR_PL(n) ((n) << 12)
/** @} */
/**
* @name CR register constants only found in enhanced DMA
* @{
*/
#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
/** @} */
/**
* @name Status flags passed to the ISR callbacks
* @{
*/
#define STM32_DMA_ISR_FEIF 0
#define STM32_DMA_ISR_DMEIF 0
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief STM32 DMA stream descriptor structure.
*/
typedef struct {
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
uint8_t ishift; /**< @brief Bits offset in xIFCR
register. */
uint8_t selfindex; /**< @brief Index to self in array. */
uint8_t vector; /**< @brief Associated IRQ vector. */
} stm32_dma_stream_t;
/**
* @brief STM32 DMA ISR function type.
*
* @param[in] p parameter for the registered function
* @param[in] flags pre-shifted content of the ISR register, the bits
* are aligned to bit zero
*/
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Macro Functions
* @{
*/
/**
* @brief Associates a peripheral data register to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] addr value to be written in the CPAR register
*
* @special
*/
#define dmaStreamSetPeripheral(dmastp, addr) { \
(dmastp)->channel->CPAR = (uint32_t)(addr); \
}
/**
* @brief Associates a memory destination to a DMA stream.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] addr value to be written in the CMAR register
*
* @special
*/
#define dmaStreamSetMemory0(dmastp, addr) { \
(dmastp)->channel->CMAR = (uint32_t)(addr); \
}
/**
* @brief Sets the number of transfers to be performed.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] size value to be written in the CNDTR register
*
* @special
*/
#define dmaStreamSetTransactionSize(dmastp, size) { \
(dmastp)->channel->CNDTR = (uint32_t)(size); \
}
/**
* @brief Returns the number of transfers to be performed.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @return The number of transfers to be performed.
*
* @special
*/
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
/**
* @brief Programs the stream mode settings.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register
*
* @special
*/
#define dmaStreamSetMode(dmastp, mode) { \
(dmastp)->channel->CCR = (uint32_t)(mode); \
}
/**
* @brief DMA stream enable.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamEnable(dmastp) { \
(dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
}
/**
* @brief DMA stream disable.
* @details The function disables the specified stream and then clears any
* pending interrupt.
* @note This function can be invoked in both ISR or thread context.
* @note Interrupts enabling flags are set to zero after this call, see
* bug 3607518.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamDisable(dmastp) { \
(dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \
dmaStreamClearInterrupt(dmastp); \
}
/**
* @brief DMA stream interrupt sources clear.
* @note This function can be invoked in both ISR or thread context.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*
* @special
*/
#define dmaStreamClearInterrupt(dmastp) { \
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
}
/**
* @brief Starts a memory to memory operation using the specified stream.
* @note The default transfer data mode is "byte to byte" but it can be
* changed by specifying extra options in the @p mode parameter.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
* @param[in] mode value to be written in the CCR register, this value
* is implicitly ORed with:
* - @p STM32_DMA_CR_MINC
* - @p STM32_DMA_CR_PINC
* - @p STM32_DMA_CR_DIR_M2M
* - @p STM32_DMA_CR_EN
* .
* @param[in] src source address
* @param[in] dst destination address
* @param[in] n number of data units to copy
*/
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
dmaStreamSetPeripheral(dmastp, src); \
dmaStreamSetMemory0(dmastp, dst); \
dmaStreamSetTransactionSize(dmastp, n); \
dmaStreamSetMode(dmastp, (mode) | \
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
}
/**
* @brief Polled wait for DMA transfer end.
* @pre The stream must have been allocated using @p dmaStreamAllocate().
* @post After use the stream can be released using @p dmaStreamRelease().
*
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
*/
#define dmaWaitCompletion(dmastp) { \
while ((dmastp)->channel->CNDTR > 0) \
; \
dmaStreamDisable(dmastp); \
}
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
#endif
#ifdef __cplusplus
extern "C" {
#endif
void dmaInit(void);
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
uint32_t priority,
stm32_dmaisr_t func,
void *param);
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
#ifdef __cplusplus
}
#endif
#endif /* _STM32_DMA_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/stm32_isr.h
* @brief ISR remapper driver header.
*
* @addtogroup STM32F0xx_ISR
* @{
*/
#ifndef _STM32_ISR_H_
#define _STM32_ISR_H_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @name ISR names and numbers remapping
* @{
*/
/*
* I2C units.
*/
#define STM32_I2C1_GLOBAL_HANDLER Vector9C
#define STM32_I2C1_GLOBAL_NUMBER 23
#define STM32_I2C2_GLOBAL_HANDLER VectorA0
#define STM32_I2C2_GLOBAL_NUMBER 24
/*
* TIM units.
*/
#define STM32_TIM1_UP_HANDLER Vector74
#define STM32_TIM1_CC_HANDLER Vector78
#define STM32_TIM2_HANDLER Vector7C
#define STM32_TIM3_HANDLER Vector80
#define STM32_TIM1_UP_NUMBER 13
#define STM32_TIM1_CC_NUMBER 14
#define STM32_TIM2_NUMBER 15
#define STM32_TIM3_NUMBER 16
/*
* USART units.
*/
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART1_NUMBER 27
#define STM32_USART2_NUMBER 28
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#endif /* _STM32_ISR_H_ */
/** @} */

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/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/stm32_rcc.h
* @brief RCC helper driver header.
* @note This file requires definitions from the ST header file
* @p stm32f0xx.h.
*
* @addtogroup STM32F0xx_RCC
* @{
*/
#ifndef _STM32_RCC_
#define _STM32_RCC_
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @name Generic RCC operations
* @{
*/
/**
* @brief Enables the clock of one or more peripheral on the APB1 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB1(mask, lp) { \
RCC->APB1ENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB1 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB1 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAPB1(mask, lp) { \
RCC->APB1ENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB1 bus.
*
* @param[in] mask APB1 peripherals mask
*
* @api
*/
#define rccResetAPB1(mask) { \
RCC->APB1RSTR |= (mask); \
RCC->APB1RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the APB2 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAPB2(mask, lp) { \
RCC->APB2ENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the APB2 bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask APB2 peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAPB2(mask, lp) { \
RCC->APB2ENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the APB2 bus.
*
* @param[in] mask APB2 peripherals mask
*
* @api
*/
#define rccResetAPB2(mask) { \
RCC->APB2RSTR |= (mask); \
RCC->APB2RSTR = 0; \
}
/**
* @brief Enables the clock of one or more peripheral on the AHB bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask AHB peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableAHB(mask, lp) { \
RCC->AHBENR |= (mask); \
}
/**
* @brief Disables the clock of one or more peripheral on the AHB bus.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] mask AHB peripherals mask
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableAHB(mask, lp) { \
RCC->AHBENR &= ~(mask); \
}
/**
* @brief Resets one or more peripheral on the AHB bus.
*
* @param[in] mask AHB peripherals mask
*
* @api
*/
#define rccResetAHB(mask) { \
RCC->AHBRSTR |= (mask); \
RCC->AHBRSTR = 0; \
}
/** @} */
/**
* @name ADC peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the ADC1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
* @brief Disables the ADC1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
/**
* @brief Resets the ADC1 peripheral.
*
* @api
*/
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** @} */
/**
* @name PWR interface specific RCC operations
* @{
*/
/**
* @brief Enables the PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Disables PWR interface clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
/**
* @brief Resets the PWR interface.
*
* @api
*/
#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
/** @} */
/**
* @name DMA peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the DMA1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
/**
* @brief Disables the DMA1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
/**
* @brief Resets the DMA1 peripheral.
* @note Not supported in this family, does nothing.
*
* @api
*/
#define rccResetDMA1()
/** @} */
/**
* @name I2C peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the I2C1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
* @brief Disables the I2C1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
/**
* @brief Resets the I2C1 peripheral.
*
* @api
*/
#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
/**
* @brief Enables the I2C2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
* @brief Disables the I2C2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
/**
* @brief Resets the I2C2 peripheral.
*
* @api
*/
#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
/** @} */
/**
* @name SPI peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the SPI1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
* @brief Disables the SPI1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
/**
* @brief Resets the SPI1 peripheral.
*
* @api
*/
#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
/**
* @brief Enables the SPI2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
* @brief Disables the SPI2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
/**
* @brief Resets the SPI2 peripheral.
*
* @api
*/
#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
/** @} */
/**
* @name TIM peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the TIM1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
/**
* @brief Disables the TIM1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
/**
* @brief Resets the TIM1 peripheral.
*
* @api
*/
#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
/**
* @brief Enables the TIM2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
* @brief Disables the TIM2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
/**
* @brief Resets the TIM2 peripheral.
*
* @api
*/
#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
/**
* @brief Enables the TIM3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
* @brief Disables the TIM3 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
/**
* @brief Resets the TIM3 peripheral.
*
* @api
*/
#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
/** @} */
/**
* @name USART/UART peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the USART1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
* @brief Disables the USART1 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
/**
* @brief Resets the USART1 peripheral.
*
* @api
*/
#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
/**
* @brief Enables the USART2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
* @brief Disables the USART2 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
/**
* @brief Resets the USART2 peripheral.
*
* @api
*/
#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
/**
* @brief Enables the CRC peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
/**
* @brief Disables the CRC peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp)
/**
* @brief Resets the CRC peripheral.
*
* @api
*/
#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
/**
* @brief Enables the WWDG peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp)
/**
* @brief Disables the WWDG peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableWWDG(lp) rccDisableAPB1(RCC_APB1ENR_WWDGEN, lp)
/**
* @brief Resets the WWDG peripheral.
*
* @api
*/
#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST)
/** @} */
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _STM32_RCC_ */
/** @} */

198
os/hal/platforms/STM32F0xx/stm32_registry.h Normal file
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@ -0,0 +1,198 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file STM32F0xx/stm32_registry.h
* @brief STM32F0xx capabilities registry.
*
* @addtogroup HAL
* @{
*/
#ifndef _STM32_REGISTRY_H_
#define _STM32_REGISTRY_H_
/*===========================================================================*/
/* Platform capabilities. */
/*===========================================================================*/
/**
* @name STM32F0xx capabilities
* @{
*/
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) | \
STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_ADC1_DMA_CHN 0x00000000
#define STM32_HAS_ADC2 FALSE
#define STM32_ADC2_DMA_MSK 0x00000000
#define STM32_ADC2_DMA_CHN 0x00000000
#define STM32_HAS_ADC3 FALSE
#define STM32_ADC3_DMA_MSK 0x00000000
#define STM32_ADC3_DMA_CHN 0x00000000
#define STM32_HAS_ADC4 FALSE
#define STM32_ADC4_DMA_MSK 0x00000000
#define STM32_ADC4_DMA_CHN 0x00000000
/* CAN attributes.*/
#define STM32_HAS_CAN1 FALSE
#define STM32_HAS_CAN2 FALSE
#define STM32_CAN_MAX_FILTERS 0
/* DAC attributes.*/
#define STM32_HAS_DAC TRUE
/* DMA attributes.*/
#define STM32_ADVANCED_DMA FALSE
#define STM32_HAS_DMA1 TRUE
#define STM32_HAS_DMA2 FALSE
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
/* EXTI attributes.*/
#define STM32_EXTI_NUM_CHANNELS 28
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD TRUE
#define STM32_HAS_GPIOE FALSE
#define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOH FALSE
#define STM32_HAS_GPIOI FALSE
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_I2C1_RX_DMA_CHN 0x00000000
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_I2C1_TX_DMA_CHN 0x00000000
#define STM32_HAS_I2C2 TRUE
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_I2C2_RX_DMA_CHN 0x00000000
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_I2C2_TX_DMA_CHN 0x00000000
#define STM32_HAS_I2C3 FALSE
#define STM32_I2C3_RX_DMA_MSK 0
#define STM32_I2C3_RX_DMA_CHN 0x00000000
#define STM32_I2C3_TX_DMA_MSK 0
#define STM32_I2C3_TX_DMA_CHN 0x00000000
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS FALSE
#define STM32_RTC_IS_CALENDAR TRUE
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
/* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
#define STM32_SPI1_RX_DMA_CHN 0x00000000
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
#define STM32_SPI1_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_SPI2_RX_DMA_CHN 0x00000000
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
#define STM32_SPI2_TX_DMA_CHN 0x00000000
#define STM32_HAS_SPI3 FALSE
#define STM32_SPI3_RX_DMA_MSK 0
#define STM32_SPI3_RX_DMA_CHN 0x00000000
#define STM32_SPI3_TX_DMA_MSK 0
#define STM32_SPI3_TX_DMA_CHN 0x00000000
/* TIM attributes.*/
#define STM32_HAS_TIM1 TRUE
#define STM32_HAS_TIM2 TRUE
#define STM32_HAS_TIM3 TRUE
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM6 TRUE
#define STM32_HAS_TIM7 FALSE
#define STM32_HAS_TIM8 FALSE
#define STM32_HAS_TIM9 FALSE
#define STM32_HAS_TIM10 FALSE
#define STM32_HAS_TIM11 FALSE
#define STM32_HAS_TIM12 FALSE
#define STM32_HAS_TIM13 FALSE
#define STM32_HAS_TIM14 TRUE
#define STM32_HAS_TIM15 TRUE
#define STM32_HAS_TIM16 TRUE
#define STM32_HAS_TIM17 TRUE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00000000
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) | \
STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_USART1_TX_DMA_CHN 0x00000000
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART2_RX_DMA_CHN 0x00000000
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_USART2_TX_DMA_CHN 0x00000000
#define STM32_HAS_USART3 FALSE
#define STM32_USART3_RX_DMA_MSK 0
#define STM32_USART3_RX_DMA_CHN 0x00000000
#define STM32_USART3_TX_DMA_MSK 0
#define STM32_USART3_TX_DMA_CHN 0x00000000
#define STM32_HAS_UART4 FALSE
#define STM32_UART4_RX_DMA_MSK 0
#define STM32_UART4_RX_DMA_CHN 0x00000000
#define STM32_UART4_TX_DMA_MSK 0
#define STM32_UART4_TX_DMA_CHN 0x00000000
#define STM32_HAS_UART5 FALSE
#define STM32_UART5_RX_DMA_MSK 0
#define STM32_UART5_RX_DMA_CHN 0x00000000
#define STM32_UART5_TX_DMA_MSK 0
#define STM32_UART5_TX_DMA_CHN 0x00000000
#define STM32_HAS_USART6 FALSE
#define STM32_USART6_RX_DMA_MSK 0
#define STM32_USART6_RX_DMA_CHN 0x00000000
#define STM32_USART6_TX_DMA_MSK 0
#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB TRUE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
/** @} */
#endif /* _STM32_REGISTRY_H_ */
/** @} */

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6
os/rt/ports/ARMCMx/chcore_v6m.c
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@ -19,7 +19,7 @@
*/
/**
* @file GCC/ARMCMx/chcore_v6m.c
* @file ARMCMx/chcore_v6m.c
* @brief ARMv6-M architecture port code.
*
* @addtogroup ARMCMx_V6M_CORE
@ -58,7 +58,7 @@
* @details The NMI vector is used for exception mode re-entering after a
* context switch.
*/
void NMIVector(void) {
void NMI_Handler(void) {
/* The extctx structure is pointed by the PSP register.*/
struct extctx *ctxp = (struct extctx *)__get_PSP();
@ -81,7 +81,7 @@ void NMIVector(void) {
* @details The PendSV vector is used for exception mode re-entering after a
* context switch.
*/
void PendSVVector(void) {
void PendSV_Handler(void) {
/* The extctx structure is pointed by the PSP register.*/
struct extctx *ctxp = (struct extctx *)__get_PSP();