From b80e79d47ff0c07c20090e9b0596ad49dc0ac702 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 7 Jul 2019 13:40:51 +0000 Subject: [PATCH] Implemented TIMPRE setting for STM32F7xx HAL. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12881 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../cfg/mcuconf.h | 1 + .../NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h | 1 + .../cfg/stm32f746_discovery/mcuconf.h | 1 + .../cfg/stm32f746_discovery/mcuconf.h | 1 + .../cfg/stm32f769_discovery/mcuconf.h | 1 + .../RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h | 1 + .../RT-STM32F746G-DISCOVERY/cfg/mcuconf.h | 1 + .../RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h | 1 + .../RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h | 1 + .../RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h | 1 + .../RT-STM32F769I-DISCOVERY/cfg/mcuconf.h | 1 + os/hal/ports/STM32/STM32F7xx/hal_lld.c | 3 +++ os/hal/ports/STM32/STM32F7xx/hal_lld.h | 27 +++++++++++++++++++ readme.txt | 1 + testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h | 1 + testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h | 1 + testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h | 1 + testhal/STM32/STM32F7xx/SPI/mcuconf.h | 1 + testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h | 1 + .../cfg/stm32f756zg_nucleo144/mcuconf.h | 1 + .../PAL/cfg/stm32f746_discovery/mcuconf.h | 1 + .../RTC/cfg/stm32f746_discovery/mcuconf.h | 1 + .../UART/cfg/stm32f746_discovery/mcuconf.h | 1 + .../USB_CDC/cfg/stm32f746_discovery/mcuconf.h | 1 + .../conf/mcuconf_stm32f72xxx/mcuconf.h.ftl | 1 + .../conf/mcuconf_stm32f746xx/mcuconf.h.ftl | 1 + .../conf/mcuconf_stm32f76xxx/mcuconf.h.ftl | 1 + 27 files changed, 55 insertions(+) diff --git a/demos/STM32/NASA-OSAL-STM32F746G-DISCOVERY/cfg/mcuconf.h b/demos/STM32/NASA-OSAL-STM32F746G-DISCOVERY/cfg/mcuconf.h index 2ee801f0b..6901dd563 100644 --- a/demos/STM32/NASA-OSAL-STM32F746G-DISCOVERY/cfg/mcuconf.h +++ b/demos/STM32/NASA-OSAL-STM32F746G-DISCOVERY/cfg/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h b/demos/STM32/NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h index dde3318b8..279b3036b 100644 --- a/demos/STM32/NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h +++ b/demos/STM32/NIL-STM32F746G-DISCOVERY/cfg/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32-LWIP-FATFS-USB-HTTPS/cfg/stm32f746_discovery/mcuconf.h b/demos/STM32/RT-STM32-LWIP-FATFS-USB-HTTPS/cfg/stm32f746_discovery/mcuconf.h index 899f46955..647e17591 100644 --- a/demos/STM32/RT-STM32-LWIP-FATFS-USB-HTTPS/cfg/stm32f746_discovery/mcuconf.h +++ b/demos/STM32/RT-STM32-LWIP-FATFS-USB-HTTPS/cfg/stm32f746_discovery/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f746_discovery/mcuconf.h b/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f746_discovery/mcuconf.h index 899f46955..647e17591 100644 --- a/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f746_discovery/mcuconf.h +++ b/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f746_discovery/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f769_discovery/mcuconf.h b/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f769_discovery/mcuconf.h index 8fba2440d..6498b8a02 100644 --- a/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f769_discovery/mcuconf.h +++ b/demos/STM32/RT-STM32-LWIP-FATFS-USB/cfg/stm32f769_discovery/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h index fab6b634a..b8987d3ec 100644 --- a/demos/STM32/RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32F722ZE-NUCLEO144/cfg/mcuconf.h @@ -64,6 +64,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32F746G-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32F746G-DISCOVERY/cfg/mcuconf.h index dde3318b8..279b3036b 100644 --- a/demos/STM32/RT-STM32F746G-DISCOVERY/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32F746G-DISCOVERY/cfg/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h index e40bd381d..6b10888f4 100644 --- a/demos/STM32/RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32F746ZG-NUCLEO144/cfg/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h index e40bd381d..6b10888f4 100644 --- a/demos/STM32/RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32F756ZG-NUCLEO144/cfg/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h index dc0640b1a..5ed5e4db9 100644 --- a/demos/STM32/RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32F767ZI-NUCLEO144/cfg/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32F769I-DISCOVERY/cfg/mcuconf.h index 342c27b1b..aea81bf65 100644 --- a/demos/STM32/RT-STM32F769I-DISCOVERY/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/cfg/mcuconf.h @@ -65,6 +65,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c index 0014fa578..d7f0cfdf8 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c @@ -274,6 +274,9 @@ void stm32_clock_init(void) { #endif #if STM32_SAI1SEL != STM32_SAI1SEL_OFF dckcfgr1 |= STM32_SAI1SEL; +#endif +#if STM32_TIMPRE_ENABLE == TRUE + dckcfgr1 |= RCC_DCKCFGR1_TIMPRE; #endif RCC->DCKCFGR1 = dckcfgr1; } diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index dbdd9ed7d..474b41fa5 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -650,6 +650,13 @@ #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 #endif +/** + * @brief TIM clock prescaler selection. + */ +#if !defined(STM32_TIMPRE_ENABLE) || defined(__DOXYGEN__) +#define STM32_TIMPRE_ENABLE FALSE +#endif + /** * @brief I2S clock source. */ @@ -2061,20 +2068,40 @@ /** * @brief Clock of timers connected to APB1 */ +#if (STM32_TIMPRE_ENABLE == FALSE) || defined(__DOXYGEN__) #if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) #define STM32_TIMCLK1 (STM32_PCLK1 * 1) #else #define STM32_TIMCLK1 (STM32_PCLK1 * 2) #endif +#else +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \ + (STM32_PPRE1 == STM32_PPRE1_DIV2) || \ + (STM32_PPRE1 == STM32_PPRE1_DIV4) +#define STM32_TIMCLK1 (STM32_HCLK * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 4) +#endif +#endif /** * @brief Clock of timers connected to APB2. */ +#if (STM32_TIMPRE_ENABLE == FALSE) || defined(__DOXYGEN__) #if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) #define STM32_TIMCLK2 (STM32_PCLK2 * 1) #else #define STM32_TIMCLK2 (STM32_PCLK2 * 2) #endif +#else +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \ + (STM32_PPRE2 == STM32_PPRE2_DIV2) || \ + (STM32_PPRE2 == STM32_PPRE2_DIV4) +#define STM32_TIMCLK2 (STM32_HCLK * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 4) +#endif +#endif /** * @brief Flash settings. diff --git a/readme.txt b/readme.txt index 2ec3078c5..8af786a91 100644 --- a/readme.txt +++ b/readme.txt @@ -74,6 +74,7 @@ ***************************************************************************** *** Next *** +- NEW: Implemented TIMPRE setting for STM32F7xx HAL. - NEW: Merged FatFS 0.13c. - NEW: Added a "library generator" project for RT, it allows to generate a library with a pre-configured RT. It also includes diff --git a/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h b/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h index 39884c16f..972b77aa8 100644 --- a/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h +++ b/testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h index a06b371c3..8cc5e7be8 100644 --- a/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h +++ b/testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h b/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h index 81f4706ce..40fc15aaf 100644 --- a/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h +++ b/testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/STM32F7xx/SPI/mcuconf.h b/testhal/STM32/STM32F7xx/SPI/mcuconf.h index 54bdd070e..97054cbea 100644 --- a/testhal/STM32/STM32F7xx/SPI/mcuconf.h +++ b/testhal/STM32/STM32F7xx/SPI/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h b/testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h index e8c2f81d0..b0ecf50aa 100644 --- a/testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h +++ b/testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/multi/CRYPTO/cfg/stm32f756zg_nucleo144/mcuconf.h b/testhal/STM32/multi/CRYPTO/cfg/stm32f756zg_nucleo144/mcuconf.h index c0109a4a7..3199df2f7 100644 --- a/testhal/STM32/multi/CRYPTO/cfg/stm32f756zg_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/CRYPTO/cfg/stm32f756zg_nucleo144/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/multi/PAL/cfg/stm32f746_discovery/mcuconf.h b/testhal/STM32/multi/PAL/cfg/stm32f746_discovery/mcuconf.h index dde3318b8..279b3036b 100644 --- a/testhal/STM32/multi/PAL/cfg/stm32f746_discovery/mcuconf.h +++ b/testhal/STM32/multi/PAL/cfg/stm32f746_discovery/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/multi/RTC/cfg/stm32f746_discovery/mcuconf.h b/testhal/STM32/multi/RTC/cfg/stm32f746_discovery/mcuconf.h index f68c554e2..13c5044f2 100644 --- a/testhal/STM32/multi/RTC/cfg/stm32f746_discovery/mcuconf.h +++ b/testhal/STM32/multi/RTC/cfg/stm32f746_discovery/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/multi/UART/cfg/stm32f746_discovery/mcuconf.h b/testhal/STM32/multi/UART/cfg/stm32f746_discovery/mcuconf.h index f68c554e2..13c5044f2 100644 --- a/testhal/STM32/multi/UART/cfg/stm32f746_discovery/mcuconf.h +++ b/testhal/STM32/multi/UART/cfg/stm32f746_discovery/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32f746_discovery/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32f746_discovery/mcuconf.h index e1a779771..36e9bb274 100644 --- a/testhal/STM32/multi/USB_CDC/cfg/stm32f746_discovery/mcuconf.h +++ b/testhal/STM32/multi/USB_CDC/cfg/stm32f746_discovery/mcuconf.h @@ -62,6 +62,7 @@ #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK #define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_TIMPRE_ENABLE FALSE #define STM32_I2SSRC STM32_I2SSRC_OFF #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SP_VALUE 4 diff --git a/tools/ftl/processors/conf/mcuconf_stm32f72xxx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32f72xxx/mcuconf.h.ftl index ac243dae9..ca02b36cf 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32f72xxx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32f72xxx/mcuconf.h.ftl @@ -75,6 +75,7 @@ #define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"} #define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"} #define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"} +#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"} #define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"} #define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"} #define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"} diff --git a/tools/ftl/processors/conf/mcuconf_stm32f746xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32f746xx/mcuconf.h.ftl index d140ef34f..332fa1f91 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32f746xx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32f746xx/mcuconf.h.ftl @@ -73,6 +73,7 @@ #define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"} #define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"} #define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"} +#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"} #define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"} #define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"} #define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"} diff --git a/tools/ftl/processors/conf/mcuconf_stm32f76xxx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32f76xxx/mcuconf.h.ftl index e72c65cb4..99140890d 100644 --- a/tools/ftl/processors/conf/mcuconf_stm32f76xxx/mcuconf.h.ftl +++ b/tools/ftl/processors/conf/mcuconf_stm32f76xxx/mcuconf.h.ftl @@ -76,6 +76,7 @@ #define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"} #define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"} #define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"} +#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"} #define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"} #define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"} #define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"}