From b87e6f0f8c17154c2c11a8fb29e61f9a07e03a42 Mon Sep 17 00:00:00 2001 From: edolomb Date: Mon, 26 Oct 2020 17:45:53 +0000 Subject: [PATCH] Support for STM32H750B-DK: - Added STM32H750xB.ld - Added ST_STM32H750XB_DISCOVERY board - Updated hal_mii.h - Added RT-STM32H750XB-DISCOVERY demo git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13891 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../STM32/RT-STM32H750XB-DISCOVERY/.cproject | 55 + demos/STM32/RT-STM32H750XB-DISCOVERY/.project | 96 + demos/STM32/RT-STM32H750XB-DISCOVERY/Makefile | 189 ++ .../RT-STM32H750XB-DISCOVERY/cfg/chconf.h | 776 ++++++++ .../RT-STM32H750XB-DISCOVERY/cfg/halconf.h | 551 ++++++ .../RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h | 500 +++++ demos/STM32/RT-STM32H750XB-DISCOVERY/main.c | 79 + .../boards/ST_STM32H750XB_DISCOVERY/board.c | 266 +++ .../boards/ST_STM32H750XB_DISCOVERY/board.h | 1733 +++++++++++++++++ .../boards/ST_STM32H750XB_DISCOVERY/board.mk | 9 + .../ST_STM32H750XB_DISCOVERY/cfg/board.chcfg | 1459 ++++++++++++++ .../ST_STM32H750XB_DISCOVERY/cfg/board.fmpp | 15 + 12 files changed, 5728 insertions(+) create mode 100644 demos/STM32/RT-STM32H750XB-DISCOVERY/.cproject create mode 100644 demos/STM32/RT-STM32H750XB-DISCOVERY/.project create mode 100644 demos/STM32/RT-STM32H750XB-DISCOVERY/Makefile create mode 100644 demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/chconf.h create mode 100644 demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h create mode 100644 demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h create mode 100644 demos/STM32/RT-STM32H750XB-DISCOVERY/main.c create mode 100644 os/hal/boards/ST_STM32H750XB_DISCOVERY/board.c create mode 100644 os/hal/boards/ST_STM32H750XB_DISCOVERY/board.h create mode 100644 os/hal/boards/ST_STM32H750XB_DISCOVERY/board.mk create mode 100644 os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.chcfg create mode 100644 os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.fmpp diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/.cproject b/demos/STM32/RT-STM32H750XB-DISCOVERY/.cproject new file mode 100644 index 000000000..d71d31f85 --- /dev/null +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/.cproject @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/.project b/demos/STM32/RT-STM32H750XB-DISCOVERY/.project new file mode 100644 index 000000000..b09e31d5b --- /dev/null +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/.project @@ -0,0 +1,96 @@ + + + RT-STM32H750XB-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_STM32H750XB_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/Makefile b/demos/STM32/RT-STM32H750XB-DISCOVERY/Makefile new file mode 100644 index 000000000..0319aed96 --- /dev/null +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/Makefile @@ -0,0 +1,189 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv5-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m7 + +# Imported source files and paths. +CHIBIOS := ../../.. +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS)/test/lib/test.mk +include $(CHIBIOS)/test/rt/rt_test.mk +include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32H750xB.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/chconf.h b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/chconf.h new file mode 100644 index 000000000..75f43de7f --- /dev/null +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/chconf.h @@ -0,0 +1,776 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_NONE +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add system instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @param[in] tp pointer to the @p thread_t structure + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + * + * @param[in] ntp thread being switched in + * @param[in] otp thread being switched out + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h new file mode 100644 index 000000000..cdbad17f1 --- /dev/null +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h @@ -0,0 +1,551 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_1_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC TRUE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SIO driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SIO_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Support for thread synchronization API. + */ +#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__) +#define SIO_USE_SYNCHRONIZATION TRUE +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h new file mode 100644 index 000000000..b6a9cc38b --- /dev/null +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h @@ -0,0 +1,500 @@ +/* + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32H7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32H7xx_MCUCONF +#define STM32H742_MCUCONF +#define STM32H743_MCUCONF +#define STM32H753_MCUCONF +#define STM32H745_MCUCONF +#define STM32H755_MCUCONF +#define STM32H747_MCUCONF +#define STM32H757_MCUCONF +#define STM32H750_MCUCONF + +/* + * General settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_TARGET_CORE 1 + +/* + * Memory attributes settings. + */ +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#define STM32_NOCACHE_SRAM1_SRAM2 FALSE +#define STM32_NOCACHE_SRAM3 TRUE + +/* + * PWR system settings. + * Reading STM32 Reference Manual is required, settings in PWR_CR3 are + * very critical. + * Register constants are taken from the ST header. + */ +#define STM32_VOS STM32_VOS_SCALE1 +#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) +#define STM32_PWR_CR2 (PWR_CR2_BREN) +#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN) +#define STM32_PWR_CPUCR 0 + +/* + * Clock tree static settings. + * Reading STM32 Reference Manual is required. + */ +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_CSI_ENABLED TRUE +#define STM32_HSI48_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_HSIDIV STM32_HSIDIV_DIV1 + +/* + * PLLs static settings. + * Reading STM32 Reference Manual is required. + */ +#define STM32_PLLSRC STM32_PLLSRC_HSE_CK +#define STM32_PLLCFGR_MASK ~0 +#define STM32_PLL1_ENABLED TRUE +#define STM32_PLL1_P_ENABLED TRUE +#define STM32_PLL1_Q_ENABLED TRUE +#define STM32_PLL1_R_ENABLED TRUE +#define STM32_PLL1_DIVM_VALUE 2 +#define STM32_PLL1_DIVN_VALUE 38 +#define STM32_PLL1_FRACN_VALUE 0 +#define STM32_PLL1_DIVP_VALUE 2 +#define STM32_PLL1_DIVQ_VALUE 16 +#define STM32_PLL1_DIVR_VALUE 8 +#define STM32_PLL2_ENABLED TRUE +#define STM32_PLL2_P_ENABLED TRUE +#define STM32_PLL2_Q_ENABLED TRUE +#define STM32_PLL2_R_ENABLED TRUE +#define STM32_PLL2_DIVM_VALUE 2 +#define STM32_PLL2_DIVN_VALUE 38 +#define STM32_PLL2_FRACN_VALUE 0 +#define STM32_PLL2_DIVP_VALUE 40 +#define STM32_PLL2_DIVQ_VALUE 8 +#define STM32_PLL2_DIVR_VALUE 8 +#define STM32_PLL3_ENABLED TRUE +#define STM32_PLL3_P_ENABLED TRUE +#define STM32_PLL3_Q_ENABLED TRUE +#define STM32_PLL3_R_ENABLED TRUE +#define STM32_PLL3_DIVM_VALUE 2 +#define STM32_PLL3_DIVN_VALUE 38 +#define STM32_PLL3_FRACN_VALUE 0 +#define STM32_PLL3_DIVP_VALUE 8 +#define STM32_PLL3_DIVQ_VALUE 8 +#define STM32_PLL3_DIVR_VALUE 8 + +/* + * Core clocks dynamic settings (can be changed at runtime). + * Reading STM32 Reference Manual is required. + */ +#define STM32_SW STM32_SW_PLL1_P_CK +#define STM32_RTCSEL STM32_RTCSEL_LSE_CK +#define STM32_D1CPRE STM32_D1CPRE_DIV1 +#define STM32_D1HPRE STM32_D1HPRE_DIV2 +#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2 +#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2 +#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2 +#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2 + +/* + * Peripherals clocks static settings. + * Reading STM32 Reference Manual is required. + */ +#define STM32_MCO1SEL STM32_MCO1SEL_HSI_CK +#define STM32_MCO1PRE_VALUE 4 +#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK +#define STM32_MCO2PRE_VALUE 4 +#define STM32_TIMPRE_ENABLE TRUE +#define STM32_HRTIMSEL 0 +#define STM32_STOPKERWUCK 0 +#define STM32_STOPWUCK 0 +#define STM32_RTCPRE_VALUE 8 +#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK +#define STM32_QSPISEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_SWPSEL STM32_SWPSEL_PCLK1 +#define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK +#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 +#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK +#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2 +#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK +#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK +#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE_CK +#define STM32_USBSEL STM32_USBSEL_PLL1_Q_CK +#define STM32_I2C123SEL STM32_I2C123SEL_PCLK1 +#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK +#define STM32_USART16SEL STM32_USART16SEL_PCLK2 +#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1 +#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4 +#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK +#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK +#define STM32_ADCSEL STM32_ADCSEL_PLL2_P_CK +#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4 +#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK4 +#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4 + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 6 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_21_PRIORITY 6 + +#define STM32_IRQ_FDCAN1_PRIORITY 10 +#define STM32_IRQ_FDCAN2_PRIORITY 10 + +#define STM32_IRQ_MDMA_PRIORITY 9 + +#define STM32_IRQ_QUADSPI1_PRIORITY 10 + +#define STM32_IRQ_SDMMC1_PRIORITY 9 +#define STM32_IRQ_SDMMC2_PRIORITY 9 + +#define STM32_IRQ_TIM1_UP_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 +#define STM32_IRQ_TIM15_PRIORITY 7 +#define STM32_IRQ_TIM16_PRIORITY 7 +#define STM32_IRQ_TIM17_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 +#define STM32_IRQ_LPUART1_PRIORITY 12 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC12 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_ADC_ADC3_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_ADC_ADC12_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 +#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV4 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_FDCAN1 FALSE +#define STM32_CAN_USE_FDCAN2 FALSE + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM13 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_USE_TIM15 FALSE +#define STM32_GPT_USE_TIM16 FALSE +#define STM32_GPT_USE_TIM17 FALSE + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C4_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_I2C_I2C4_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM12 FALSE +#define STM32_ICU_USE_TIM13 FALSE +#define STM32_ICU_USE_TIM14 FALSE +#define STM32_ICU_USE_TIM15 FALSE +#define STM32_ICU_USE_TIM16 FALSE +#define STM32_ICU_USE_TIM17 FALSE + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM12 FALSE +#define STM32_PWM_USE_TIM13 FALSE +#define STM32_PWM_USE_TIM14 FALSE +#define STM32_PWM_USE_TIM15 FALSE +#define STM32_PWM_USE_TIM16 FALSE +#define STM32_PWM_USE_TIM17 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 TRUE +#define STM32_SDC_USE_SDMMC2 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC_PWRSAV TRUE + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USE_LPUART1 FALSE + +/* + * SIO driver system settings. + */ +#define STM32_SIO_USE_USART1 FALSE +#define STM32_SIO_USE_USART2 FALSE +#define STM32_SIO_USE_USART3 FALSE +#define STM32_SIO_USE_UART4 FALSE +#define STM32_SIO_USE_UART5 FALSE +#define STM32_SIO_USE_USART6 FALSE +#define STM32_SIO_USE_UART7 FALSE +#define STM32_SIO_USE_UART8 FALSE +#define STM32_SIO_USE_LPUART1 FALSE + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI6_RX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_SPI_SPI6_TX_BDMA_STREAM STM32_BDMA_STREAM_ID_ANY +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * TRNG driver system settings. + */ +#define STM32_TRNG_USE_RNG1 FALSE + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1 +#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY +#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1 +#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) osalSysHalt("MDMA failure") + +#endif /* MCUCONF_H */ diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/main.c b/demos/STM32/RT-STM32H750XB-DISCOVERY/main.c new file mode 100644 index 000000000..744cb4ffd --- /dev/null +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/main.c @@ -0,0 +1,79 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "rt_test_root.h" +#include "oslib_test_root.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palSetLine(LINE_LED_GREEN); + chThdSleepMilliseconds(50); + palSetLine(LINE_LED_RED); + chThdSleepMilliseconds(200); + palClearLine(LINE_LED_GREEN); + chThdSleepMilliseconds(50); + palClearLine(LINE_LED_RED); + chThdSleepMilliseconds(200); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD3, NULL); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO+1, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (1) { + if (palReadLine(LINE_BUTTON)) { + test_execute((BaseSequentialStream *)&SD3, &rt_test_suite); + test_execute((BaseSequentialStream *)&SD3, &oslib_test_suite); + } + chThdSleepMilliseconds(500); + } +} diff --git a/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.c b/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.c new file mode 100644 index 000000000..7173084e8 --- /dev/null +++ b/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB4(STM32_GPIO_EN_MASK); + rccEnableAHB4(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.h b/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.h new file mode 100644 index 000000000..8f36743fa --- /dev/null +++ b/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.h @@ -0,0 +1,1733 @@ +/* + ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32H750XB_DISCOVERY board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32H750XB_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32H750XB_DISCOVERY" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8740A_ID + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * MCU type as defined in the ST header. + */ +#define STM32H750xx + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_MII_RX_CLK 1U +#define GPIOA_MII_MDIO 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_MII_RX_DV 7U +#define GPIOA_PIN8 8U +#define GPIOA_VBUS_FS2 9U +#define GPIOA_USB_OTG_FS2_ID 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_T_JTDI 15U + +#define GPIOB_MII_RXD2 0U +#define GPIOB_MII_RXD3 1U +#define GPIOB_MII_TX_ER 2U +#define GPIOB_SWO 3U +#define GPIOB_PIN4 4U +#define GPIOB_FDCAN2_RX 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_SDIO1_D4 8U +#define GPIOB_SDIO1_D5 9U +#define GPIOB_VCP_TX 10U +#define GPIOB_VCP_RX 11U +#define GPIOB_LCD_RST 12U +#define GPIOB_FDCAN2_TX 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_MII_MDC 1U +#define GPIOC_MII_TXD2 2U +#define GPIOC_MII_TX_CLK 3U +#define GPIOC_MII_RXD0 4U +#define GPIOC_MII_RXD1 5U +#define GPIOC_SDIO1_D6 6U +#define GPIOC_SDIO1_D7 7U +#define GPIOC_SDIO1_D0 8U +#define GPIOC_SDIO1_D1 9U +#define GPIOC_SDIO1_D2 10U +#define GPIOC_SDIO1_D3 11U +#define GPIOC_SDIO1_CK 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_SDRAM_D2 0U +#define GPIOD_SDRAM_D3 1U +#define GPIOD_SDIO1_CMD 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_LCD_DISP 7U +#define GPIOD_SDRAM_D13 8U +#define GPIOD_SDRAM_D14 9U +#define GPIOD_SDRAM_D15 10U +#define GPIOD_QSPI_BK1_IO0 11U +#define GPIOD_I2C4_SCL 12U +#define GPIOD_I2C4_SDA 13U +#define GPIOD_SDRAM_D0 14U +#define GPIOD_SDRAM_D1 15U + +#define GPIOE_SDRAM_NBL0 0U +#define GPIOE_SDRAM_NBL1 1U +#define GPIOE_MII_TXD3 2U +#define GPIOE_PIN3 3U +#define GPIOE_SAI4_D2 4U +#define GPIOE_SAI4_CK2 5U +#define GPIOE_PIN6 6U +#define GPIOE_SDRAM_D4 7U +#define GPIOE_SDRAM_D5 8U +#define GPIOE_SDRAM_D6 9U +#define GPIOE_SDRAM_D7 10U +#define GPIOE_SDRAM_D8 11U +#define GPIOE_SDRAM_D9 12U +#define GPIOE_SDRAM_D10 13U +#define GPIOE_SDRAM_D11 14U +#define GPIOE_SDRAM_D12 15U + +#define GPIOF_SDRAM_A0 0U +#define GPIOF_SDRAM_A1 1U +#define GPIOF_SDRAM_A2 2U +#define GPIOF_SDRAM_A3 3U +#define GPIOF_SDRAM_A4 4U +#define GPIOF_SDRAM_A5 5U +#define GPIOF_QSPI_BK1_IO3 6U +#define GPIOF_QSPI_BK1_IO2 7U +#define GPIOF_PIN8 8U +#define GPIOF_QSPI_BK1_IO1 9U +#define GPIOF_QSPI_CLK 10U +#define GPIOF_SDRAM_SDNRAS 11U +#define GPIOF_SDRAM_A6 12U +#define GPIOF_SDRAM_A7 13U +#define GPIOF_SDRAM_A8 14U +#define GPIOF_SDRAM_A9 15U + +#define GPIOG_SDRAM_A10 0U +#define GPIOG_SDRAM_A11 1U +#define GPIOG_LCD_INT 2U +#define GPIOG_PIN3 3U +#define GPIOG_SDRAM_BA0 4U +#define GPIOG_SDRAM_BA1 5U +#define GPIOG_RCC_OSC_OUT 6U +#define GPIOG_PIN7 7U +#define GPIOG_SDRAM_SDCLK 8U +#define GPIOG_QSPI_BK2_IO2 9U +#define GPIOG_SAI2_SDB 10U +#define GPIOG_MII_TX_EN 11U +#define GPIOG_MII_TXD1 12U +#define GPIOG_MII_TXD0 13U +#define GPIOG_QSPI_BK2_IO3 14U +#define GPIOG_SDRAM_SDNCAS 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_PIN1 1U +#define GPIOH_QSPI_BK2_IO0 2U +#define GPIOH_QSPI_BK2_IO1 3U +#define GPIOH_PIN4 4U +#define GPIOH_SDRAM_SDNWE 5U +#define GPIOH_SDRAM_SDNE1 6U +#define GPIOH_SDRAM_SDCKE1 7U +#define GPIOH_PIN8 8U +#define GPIOH_LCD_R3 9U +#define GPIOH_PIN10 10U +#define GPIOH_OTG_FS2_OVER_CURRENT 11U +#define GPIOH_PIN12 12U +#define GPIOH_FDCAN1_TX 13U +#define GPIOH_FDCAN1_RX 14U +#define GPIOH_PIN15 15U + +#define GPIOI_LCD_G5 0U +#define GPIOI_LCD_G6 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_SAI2_MCLKA 4U +#define GPIOI_SAI2_SCKA 5U +#define GPIOI_SAI2_SDA 6U +#define GPIOI_SAI2_FSA 7U +#define GPIOI_PIN8 8U +#define GPIOI_LCD_VSYNC 9U +#define GPIOI_MII_RX_ER 10U +#define GPIOI_PIN11 11U +#define GPIOI_LCD_HSYNC 12U +#define GPIOI_LED_GREEN 13U +#define GPIOI_LCD_CLK 14U +#define GPIOI_LCD_R0 15U + +#define GPIOJ_LCD_R1 0U +#define GPIOJ_LCD_R2 1U +#define GPIOJ_LED_RED 2U +#define GPIOJ_LCD_R4 3U +#define GPIOJ_LCD_R5 4U +#define GPIOJ_LCD_R6 5U +#define GPIOJ_LCD_R7 6U +#define GPIOJ_LCD_G0 7U +#define GPIOJ_LCD_G1 8U +#define GPIOJ_LCD_G2 9U +#define GPIOJ_LCD_G3 10U +#define GPIOJ_LCD_G4 11U +#define GPIOJ_LCD_B0 12U +#define GPIOJ_LCD_B1 13U +#define GPIOJ_LCD_B2 14U +#define GPIOJ_LCD_B3 15U + +#define GPIOK_LCD_BL 0U +#define GPIOK_PIN1 1U +#define GPIOK_LCD_G7 2U +#define GPIOK_LCD_B4 3U +#define GPIOK_LCD_B5 4U +#define GPIOK_LCD_B6 5U +#define GPIOK_LCD_B7 6U +#define GPIOK_LCD_DE 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_MII_RX_CLK PAL_LINE(GPIOA, 1U) +#define LINE_MII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_MII_RX_DV PAL_LINE(GPIOA, 7U) +#define LINE_VBUS_FS2 PAL_LINE(GPIOA, 9U) +#define LINE_USB_OTG_FS2_ID PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_T_JTDI PAL_LINE(GPIOA, 15U) +#define LINE_MII_RXD2 PAL_LINE(GPIOB, 0U) +#define LINE_MII_RXD3 PAL_LINE(GPIOB, 1U) +#define LINE_MII_TX_ER PAL_LINE(GPIOB, 2U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_FDCAN2_RX PAL_LINE(GPIOB, 5U) +#define LINE_SDIO1_D4 PAL_LINE(GPIOB, 8U) +#define LINE_SDIO1_D5 PAL_LINE(GPIOB, 9U) +#define LINE_VCP_TX PAL_LINE(GPIOB, 10U) +#define LINE_VCP_RX PAL_LINE(GPIOB, 11U) +#define LINE_LCD_RST PAL_LINE(GPIOB, 12U) +#define LINE_FDCAN2_TX PAL_LINE(GPIOB, 13U) +#define LINE_MII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_MII_TXD2 PAL_LINE(GPIOC, 2U) +#define LINE_MII_TX_CLK PAL_LINE(GPIOC, 3U) +#define LINE_MII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_MII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_SDIO1_D6 PAL_LINE(GPIOC, 6U) +#define LINE_SDIO1_D7 PAL_LINE(GPIOC, 7U) +#define LINE_SDIO1_D0 PAL_LINE(GPIOC, 8U) +#define LINE_SDIO1_D1 PAL_LINE(GPIOC, 9U) +#define LINE_SDIO1_D2 PAL_LINE(GPIOC, 10U) +#define LINE_SDIO1_D3 PAL_LINE(GPIOC, 11U) +#define LINE_SDIO1_CK PAL_LINE(GPIOC, 12U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_SDRAM_D2 PAL_LINE(GPIOD, 0U) +#define LINE_SDRAM_D3 PAL_LINE(GPIOD, 1U) +#define LINE_SDIO1_CMD PAL_LINE(GPIOD, 2U) +#define LINE_LCD_DISP PAL_LINE(GPIOD, 7U) +#define LINE_SDRAM_D13 PAL_LINE(GPIOD, 8U) +#define LINE_SDRAM_D14 PAL_LINE(GPIOD, 9U) +#define LINE_SDRAM_D15 PAL_LINE(GPIOD, 10U) +#define LINE_QSPI_BK1_IO0 PAL_LINE(GPIOD, 11U) +#define LINE_I2C4_SCL PAL_LINE(GPIOD, 12U) +#define LINE_I2C4_SDA PAL_LINE(GPIOD, 13U) +#define LINE_SDRAM_D0 PAL_LINE(GPIOD, 14U) +#define LINE_SDRAM_D1 PAL_LINE(GPIOD, 15U) +#define LINE_SDRAM_NBL0 PAL_LINE(GPIOE, 0U) +#define LINE_SDRAM_NBL1 PAL_LINE(GPIOE, 1U) +#define LINE_MII_TXD3 PAL_LINE(GPIOE, 2U) +#define LINE_SAI4_D2 PAL_LINE(GPIOE, 4U) +#define LINE_SAI4_CK2 PAL_LINE(GPIOE, 5U) +#define LINE_SDRAM_D4 PAL_LINE(GPIOE, 7U) +#define LINE_SDRAM_D5 PAL_LINE(GPIOE, 8U) +#define LINE_SDRAM_D6 PAL_LINE(GPIOE, 9U) +#define LINE_SDRAM_D7 PAL_LINE(GPIOE, 10U) +#define LINE_SDRAM_D8 PAL_LINE(GPIOE, 11U) +#define LINE_SDRAM_D9 PAL_LINE(GPIOE, 12U) +#define LINE_SDRAM_D10 PAL_LINE(GPIOE, 13U) +#define LINE_SDRAM_D11 PAL_LINE(GPIOE, 14U) +#define LINE_SDRAM_D12 PAL_LINE(GPIOE, 15U) +#define LINE_SDRAM_A0 PAL_LINE(GPIOF, 0U) +#define LINE_SDRAM_A1 PAL_LINE(GPIOF, 1U) +#define LINE_SDRAM_A2 PAL_LINE(GPIOF, 2U) +#define LINE_SDRAM_A3 PAL_LINE(GPIOF, 3U) +#define LINE_SDRAM_A4 PAL_LINE(GPIOF, 4U) +#define LINE_SDRAM_A5 PAL_LINE(GPIOF, 5U) +#define LINE_QSPI_BK1_IO3 PAL_LINE(GPIOF, 6U) +#define LINE_QSPI_BK1_IO2 PAL_LINE(GPIOF, 7U) +#define LINE_QSPI_BK1_IO1 PAL_LINE(GPIOF, 9U) +#define LINE_QSPI_CLK PAL_LINE(GPIOF, 10U) +#define LINE_SDRAM_SDNRAS PAL_LINE(GPIOF, 11U) +#define LINE_SDRAM_A6 PAL_LINE(GPIOF, 12U) +#define LINE_SDRAM_A7 PAL_LINE(GPIOF, 13U) +#define LINE_SDRAM_A8 PAL_LINE(GPIOF, 14U) +#define LINE_SDRAM_A9 PAL_LINE(GPIOF, 15U) +#define LINE_SDRAM_A10 PAL_LINE(GPIOG, 0U) +#define LINE_SDRAM_A11 PAL_LINE(GPIOG, 1U) +#define LINE_LCD_INT PAL_LINE(GPIOG, 2U) +#define LINE_SDRAM_BA0 PAL_LINE(GPIOG, 4U) +#define LINE_SDRAM_BA1 PAL_LINE(GPIOG, 5U) +#define LINE_RCC_OSC_OUT PAL_LINE(GPIOG, 6U) +#define LINE_SDRAM_SDCLK PAL_LINE(GPIOG, 8U) +#define LINE_QSPI_BK2_IO2 PAL_LINE(GPIOG, 9U) +#define LINE_SAI2_SDB PAL_LINE(GPIOG, 10U) +#define LINE_MII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_MII_TXD1 PAL_LINE(GPIOG, 12U) +#define LINE_MII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_QSPI_BK2_IO3 PAL_LINE(GPIOG, 14U) +#define LINE_SDRAM_SDNCAS PAL_LINE(GPIOG, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_QSPI_BK2_IO0 PAL_LINE(GPIOH, 2U) +#define LINE_QSPI_BK2_IO1 PAL_LINE(GPIOH, 3U) +#define LINE_SDRAM_SDNWE PAL_LINE(GPIOH, 5U) +#define LINE_SDRAM_SDNE1 PAL_LINE(GPIOH, 6U) +#define LINE_SDRAM_SDCKE1 PAL_LINE(GPIOH, 7U) +#define LINE_LCD_R3 PAL_LINE(GPIOH, 9U) +#define LINE_OTG_FS2_OVER_CURRENT PAL_LINE(GPIOH, 11U) +#define LINE_FDCAN1_TX PAL_LINE(GPIOH, 13U) +#define LINE_FDCAN1_RX PAL_LINE(GPIOH, 14U) +#define LINE_LCD_G5 PAL_LINE(GPIOI, 0U) +#define LINE_LCD_G6 PAL_LINE(GPIOI, 1U) +#define LINE_SAI2_MCLKA PAL_LINE(GPIOI, 4U) +#define LINE_SAI2_SCKA PAL_LINE(GPIOI, 5U) +#define LINE_SAI2_SDA PAL_LINE(GPIOI, 6U) +#define LINE_SAI2_FSA PAL_LINE(GPIOI, 7U) +#define LINE_LCD_VSYNC PAL_LINE(GPIOI, 9U) +#define LINE_MII_RX_ER PAL_LINE(GPIOI, 10U) +#define LINE_LCD_HSYNC PAL_LINE(GPIOI, 12U) +#define LINE_LED_GREEN PAL_LINE(GPIOI, 13U) +#define LINE_LCD_CLK PAL_LINE(GPIOI, 14U) +#define LINE_LCD_R0 PAL_LINE(GPIOI, 15U) +#define LINE_LCD_R1 PAL_LINE(GPIOJ, 0U) +#define LINE_LCD_R2 PAL_LINE(GPIOJ, 1U) +#define LINE_LED_RED PAL_LINE(GPIOJ, 2U) +#define LINE_LCD_R4 PAL_LINE(GPIOJ, 3U) +#define LINE_LCD_R5 PAL_LINE(GPIOJ, 4U) +#define LINE_LCD_R6 PAL_LINE(GPIOJ, 5U) +#define LINE_LCD_R7 PAL_LINE(GPIOJ, 6U) +#define LINE_LCD_G0 PAL_LINE(GPIOJ, 7U) +#define LINE_LCD_G1 PAL_LINE(GPIOJ, 8U) +#define LINE_LCD_G2 PAL_LINE(GPIOJ, 9U) +#define LINE_LCD_G3 PAL_LINE(GPIOJ, 10U) +#define LINE_LCD_G4 PAL_LINE(GPIOJ, 11U) +#define LINE_LCD_B0 PAL_LINE(GPIOJ, 12U) +#define LINE_LCD_B1 PAL_LINE(GPIOJ, 13U) +#define LINE_LCD_B2 PAL_LINE(GPIOJ, 14U) +#define LINE_LCD_B3 PAL_LINE(GPIOJ, 15U) +#define LINE_LCD_BL PAL_LINE(GPIOK, 0U) +#define LINE_LCD_G7 PAL_LINE(GPIOK, 2U) +#define LINE_LCD_B4 PAL_LINE(GPIOK, 3U) +#define LINE_LCD_B5 PAL_LINE(GPIOK, 4U) +#define LINE_LCD_B6 PAL_LINE(GPIOK, 5U) +#define LINE_LCD_B7 PAL_LINE(GPIOK, 6U) +#define LINE_LCD_DE PAL_LINE(GPIOK, 7U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - PIN0 (input floating). + * PA1 - MII_RX_CLK (alternate 11). + * PA2 - MII_MDIO (alternate 11). + * PA3 - PIN3 (input floating). + * PA4 - PIN4 (input floating). + * PA5 - PIN5 (input floating). + * PA6 - PIN6 (input floating). + * PA7 - MII_RX_DV (alternate 11). + * PA8 - PIN8 (input floating). + * PA9 - VBUS_FS2 (analog). + * PA10 - USB_OTG_FS2_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - T_JTDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_ALTERNATE(GPIOA_MII_RX_CLK) | \ + PIN_MODE_ALTERNATE(GPIOA_MII_MDIO) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOA_MII_RX_DV) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_ANALOG(GPIOA_VBUS_FS2) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_OTG_FS2_ID) |\ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_T_JTDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MII_RX_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_MII_RX_DV) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_OTG_FS2_ID) |\ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_T_JTDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \ + PIN_OSPEED_HIGH(GPIOA_MII_RX_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_MII_MDIO) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \ + PIN_OSPEED_HIGH(GPIOA_MII_RX_DV) | \ + PIN_OSPEED_HIGH(GPIOA_PIN8) | \ + PIN_OSPEED_HIGH(GPIOA_VBUS_FS2) | \ + PIN_OSPEED_HIGH(GPIOA_USB_OTG_FS2_ID) |\ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_T_JTDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOA_MII_RX_CLK) | \ + PIN_PUPDR_PULLUP(GPIOA_MII_MDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOA_MII_RX_DV) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS2) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_OTG_FS2_ID) |\ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_T_JTDI)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ + PIN_ODR_HIGH(GPIOA_MII_RX_CLK) | \ + PIN_ODR_HIGH(GPIOA_MII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_MII_RX_DV) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS2) | \ + PIN_ODR_HIGH(GPIOA_USB_OTG_FS2_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_T_JTDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOA_MII_RX_CLK, 11U) | \ + PIN_AFIO_AF(GPIOA_MII_MDIO, 11U) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOA_MII_RX_DV, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS2, 0U) | \ + PIN_AFIO_AF(GPIOA_USB_OTG_FS2_ID, 10U) |\ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_T_JTDI, 0U)) + +/* + * GPIOB setup: + * + * PB0 - MII_RXD2 (alternate 11). + * PB1 - MII_RXD3 (alternate 11). + * PB2 - MII_TX_ER (analog). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input floating). + * PB5 - FDCAN2_RX (input floating). + * PB6 - PIN6 (input floating). + * PB7 - PIN7 (input floating). + * PB8 - SDIO1_D4 (alternate 12). + * PB9 - SDIO1_D5 (alternate 12). + * PB10 - VCP_TX (alternate 7). + * PB11 - VCP_RX (alternate 7). + * PB12 - LCD_RST (output pushpull maximum). + * PB13 - FDCAN2_TX (alternate 9). + * PB14 - PIN14 (input floating). + * PB15 - PIN15 (input floating). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_MII_RXD2) | \ + PIN_MODE_ALTERNATE(GPIOB_MII_RXD3) | \ + PIN_MODE_ANALOG(GPIOB_MII_TX_ER) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_FDCAN2_RX) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_SDIO1_D4) | \ + PIN_MODE_ALTERNATE(GPIOB_SDIO1_D5) | \ + PIN_MODE_ALTERNATE(GPIOB_VCP_TX) | \ + PIN_MODE_ALTERNATE(GPIOB_VCP_RX) | \ + PIN_MODE_OUTPUT(GPIOB_LCD_RST) | \ + PIN_MODE_ALTERNATE(GPIOB_FDCAN2_TX) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_MII_RXD2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_MII_RXD3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_MII_TX_ER) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FDCAN2_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SDIO1_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SDIO1_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_VCP_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_VCP_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LCD_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_FDCAN2_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_MII_RXD2) | \ + PIN_OSPEED_HIGH(GPIOB_MII_RXD3) | \ + PIN_OSPEED_HIGH(GPIOB_MII_TX_ER) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_FDCAN2_RX) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOB_SDIO1_D4) | \ + PIN_OSPEED_VERYLOW(GPIOB_SDIO1_D5) | \ + PIN_OSPEED_HIGH(GPIOB_VCP_TX) | \ + PIN_OSPEED_HIGH(GPIOB_VCP_RX) | \ + PIN_OSPEED_HIGH(GPIOB_LCD_RST) | \ + PIN_OSPEED_HIGH(GPIOB_FDCAN2_TX) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_MII_RXD2) | \ + PIN_PUPDR_FLOATING(GPIOB_MII_RXD3) | \ + PIN_PUPDR_FLOATING(GPIOB_MII_TX_ER) | \ + PIN_PUPDR_PULLUP(GPIOB_SWO) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOB_FDCAN2_RX) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_SDIO1_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_SDIO1_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_VCP_TX) | \ + PIN_PUPDR_FLOATING(GPIOB_VCP_RX) | \ + PIN_PUPDR_PULLDOWN(GPIOB_LCD_RST) | \ + PIN_PUPDR_FLOATING(GPIOB_FDCAN2_TX) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_MII_RXD2) | \ + PIN_ODR_HIGH(GPIOB_MII_RXD3) | \ + PIN_ODR_HIGH(GPIOB_MII_TX_ER) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_HIGH(GPIOB_FDCAN2_RX) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ + PIN_ODR_LOW(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_SDIO1_D4) | \ + PIN_ODR_HIGH(GPIOB_SDIO1_D5) | \ + PIN_ODR_HIGH(GPIOB_VCP_TX) | \ + PIN_ODR_HIGH(GPIOB_VCP_RX) | \ + PIN_ODR_LOW(GPIOB_LCD_RST) | \ + PIN_ODR_HIGH(GPIOB_FDCAN2_TX) | \ + PIN_ODR_LOW(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_MII_RXD2, 11U) | \ + PIN_AFIO_AF(GPIOB_MII_RXD3, 11U) | \ + PIN_AFIO_AF(GPIOB_MII_TX_ER, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_FDCAN2_RX, 9U) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_SDIO1_D4, 12U) | \ + PIN_AFIO_AF(GPIOB_SDIO1_D5, 12U) | \ + PIN_AFIO_AF(GPIOB_VCP_TX, 7U) | \ + PIN_AFIO_AF(GPIOB_VCP_RX, 7U) | \ + PIN_AFIO_AF(GPIOB_LCD_RST, 0U) | \ + PIN_AFIO_AF(GPIOB_FDCAN2_TX, 9U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input floating). + * PC1 - MII_MDC (alternate 11). + * PC2 - MII_TXD2 (alternate 11). + * PC3 - MII_TX_CLK (alternate 11). + * PC4 - MII_RXD0 (alternate 11). + * PC5 - MII_RXD1 (alternate 11). + * PC6 - SDIO1_D6 (alternate 12). + * PC7 - SDIO1_D7 (alternate 12). + * PC8 - SDIO1_D0 (alternate 12). + * PC9 - SDIO1_D1 (alternate 12). + * PC10 - SDIO1_D2 (alternate 12). + * PC11 - SDIO1_D3 (alternate 12). + * PC12 - SDIO1_CK (alternate 12). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_ALTERNATE(GPIOC_MII_MDC) | \ + PIN_MODE_ALTERNATE(GPIOC_MII_TXD2) | \ + PIN_MODE_ALTERNATE(GPIOC_MII_TX_CLK) | \ + PIN_MODE_ALTERNATE(GPIOC_MII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_MII_RXD1) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO1_D6) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO1_D7) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO1_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO1_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO1_D2) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO1_D3) | \ + PIN_MODE_ALTERNATE(GPIOC_SDIO1_CK) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MII_TXD2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MII_TX_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_MII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIO1_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIO1_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIO1_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIO1_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIO1_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIO1_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SDIO1_CK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \ + PIN_OSPEED_HIGH(GPIOC_MII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_MII_TXD2) | \ + PIN_OSPEED_HIGH(GPIOC_MII_TX_CLK) | \ + PIN_OSPEED_HIGH(GPIOC_MII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_MII_RXD1) | \ + PIN_OSPEED_HIGH(GPIOC_SDIO1_D6) | \ + PIN_OSPEED_HIGH(GPIOC_SDIO1_D7) | \ + PIN_OSPEED_HIGH(GPIOC_SDIO1_D0) | \ + PIN_OSPEED_HIGH(GPIOC_SDIO1_D1) | \ + PIN_OSPEED_HIGH(GPIOC_SDIO1_D2) | \ + PIN_OSPEED_HIGH(GPIOC_SDIO1_D3) | \ + PIN_OSPEED_HIGH(GPIOC_SDIO1_CK) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOC_MII_MDC) | \ + PIN_PUPDR_FLOATING(GPIOC_MII_TXD2) | \ + PIN_PUPDR_FLOATING(GPIOC_MII_TX_CLK) | \ + PIN_PUPDR_FLOATING(GPIOC_MII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_MII_RXD1) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIO1_D6) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIO1_D7) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIO1_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIO1_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIO1_D2) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIO1_D3) | \ + PIN_PUPDR_FLOATING(GPIOC_SDIO1_CK) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_MII_MDC) | \ + PIN_ODR_HIGH(GPIOC_MII_TXD2) | \ + PIN_ODR_HIGH(GPIOC_MII_TX_CLK) | \ + PIN_ODR_HIGH(GPIOC_MII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_MII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_SDIO1_D6) | \ + PIN_ODR_HIGH(GPIOC_SDIO1_D7) | \ + PIN_ODR_HIGH(GPIOC_SDIO1_D0) | \ + PIN_ODR_HIGH(GPIOC_SDIO1_D1) | \ + PIN_ODR_HIGH(GPIOC_SDIO1_D2) | \ + PIN_ODR_HIGH(GPIOC_SDIO1_D3) | \ + PIN_ODR_HIGH(GPIOC_SDIO1_CK) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOC_MII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_MII_TXD2, 11U) | \ + PIN_AFIO_AF(GPIOC_MII_TX_CLK, 11U) | \ + PIN_AFIO_AF(GPIOC_MII_RXD0, 11U) | \ + PIN_AFIO_AF(GPIOC_MII_RXD1, 11U) | \ + PIN_AFIO_AF(GPIOC_SDIO1_D6, 12U) | \ + PIN_AFIO_AF(GPIOC_SDIO1_D7, 12U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SDIO1_D0, 12U) | \ + PIN_AFIO_AF(GPIOC_SDIO1_D1, 12U) | \ + PIN_AFIO_AF(GPIOC_SDIO1_D2, 12U) | \ + PIN_AFIO_AF(GPIOC_SDIO1_D3, 12U) | \ + PIN_AFIO_AF(GPIOC_SDIO1_CK, 12U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - SDRAM_D2 (alternate 12). + * PD1 - SDRAM_D3 (alternate 12). + * PD2 - SDIO1_CMD (alternate 12). + * PD3 - PIN3 (input floating). + * PD4 - PIN4 (input floating). + * PD5 - PIN5 (input floating). + * PD6 - PIN6 (input floating). + * PD7 - LCD_DISP (output pushpull maximum). + * PD8 - SDRAM_D13 (alternate 12). + * PD9 - SDRAM_D14 (alternate 12). + * PD10 - SDRAM_D15 (alternate 12). + * PD11 - QSPI_BK1_IO0 (alternate 9). + * PD12 - I2C4_SCL (alternate 4). + * PD13 - I2C4_SDA (alternate 4). + * PD14 - SDRAM_D0 (alternate 12). + * PD15 - SDRAM_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_SDRAM_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_SDRAM_D3) | \ + PIN_MODE_ALTERNATE(GPIOD_SDIO1_CMD) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_OUTPUT(GPIOD_LCD_DISP) | \ + PIN_MODE_ALTERNATE(GPIOD_SDRAM_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_SDRAM_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_SDRAM_D15) | \ + PIN_MODE_ALTERNATE(GPIOD_QSPI_BK1_IO0) |\ + PIN_MODE_ALTERNATE(GPIOD_I2C4_SCL) | \ + PIN_MODE_ALTERNATE(GPIOD_I2C4_SDA) | \ + PIN_MODE_ALTERNATE(GPIOD_SDRAM_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_SDRAM_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_SDRAM_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SDRAM_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SDIO1_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LCD_DISP) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SDRAM_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SDRAM_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SDRAM_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_QSPI_BK1_IO0) |\ + PIN_OTYPE_PUSHPULL(GPIOD_I2C4_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOD_I2C4_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SDRAM_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SDRAM_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_SDRAM_D2) | \ + PIN_OSPEED_HIGH(GPIOD_SDRAM_D3) | \ + PIN_OSPEED_HIGH(GPIOD_SDIO1_CMD) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_LCD_DISP) | \ + PIN_OSPEED_HIGH(GPIOD_SDRAM_D13) | \ + PIN_OSPEED_HIGH(GPIOD_SDRAM_D14) | \ + PIN_OSPEED_HIGH(GPIOD_SDRAM_D15) | \ + PIN_OSPEED_HIGH(GPIOD_QSPI_BK1_IO0) | \ + PIN_OSPEED_HIGH(GPIOD_I2C4_SCL) | \ + PIN_OSPEED_HIGH(GPIOD_I2C4_SDA) | \ + PIN_OSPEED_HIGH(GPIOD_SDRAM_D0) | \ + PIN_OSPEED_HIGH(GPIOD_SDRAM_D1)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_SDRAM_D2) | \ + PIN_PUPDR_FLOATING(GPIOD_SDRAM_D3) | \ + PIN_PUPDR_FLOATING(GPIOD_SDIO1_CMD) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_LCD_DISP) | \ + PIN_PUPDR_FLOATING(GPIOD_SDRAM_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_SDRAM_D14) | \ + PIN_PUPDR_FLOATING(GPIOD_SDRAM_D15) | \ + PIN_PUPDR_FLOATING(GPIOD_QSPI_BK1_IO0) |\ + PIN_PUPDR_FLOATING(GPIOD_I2C4_SCL) | \ + PIN_PUPDR_FLOATING(GPIOD_I2C4_SDA) | \ + PIN_PUPDR_FLOATING(GPIOD_SDRAM_D0) | \ + PIN_PUPDR_FLOATING(GPIOD_SDRAM_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_SDRAM_D2) | \ + PIN_ODR_HIGH(GPIOD_SDRAM_D3) | \ + PIN_ODR_HIGH(GPIOD_SDIO1_CMD) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_LCD_DISP) | \ + PIN_ODR_HIGH(GPIOD_SDRAM_D13) | \ + PIN_ODR_HIGH(GPIOD_SDRAM_D14) | \ + PIN_ODR_HIGH(GPIOD_SDRAM_D15) | \ + PIN_ODR_HIGH(GPIOD_QSPI_BK1_IO0) | \ + PIN_ODR_HIGH(GPIOD_I2C4_SCL) | \ + PIN_ODR_HIGH(GPIOD_I2C4_SDA) | \ + PIN_ODR_HIGH(GPIOD_SDRAM_D0) | \ + PIN_ODR_HIGH(GPIOD_SDRAM_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_SDRAM_D2, 12U) | \ + PIN_AFIO_AF(GPIOD_SDRAM_D3, 12U) | \ + PIN_AFIO_AF(GPIOD_SDIO1_CMD, 12U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_LCD_DISP, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_SDRAM_D13, 12U) | \ + PIN_AFIO_AF(GPIOD_SDRAM_D14, 12U) | \ + PIN_AFIO_AF(GPIOD_SDRAM_D15, 12U) | \ + PIN_AFIO_AF(GPIOD_QSPI_BK1_IO0, 9U) | \ + PIN_AFIO_AF(GPIOD_I2C4_SCL, 4U) | \ + PIN_AFIO_AF(GPIOD_I2C4_SDA, 4U) | \ + PIN_AFIO_AF(GPIOD_SDRAM_D0, 12U) | \ + PIN_AFIO_AF(GPIOD_SDRAM_D1, 12U)) + +/* + * GPIOE setup: + * + * PE0 - SDRAM_NBL0 (alternate 12). + * PE1 - SDRAM_NBL1 (alternate 12). + * PE2 - MII_TXD3 (alternate 11). + * PE3 - PIN3 (input floating). + * PE4 - SAI4_D2 (alternate 10). + * PE5 - SAI4_CK2 (alternate 10). + * PE6 - PIN6 (input floating). + * PE7 - SDRAM_D4 (alternate 12). + * PE8 - SDRAM_D5 (alternate 12). + * PE9 - SDRAM_D6 (alternate 12). + * PE10 - SDRAM_D7 (alternate 12). + * PE11 - SDRAM_D8 (alternate 12). + * PE12 - SDRAM_D9 (alternate 12). + * PE13 - SDRAM_D10 (alternate 12). + * PE14 - SDRAM_D11 (alternate 12). + * PE15 - SDRAM_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_SDRAM_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_NBL1) | \ + PIN_MODE_ALTERNATE(GPIOE_MII_TXD3) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI4_D2) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI4_CK2) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D11) | \ + PIN_MODE_ALTERNATE(GPIOE_SDRAM_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_MII_TXD3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI4_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI4_CK2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SDRAM_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_SDRAM_NBL0) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_NBL1) | \ + PIN_OSPEED_HIGH(GPIOE_MII_TXD3) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_SAI4_D2) | \ + PIN_OSPEED_HIGH(GPIOE_SAI4_CK2) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D4) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D5) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D6) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D7) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D8) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D9) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D10) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D11) | \ + PIN_OSPEED_HIGH(GPIOE_SDRAM_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_SDRAM_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_NBL1) | \ + PIN_PUPDR_FLOATING(GPIOE_MII_TXD3) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI4_D2) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI4_CK2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D4) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D5) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D6) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D7) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D11) | \ + PIN_PUPDR_FLOATING(GPIOE_SDRAM_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_SDRAM_NBL0) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_NBL1) | \ + PIN_ODR_HIGH(GPIOE_MII_TXD3) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_SAI4_D2) | \ + PIN_ODR_HIGH(GPIOE_SAI4_CK2) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D4) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D5) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D6) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D7) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D8) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D9) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D10) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D11) | \ + PIN_ODR_HIGH(GPIOE_SDRAM_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_SDRAM_NBL0, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_NBL1, 12U) | \ + PIN_AFIO_AF(GPIOE_MII_TXD3, 11U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_SAI4_D2, 10U) | \ + PIN_AFIO_AF(GPIOE_SAI4_CK2, 10U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D4, 12U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_SDRAM_D5, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D6, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D7, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D8, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D9, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D10, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D11, 12U) | \ + PIN_AFIO_AF(GPIOE_SDRAM_D12, 12U)) + +/* + * GPIOF setup: + * + * PF0 - SDRAM_A0 (alternate 12). + * PF1 - SDRAM_A1 (alternate 12). + * PF2 - SDRAM_A2 (alternate 12). + * PF3 - SDRAM_A3 (alternate 12). + * PF4 - SDRAM_A4 (alternate 12). + * PF5 - SDRAM_A5 (alternate 12). + * PF6 - QSPI_BK1_IO3 (alternate 9). + * PF7 - QSPI_BK1_IO2 (alternate 9). + * PF8 - PIN8 (input floating). + * PF9 - QSPI_BK1_IO1 (alternate 10). + * PF10 - QSPI_CLK (alternate 9). + * PF11 - SDRAM_SDNRAS (alternate 12). + * PF12 - SDRAM_A6 (alternate 12). + * PF13 - SDRAM_A7 (alternate 12). + * PF14 - SDRAM_A8 (alternate 12). + * PF15 - SDRAM_A9 (alternate 12). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_SDRAM_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A5) | \ + PIN_MODE_ALTERNATE(GPIOF_QSPI_BK1_IO3) |\ + PIN_MODE_ALTERNATE(GPIOF_QSPI_BK1_IO2) |\ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOF_QSPI_BK1_IO1) |\ + PIN_MODE_ALTERNATE(GPIOF_QSPI_CLK) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_SDNRAS) |\ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_SDRAM_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_BK1_IO3) |\ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_BK1_IO2) |\ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_BK1_IO1) |\ + PIN_OTYPE_PUSHPULL(GPIOF_QSPI_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_SDNRAS) |\ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SDRAM_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_SDRAM_A0) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A1) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A2) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A3) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A4) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A5) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_BK1_IO3) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_BK1_IO2) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_BK1_IO1) | \ + PIN_OSPEED_HIGH(GPIOF_QSPI_CLK) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_SDNRAS) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A6) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A7) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A8) | \ + PIN_OSPEED_HIGH(GPIOF_SDRAM_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_SDRAM_A0) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A1) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A2) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A4) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A5) | \ + PIN_PUPDR_FLOATING(GPIOF_QSPI_BK1_IO3) |\ + PIN_PUPDR_FLOATING(GPIOF_QSPI_BK1_IO2) |\ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_QSPI_BK1_IO1) |\ + PIN_PUPDR_FLOATING(GPIOF_QSPI_CLK) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_SDNRAS) |\ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A6) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A7) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A8) | \ + PIN_PUPDR_FLOATING(GPIOF_SDRAM_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_SDRAM_A0) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A1) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A2) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A3) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A4) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A5) | \ + PIN_ODR_HIGH(GPIOF_QSPI_BK1_IO3) | \ + PIN_ODR_HIGH(GPIOF_QSPI_BK1_IO2) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_QSPI_BK1_IO1) | \ + PIN_ODR_HIGH(GPIOF_QSPI_CLK) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A6) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A7) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A8) | \ + PIN_ODR_HIGH(GPIOF_SDRAM_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_SDRAM_A0, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A1, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A2, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A3, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A4, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A5, 12U) | \ + PIN_AFIO_AF(GPIOF_QSPI_BK1_IO3, 9U) | \ + PIN_AFIO_AF(GPIOF_QSPI_BK1_IO2, 9U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_QSPI_BK1_IO1, 10U) | \ + PIN_AFIO_AF(GPIOF_QSPI_CLK, 9U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_SDNRAS, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A6, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A7, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A8, 12U) | \ + PIN_AFIO_AF(GPIOF_SDRAM_A9, 12U)) + +/* + * GPIOG setup: + * + * PG0 - SDRAM_A10 (alternate 12). + * PG1 - SDRAM_A11 (alternate 12). + * PG2 - LCD_INT (input floating). + * PG3 - PIN3 (input floating). + * PG4 - SDRAM_BA0 (alternate 12). + * PG5 - SDRAM_BA1 (alternate 12). + * PG6 - RCC_OSC_OUT (output pushpull maximum). + * PG7 - PIN7 (input floating). + * PG8 - SDRAM_SDCLK (alternate 12). + * PG9 - QSPI_BK2_IO2 (alternate 9). + * PG10 - SAI2_SDB (alternate 10). + * PG11 - MII_TX_EN (alternate 11). + * PG12 - MII_TXD1 (alternate 11). + * PG13 - MII_TXD0 (alternate 11). + * PG14 - QSPI_BK2_IO3 (alternate 9). + * PG15 - SDRAM_SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_SDRAM_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_SDRAM_A11) | \ + PIN_MODE_INPUT(GPIOG_LCD_INT) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOG_SDRAM_BA0) | \ + PIN_MODE_ALTERNATE(GPIOG_SDRAM_BA1) | \ + PIN_MODE_OUTPUT(GPIOG_RCC_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOG_SDRAM_SDCLK) |\ + PIN_MODE_ALTERNATE(GPIOG_QSPI_BK2_IO2) |\ + PIN_MODE_ALTERNATE(GPIOG_SAI2_SDB) | \ + PIN_MODE_ALTERNATE(GPIOG_MII_TX_EN) | \ + PIN_MODE_ALTERNATE(GPIOG_MII_TXD1) | \ + PIN_MODE_ALTERNATE(GPIOG_MII_TXD0) | \ + PIN_MODE_ALTERNATE(GPIOG_QSPI_BK2_IO3) |\ + PIN_MODE_ALTERNATE(GPIOG_SDRAM_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_SDRAM_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SDRAM_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_LCD_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SDRAM_BA0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SDRAM_BA1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RCC_OSC_OUT) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SDRAM_SDCLK) |\ + PIN_OTYPE_PUSHPULL(GPIOG_QSPI_BK2_IO2) |\ + PIN_OTYPE_PUSHPULL(GPIOG_SAI2_SDB) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MII_TXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_MII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_QSPI_BK2_IO3) |\ + PIN_OTYPE_PUSHPULL(GPIOG_SDRAM_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_SDRAM_A10) | \ + PIN_OSPEED_HIGH(GPIOG_SDRAM_A11) | \ + PIN_OSPEED_HIGH(GPIOG_LCD_INT) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_SDRAM_BA0) | \ + PIN_OSPEED_HIGH(GPIOG_SDRAM_BA1) | \ + PIN_OSPEED_HIGH(GPIOG_RCC_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_SDRAM_SDCLK) | \ + PIN_OSPEED_HIGH(GPIOG_QSPI_BK2_IO2) | \ + PIN_OSPEED_HIGH(GPIOG_SAI2_SDB) | \ + PIN_OSPEED_HIGH(GPIOG_MII_TX_EN) | \ + PIN_OSPEED_HIGH(GPIOG_MII_TXD1) | \ + PIN_OSPEED_HIGH(GPIOG_MII_TXD0) | \ + PIN_OSPEED_HIGH(GPIOG_QSPI_BK2_IO3) | \ + PIN_OSPEED_HIGH(GPIOG_SDRAM_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_SDRAM_A10) | \ + PIN_PUPDR_FLOATING(GPIOG_SDRAM_A11) | \ + PIN_PUPDR_FLOATING(GPIOG_LCD_INT) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_SDRAM_BA0) | \ + PIN_PUPDR_FLOATING(GPIOG_SDRAM_BA1) | \ + PIN_PUPDR_FLOATING(GPIOG_RCC_OSC_OUT) |\ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_SDRAM_SDCLK) |\ + PIN_PUPDR_FLOATING(GPIOG_QSPI_BK2_IO2) |\ + PIN_PUPDR_FLOATING(GPIOG_SAI2_SDB) | \ + PIN_PUPDR_FLOATING(GPIOG_MII_TX_EN) | \ + PIN_PUPDR_FLOATING(GPIOG_MII_TXD1) | \ + PIN_PUPDR_FLOATING(GPIOG_MII_TXD0) | \ + PIN_PUPDR_FLOATING(GPIOG_QSPI_BK2_IO3) |\ + PIN_PUPDR_FLOATING(GPIOG_SDRAM_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_SDRAM_A10) | \ + PIN_ODR_HIGH(GPIOG_SDRAM_A11) | \ + PIN_ODR_HIGH(GPIOG_LCD_INT) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_SDRAM_BA0) | \ + PIN_ODR_HIGH(GPIOG_SDRAM_BA1) | \ + PIN_ODR_LOW(GPIOG_RCC_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_SDRAM_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_QSPI_BK2_IO2) | \ + PIN_ODR_HIGH(GPIOG_SAI2_SDB) | \ + PIN_ODR_HIGH(GPIOG_MII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_MII_TXD1) | \ + PIN_ODR_HIGH(GPIOG_MII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_QSPI_BK2_IO3) | \ + PIN_ODR_HIGH(GPIOG_SDRAM_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_SDRAM_A10, 12U) | \ + PIN_AFIO_AF(GPIOG_SDRAM_A11, 12U) | \ + PIN_AFIO_AF(GPIOG_LCD_INT, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_SDRAM_BA0, 12U) | \ + PIN_AFIO_AF(GPIOG_SDRAM_BA1, 12U) | \ + PIN_AFIO_AF(GPIOG_RCC_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_SDRAM_SDCLK, 12U) | \ + PIN_AFIO_AF(GPIOG_QSPI_BK2_IO2, 9U) | \ + PIN_AFIO_AF(GPIOG_SAI2_SDB, 10U) | \ + PIN_AFIO_AF(GPIOG_MII_TX_EN, 11U) | \ + PIN_AFIO_AF(GPIOG_MII_TXD1, 11U) | \ + PIN_AFIO_AF(GPIOG_MII_TXD0, 11U) | \ + PIN_AFIO_AF(GPIOG_QSPI_BK2_IO3, 9U) | \ + PIN_AFIO_AF(GPIOG_SDRAM_SDNCAS, 12U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - PIN1 (input floating). + * PH2 - QSPI_BK2_IO0 (alternate 9). + * PH3 - QSPI_BK2_IO1 (alternate 9). + * PH4 - PIN4 (input floating). + * PH5 - SDRAM_SDNWE (alternate 12). + * PH6 - SDRAM_SDNE1 (alternate 12). + * PH7 - SDRAM_SDCKE1 (alternate 12). + * PH8 - PIN8 (input floating). + * PH9 - LCD_R3 (alternate 14). + * PH10 - PIN10 (input floating). + * PH11 - OTG_FS2_OVER_CURRENT (input floating). + * PH12 - PIN12 (input floating). + * PH13 - FDCAN1_TX (alternate 9). + * PH14 - FDCAN1_RX (alternate 9). + * PH15 - PIN15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_PIN1) | \ + PIN_MODE_ALTERNATE(GPIOH_QSPI_BK2_IO0) |\ + PIN_MODE_ALTERNATE(GPIOH_QSPI_BK2_IO1) |\ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_ALTERNATE(GPIOH_SDRAM_SDNWE) |\ + PIN_MODE_ALTERNATE(GPIOH_SDRAM_SDNE1) |\ + PIN_MODE_ALTERNATE(GPIOH_SDRAM_SDCKE1) |\ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOH_LCD_R3) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_OTG_FS2_OVER_CURRENT) |\ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOH_FDCAN1_TX) | \ + PIN_MODE_ALTERNATE(GPIOH_FDCAN1_RX) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOH_QSPI_BK2_IO0) |\ + PIN_OTYPE_PUSHPULL(GPIOH_QSPI_BK2_IO1) |\ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_SDRAM_SDNWE) |\ + PIN_OTYPE_PUSHPULL(GPIOH_SDRAM_SDNE1) |\ + PIN_OTYPE_PUSHPULL(GPIOH_SDRAM_SDCKE1) |\ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_LCD_R3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OTG_FS2_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FDCAN1_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FDCAN1_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_PIN1) | \ + PIN_OSPEED_HIGH(GPIOH_QSPI_BK2_IO0) | \ + PIN_OSPEED_HIGH(GPIOH_QSPI_BK2_IO1) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_SDRAM_SDNWE) | \ + PIN_OSPEED_HIGH(GPIOH_SDRAM_SDNE1) | \ + PIN_OSPEED_HIGH(GPIOH_SDRAM_SDCKE1) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_LCD_R3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_OTG_FS2_OVER_CURRENT) |\ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_FDCAN1_TX) | \ + PIN_OSPEED_HIGH(GPIOH_FDCAN1_RX) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOH_QSPI_BK2_IO0) |\ + PIN_PUPDR_FLOATING(GPIOH_QSPI_BK2_IO1) |\ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_SDRAM_SDNWE) |\ + PIN_PUPDR_FLOATING(GPIOH_SDRAM_SDNE1) |\ + PIN_PUPDR_FLOATING(GPIOH_SDRAM_SDCKE1) |\ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_LCD_R3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_OTG_FS2_OVER_CURRENT) |\ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_FDCAN1_TX) | \ + PIN_PUPDR_FLOATING(GPIOH_FDCAN1_RX) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_PIN1) | \ + PIN_ODR_HIGH(GPIOH_QSPI_BK2_IO0) | \ + PIN_ODR_HIGH(GPIOH_QSPI_BK2_IO1) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_SDRAM_SDNWE) | \ + PIN_ODR_HIGH(GPIOH_SDRAM_SDNE1) | \ + PIN_ODR_HIGH(GPIOH_SDRAM_SDCKE1) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_LCD_R3) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_OTG_FS2_OVER_CURRENT) |\ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_FDCAN1_TX) | \ + PIN_ODR_HIGH(GPIOH_FDCAN1_RX) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOH_QSPI_BK2_IO0, 9U) | \ + PIN_AFIO_AF(GPIOH_QSPI_BK2_IO1, 9U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_SDRAM_SDNWE, 12U) | \ + PIN_AFIO_AF(GPIOH_SDRAM_SDNE1, 12U) | \ + PIN_AFIO_AF(GPIOH_SDRAM_SDCKE1, 12U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_LCD_R3, 14U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_OTG_FS2_OVER_CURRENT, 0U) |\ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_FDCAN1_TX, 9U) | \ + PIN_AFIO_AF(GPIOH_FDCAN1_RX, 9U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - LCD_G5 (alternate 14). + * PI1 - LCD_G6 (alternate 14). + * PI2 - PIN2 (input floating). + * PI3 - PIN3 (input floating). + * PI4 - SAI2_MCLKA (alternate 10). + * PI5 - SAI2_SCKA (alternate 10). + * PI6 - SAI2_SDA (alternate 10). + * PI7 - SAI2_FSA (alternate 10). + * PI8 - PIN8 (input floating). + * PI9 - LCD_VSYNC (alternate 14). + * PI10 - MII_RX_ER (alternate 11). + * PI11 - PIN11 (input floating). + * PI12 - LCD_HSYNC (alternate 14). + * PI13 - LED_GREEN (output pushpull maximum). + * PI14 - LCD_CLK (alternate 14). + * PI15 - LCD_R0 (alternate 14). + */ +#define VAL_GPIOI_MODER (PIN_MODE_ALTERNATE(GPIOI_LCD_G5) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_G6) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_ALTERNATE(GPIOI_SAI2_MCLKA) | \ + PIN_MODE_ALTERNATE(GPIOI_SAI2_SCKA) | \ + PIN_MODE_ALTERNATE(GPIOI_SAI2_SDA) | \ + PIN_MODE_ALTERNATE(GPIOI_SAI2_FSA) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_VSYNC) | \ + PIN_MODE_ALTERNATE(GPIOI_MII_RX_ER) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_HSYNC) | \ + PIN_MODE_OUTPUT(GPIOI_LED_GREEN) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_CLK) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_R0)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_LCD_G5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_G6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_SAI2_MCLKA) | \ + PIN_OTYPE_PUSHPULL(GPIOI_SAI2_SCKA) | \ + PIN_OTYPE_PUSHPULL(GPIOI_SAI2_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOI_SAI2_FSA) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_VSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOI_MII_RX_ER) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_HSYNC) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LED_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_R0)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_LCD_G5) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_G6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_SAI2_MCLKA) | \ + PIN_OSPEED_HIGH(GPIOI_SAI2_SCKA) | \ + PIN_OSPEED_HIGH(GPIOI_SAI2_SDA) | \ + PIN_OSPEED_HIGH(GPIOI_SAI2_FSA) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_VSYNC) | \ + PIN_OSPEED_HIGH(GPIOI_MII_RX_ER) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_HSYNC) | \ + PIN_OSPEED_HIGH(GPIOI_LED_GREEN) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_CLK) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_R0)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_LCD_G5) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_G6) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_SAI2_MCLKA) | \ + PIN_PUPDR_FLOATING(GPIOI_SAI2_SCKA) | \ + PIN_PUPDR_FLOATING(GPIOI_SAI2_SDA) | \ + PIN_PUPDR_FLOATING(GPIOI_SAI2_FSA) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_VSYNC) | \ + PIN_PUPDR_FLOATING(GPIOI_MII_RX_ER) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_HSYNC) | \ + PIN_PUPDR_PULLDOWN(GPIOI_LED_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_R0)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_LCD_G5) | \ + PIN_ODR_HIGH(GPIOI_LCD_G6) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_SAI2_MCLKA) | \ + PIN_ODR_HIGH(GPIOI_SAI2_SCKA) | \ + PIN_ODR_HIGH(GPIOI_SAI2_SDA) | \ + PIN_ODR_HIGH(GPIOI_SAI2_FSA) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_LCD_VSYNC) | \ + PIN_ODR_HIGH(GPIOI_MII_RX_ER) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_LCD_HSYNC) | \ + PIN_ODR_LOW(GPIOI_LED_GREEN) | \ + PIN_ODR_HIGH(GPIOI_LCD_CLK) | \ + PIN_ODR_HIGH(GPIOI_LCD_R0)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_LCD_G5, 14U) | \ + PIN_AFIO_AF(GPIOI_LCD_G6, 14U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_SAI2_MCLKA, 10U) | \ + PIN_AFIO_AF(GPIOI_SAI2_SCKA, 10U) | \ + PIN_AFIO_AF(GPIOI_SAI2_SDA, 10U) | \ + PIN_AFIO_AF(GPIOI_SAI2_FSA, 10U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_LCD_VSYNC, 14U) | \ + PIN_AFIO_AF(GPIOI_MII_RX_ER, 11U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_LCD_HSYNC, 14U) | \ + PIN_AFIO_AF(GPIOI_LED_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOI_LCD_CLK, 14U) | \ + PIN_AFIO_AF(GPIOI_LCD_R0, 14U)) + +/* + * GPIOJ setup: + * + * PJ0 - LCD_R1 (alternate 14). + * PJ1 - LCD_R2 (alternate 14). + * PJ2 - LED_RED (output pushpull maximum). + * PJ3 - LCD_R4 (alternate 14). + * PJ4 - LCD_R5 (alternate 14). + * PJ5 - LCD_R6 (alternate 14). + * PJ6 - LCD_R7 (alternate 14). + * PJ7 - LCD_G0 (alternate 14). + * PJ8 - LCD_G1 (alternate 14). + * PJ9 - LCD_G2 (alternate 14). + * PJ10 - LCD_G3 (alternate 14). + * PJ11 - LCD_G4 (alternate 14). + * PJ12 - LCD_B0 (alternate 14). + * PJ13 - LCD_B1 (alternate 14). + * PJ14 - LCD_B2 (alternate 14). + * PJ15 - LCD_B3 (alternate 14). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_ALTERNATE(GPIOJ_LCD_R1) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_R2) | \ + PIN_MODE_OUTPUT(GPIOJ_LED_RED) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_R4) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_R5) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_R6) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_R7) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_G0) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_G1) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_G2) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_G3) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_G4) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_B0) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_B1) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_B2) | \ + PIN_MODE_ALTERNATE(GPIOJ_LCD_B3)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_LCD_R1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_R2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LED_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_R4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_R5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_R6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_R7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_G0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_G1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_G2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_G3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_G4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_B0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_B1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_B2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LCD_B3)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_HIGH(GPIOJ_LCD_R1) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_R2) | \ + PIN_OSPEED_HIGH(GPIOJ_LED_RED) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_R4) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_R5) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_R6) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_R7) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_G0) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_G1) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_G2) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_G3) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_G4) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_B0) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_B1) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_B2) | \ + PIN_OSPEED_HIGH(GPIOJ_LCD_B3)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_LCD_R1) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_R2) | \ + PIN_PUPDR_PULLDOWN(GPIOJ_LED_RED) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_R4) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_R5) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_R6) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_R7) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_G0) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_G1) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_G2) | \ + PIN_PUPDR_PULLUP(GPIOJ_LCD_G3) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_G4) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_B0) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_B1) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_B2) | \ + PIN_PUPDR_FLOATING(GPIOJ_LCD_B3)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_LCD_R1) | \ + PIN_ODR_HIGH(GPIOJ_LCD_R2) | \ + PIN_ODR_LOW(GPIOJ_LED_RED) | \ + PIN_ODR_HIGH(GPIOJ_LCD_R4) | \ + PIN_ODR_HIGH(GPIOJ_LCD_R5) | \ + PIN_ODR_HIGH(GPIOJ_LCD_R6) | \ + PIN_ODR_HIGH(GPIOJ_LCD_R7) | \ + PIN_ODR_HIGH(GPIOJ_LCD_G0) | \ + PIN_ODR_HIGH(GPIOJ_LCD_G1) | \ + PIN_ODR_HIGH(GPIOJ_LCD_G2) | \ + PIN_ODR_HIGH(GPIOJ_LCD_G3) | \ + PIN_ODR_HIGH(GPIOJ_LCD_G4) | \ + PIN_ODR_HIGH(GPIOJ_LCD_B0) | \ + PIN_ODR_HIGH(GPIOJ_LCD_B1) | \ + PIN_ODR_HIGH(GPIOJ_LCD_B2) | \ + PIN_ODR_HIGH(GPIOJ_LCD_B3)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_LCD_R1, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_R2, 14U) | \ + PIN_AFIO_AF(GPIOJ_LED_RED, 0U) | \ + PIN_AFIO_AF(GPIOJ_LCD_R4, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_R5, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_R6, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_R7, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_G0, 14U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_LCD_G1, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_G2, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_G3, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_G4, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_B0, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_B1, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_B2, 14U) | \ + PIN_AFIO_AF(GPIOJ_LCD_B3, 14U)) + +/* + * GPIOK setup: + * + * PK0 - LCD_BL (output pushpull minimum). + * PK1 - PIN1 (input floating). + * PK2 - LCD_G7 (alternate 14). + * PK3 - LCD_B4 (alternate 14). + * PK4 - LCD_B5 (alternate 14). + * PK5 - LCD_B6 (alternate 14). + * PK6 - LCD_B7 (alternate 14). + * PK7 - LCD_DE (alternate 14). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). + */ +#define VAL_GPIOK_MODER (PIN_MODE_OUTPUT(GPIOK_LCD_BL) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_ALTERNATE(GPIOK_LCD_G7) | \ + PIN_MODE_ALTERNATE(GPIOK_LCD_B4) | \ + PIN_MODE_ALTERNATE(GPIOK_LCD_B5) | \ + PIN_MODE_ALTERNATE(GPIOK_LCD_B6) | \ + PIN_MODE_ALTERNATE(GPIOK_LCD_B7) | \ + PIN_MODE_ALTERNATE(GPIOK_LCD_DE) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_LCD_BL) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_LCD_G7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_LCD_B4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_LCD_B5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_LCD_B6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_LCD_B7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_LCD_DE) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_LCD_BL) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_HIGH(GPIOK_LCD_G7) | \ + PIN_OSPEED_HIGH(GPIOK_LCD_B4) | \ + PIN_OSPEED_HIGH(GPIOK_LCD_B5) | \ + PIN_OSPEED_HIGH(GPIOK_LCD_B6) | \ + PIN_OSPEED_HIGH(GPIOK_LCD_B7) | \ + PIN_OSPEED_HIGH(GPIOK_LCD_DE) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLDOWN(GPIOK_LCD_BL) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOK_LCD_G7) | \ + PIN_PUPDR_FLOATING(GPIOK_LCD_B4) | \ + PIN_PUPDR_FLOATING(GPIOK_LCD_B5) | \ + PIN_PUPDR_FLOATING(GPIOK_LCD_B6) | \ + PIN_PUPDR_FLOATING(GPIOK_LCD_B7) | \ + PIN_PUPDR_FLOATING(GPIOK_LCD_DE) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_LOW(GPIOK_LCD_BL) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_LCD_G7) | \ + PIN_ODR_HIGH(GPIOK_LCD_B4) | \ + PIN_ODR_HIGH(GPIOK_LCD_B5) | \ + PIN_ODR_HIGH(GPIOK_LCD_B6) | \ + PIN_ODR_HIGH(GPIOK_LCD_B7) | \ + PIN_ODR_HIGH(GPIOK_LCD_DE) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_LCD_BL, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_LCD_G7, 14U) | \ + PIN_AFIO_AF(GPIOK_LCD_B4, 14U) | \ + PIN_AFIO_AF(GPIOK_LCD_B5, 14U) | \ + PIN_AFIO_AF(GPIOK_LCD_B6, 14U) | \ + PIN_AFIO_AF(GPIOK_LCD_B7, 14U) | \ + PIN_AFIO_AF(GPIOK_LCD_DE, 14U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.mk b/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.mk new file mode 100644 index 000000000..7cfe8b5a2 --- /dev/null +++ b/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32H750XB_DISCOVERY/board.c + +# Required include directories +BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32H750XB_DISCOVERY + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..8710727f5 --- /dev/null +++ b/os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,1459 @@ + + + + + resources/gencfg/processors/boards/stm32h7xx/templates + .. + 5.0.x + + STMicroelectronics STM32H750XB_DISCOVERY + ST_STM32H750XB_DISCOVERY + + + + MII_LAN8740A_ID + MII + + STM32H750xx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.fmpp b/os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.fmpp new file mode 100644 index 000000000..5003d98bb --- /dev/null +++ b/os/hal/boards/ST_STM32H750XB_DISCOVERY/cfg/board.fmpp @@ -0,0 +1,15 @@ +sourceRoot: ../../../../../tools/ftl/processors/boards/stm32h7xx/templates +outputRoot: .. +dataRoot: . + +freemarkerLinks: { + lib: ../../../../../tools/ftl/libs +} + +data : { + doc1:xml ( + board.chcfg + { + } + ) +}