From b88cbce874fb44ce66cb659de807bb621b514ce0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 5 Oct 2013 18:35:39 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6355 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/I2Cv1/i2c_lld.c | 4 +- os/hal/ports/STM32/I2Cv1/i2c_lld.h | 52 +++++++++++++++++++++++-- os/hal/ports/STM32F1xx/stm32_registry.h | 8 ++-- 3 files changed, 55 insertions(+), 9 deletions(-) diff --git a/os/hal/ports/STM32/I2Cv1/i2c_lld.c b/os/hal/ports/STM32/I2Cv1/i2c_lld.c index 35c607330..bfc45fa09 100644 --- a/os/hal/ports/STM32/I2Cv1/i2c_lld.c +++ b/os/hal/ports/STM32/I2Cv1/i2c_lld.c @@ -706,7 +706,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, systime_t start, end; #if defined(STM32F1XX_I2C) - osalDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout"); + osalDbgCheck(rxbytes > 1); #endif /* Resetting error flags for this transfer.*/ @@ -789,7 +789,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, systime_t start, end; #if defined(STM32F1XX_I2C) - osalDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL)))); + osalDbgCheck((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))); #endif /* Resetting error flags for this transfer.*/ diff --git a/os/hal/ports/STM32/I2Cv1/i2c_lld.h b/os/hal/ports/STM32/I2Cv1/i2c_lld.h index a92e48e26..c36b4bcfe 100644 --- a/os/hal/ports/STM32/I2Cv1/i2c_lld.h +++ b/os/hal/ports/STM32/I2Cv1/i2c_lld.h @@ -205,9 +205,9 @@ /* Flag for the whole STM32F1XX family. */ #if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ - defined(STM32F10X_HD) || defined(STM32F10X_XL) || \ - defined(STM32F10X_CL) + defined(STM32F10X_HD_VL) || defined(STM32F10X_LD) || \ + defined(STM32F10X_MD) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) #define STM32F1XX_I2C #endif /** @} */ @@ -234,6 +234,51 @@ #error "I2C driver activated but no I2C peripheral assigned" #endif +#if STM32_I2C_USE_I2C1 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C1" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C2" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C3" +#endif + +#if STM32_I2C_USE_I2C1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to I2C1" +#endif + +#if STM32_I2C_USE_I2C2 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY) +#error "Invalid DMA priority assigned to I2C2" +#endif + +#if STM32_I2C_USE_I2C3 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C3_DMA_PRIORITY) +#error "Invalid DMA priority assigned to I2C3" +#endif + +/* The following checks are only required when there is a DMA able to + reassign streams to different channels.*/ +#if STM32_ADVANCED_DMA +/* Check on the presence of the DMA streams settings in mcuconf.h.*/ +#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \ + !defined(STM32_I2C_I2C1_TX_DMA_STREAM)) +#error "I2C1 DMA streams not defined" +#endif + +#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \ + !defined(STM32_I2C_I2C2_TX_DMA_STREAM)) +#error "I2C2 DMA streams not defined" +#endif + +/* Check on the validity of the assigned DMA channels.*/ #if STM32_I2C_USE_I2C1 && \ !STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \ STM32_I2C1_RX_DMA_MSK) @@ -269,6 +314,7 @@ STM32_I2C3_TX_DMA_MSK) #error "invalid DMA stream associated to I2C3 TX" #endif +#endif /* STM32_ADVANCED_DMA */ #if !defined(STM32_DMA_REQUIRED) #define STM32_DMA_REQUIRED diff --git a/os/hal/ports/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32F1xx/stm32_registry.h index e2ae3779c..d03894d40 100644 --- a/os/hal/ports/STM32F1xx/stm32_registry.h +++ b/os/hal/ports/STM32F1xx/stm32_registry.h @@ -491,7 +491,7 @@ #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) @@ -626,7 +626,7 @@ #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) @@ -796,7 +796,7 @@ #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) @@ -966,7 +966,7 @@ #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C2 TRUE #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)