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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2093 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-07-27 08:36:01 +00:00
parent 5b4d534a2c
commit b91f48eb10
9 changed files with 169 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
os/hal/platforms/STM32/adc_lld.c
View File

@ -54,14 +54,14 @@ ADCDriver ADCD1;
/**
* @brief ADC1 DMA interrupt handler (channel 1).
*/
CH_IRQ_HANDLER(Vector6C) {
CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
uint32_t isr;
CH_IRQ_PROLOGUE();
isr = DMA1->ISR;
DMA1->IFCR |= DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 |
DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;
DMA1->IFCR = DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 |
DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;
if ((isr & DMA_ISR_HTIF1) != 0) {
/* Half transfer processing.*/
if (ADCD1.ad_callback != NULL) {

47
os/hal/platforms/STM32/can_lld.c
View File

@ -18,8 +18,9 @@
*/
/**
* @file STM32/can_lld.c
* @brief STM32 CAN subsystem low level driver source.
* @file STM32/can_lld.c
* @brief STM32 CAN subsystem low level driver source.
*
* @addtogroup STM32_CAN
* @{
*/
@ -53,7 +54,7 @@ CANDriver CAND1;
/*
* CAN1 TX interrupt handler.
*/
CH_IRQ_HANDLER(Vector8C) {
CH_IRQ_HANDLER(CAN1_TX_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -71,7 +72,7 @@ CH_IRQ_HANDLER(Vector8C) {
/*
* CAN1 RX0 interrupt handler.
*/
CH_IRQ_HANDLER(Vector90) {
CH_IRQ_HANDLER(CAN1_RX0_IRQHandler) {
uint32_t rf0r;
CH_IRQ_PROLOGUE();
@ -101,7 +102,7 @@ CH_IRQ_HANDLER(Vector90) {
/*
* CAN1 RX1 interrupt handler.
*/
CH_IRQ_HANDLER(Vector94) {
CH_IRQ_HANDLER(CAN1_RX1_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -113,7 +114,7 @@ CH_IRQ_HANDLER(Vector94) {
/*
* CAN1 SCE interrupt handler.
*/
CH_IRQ_HANDLER(Vector98) {
CH_IRQ_HANDLER(CAN1_SCE_IRQHandler) {
uint32_t msr;
CH_IRQ_PROLOGUE();
@ -149,7 +150,7 @@ CH_IRQ_HANDLER(Vector98) {
/*===========================================================================*/
/**
* @brief Low level CAN driver initialization.
* @brief Low level CAN driver initialization.
*/
void can_lld_init(void) {
@ -165,9 +166,9 @@ void can_lld_init(void) {
}
/**
* @brief Configures and activates the CAN peripheral.
* @brief Configures and activates the CAN peripheral.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] canp pointer to the @p CANDriver object
*/
void can_lld_start(CANDriver *canp) {
@ -249,9 +250,9 @@ void can_lld_start(CANDriver *canp) {
}
/**
* @brief Deactivates the CAN peripheral.
* @brief Deactivates the CAN peripheral.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] canp pointer to the @p CANDriver object
*/
void can_lld_stop(CANDriver *canp) {
@ -272,13 +273,13 @@ void can_lld_stop(CANDriver *canp) {
}
/**
* @brief Determines whether a frame can be transmitted.
* @brief Determines whether a frame can be transmitted.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] canp pointer to the @p CANDriver object
*
* @return The queue space availability.
* @retval FALSE no space in the transmit queue.
* @retval TRUE transmit slot available.
* @retval FALSE no space in the transmit queue.
* @retval TRUE transmit slot available.
*/
bool_t can_lld_can_transmit(CANDriver *canp) {
@ -286,7 +287,7 @@ bool_t can_lld_can_transmit(CANDriver *canp) {
}
/**
* @brief Inserts a frame into the transmit queue.
* @brief Inserts a frame into the transmit queue.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] ctfp pointer to the CAN frame to be transmitted
@ -311,13 +312,13 @@ void can_lld_transmit(CANDriver *canp, const CANTxFrame *ctfp) {
}
/**
* @brief Determines whether a frame has been received.
* @brief Determines whether a frame has been received.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[in] canp pointer to the @p CANDriver object
*
* @return The queue space availability.
* @retval FALSE no space in the transmit queue.
* @retval TRUE transmit slot available.
* @retval FALSE no space in the transmit queue.
* @retval TRUE transmit slot available.
*/
bool_t can_lld_can_receive(CANDriver *canp) {
@ -325,7 +326,7 @@ bool_t can_lld_can_receive(CANDriver *canp) {
}
/**
* @brief Receives a frame from the input queue.
* @brief Receives a frame from the input queue.
*
* @param[in] canp pointer to the @p CANDriver object
* @param[out] crfp pointer to the buffer where the CAN frame is copied
@ -359,7 +360,7 @@ void can_lld_receive(CANDriver *canp, CANRxFrame *crfp) {
#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
/**
* @brief Enters the sleep mode.
* @brief Enters the sleep mode.
*
* @param[in] canp pointer to the @p CANDriver object
*/
@ -369,7 +370,7 @@ void can_lld_sleep(CANDriver *canp) {
}
/**
* @brief Enforces leaving the sleep mode.
* @brief Enforces leaving the sleep mode.
*
* @param[in] canp pointer to the @p CANDriver object
*/

6
os/hal/platforms/STM32/hal_lld_f103.h
View File

@ -103,8 +103,10 @@
#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */
#define USB_HP_CAN1_TX_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/
#define USB_LP_CAN1_RX0_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/
#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */
#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/
#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */
#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/
#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */
#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */
#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */

73
os/hal/platforms/STM32/pwm_lld.c
View File

@ -18,8 +18,9 @@
*/
/**
* @file STM32/pwm_lld.c
* @brief STM32 PWM subsystem low level driver header.
* @file STM32/pwm_lld.c
* @brief STM32 PWM subsystem low level driver header.
*
* @addtogroup STM32_PWM
* @{
*/
@ -34,32 +35,32 @@
/*===========================================================================*/
/**
* @brief PWM1 driver identifier.
* @note The driver PWM1 allocates the complex timer TIM1 when enabled.
* @brief PWM1 driver identifier.
* @note The driver PWM1 allocates the complex timer TIM1 when enabled.
*/
#if defined(USE_STM32_PWM1) || defined(__DOXYGEN__)
PWMDriver PWMD1;
#endif
/**
* @brief PWM2 driver identifier.
* @note The driver PWM2 allocates the timer TIM2 when enabled.
* @brief PWM2 driver identifier.
* @note The driver PWM2 allocates the timer TIM2 when enabled.
*/
#if defined(USE_STM32_PWM2) || defined(__DOXYGEN__)
PWMDriver PWMD2;
#endif
/**
* @brief PWM3 driver identifier.
* @note The driver PWM3 allocates the timer TIM3 when enabled.
* @brief PWM3 driver identifier.
* @note The driver PWM3 allocates the timer TIM3 when enabled.
*/
#if defined(USE_STM32_PWM3) || defined(__DOXYGEN__)
PWMDriver PWMD3;
#endif
/**
* @brief PWM4 driver identifier.
* @note The driver PWM4 allocates the timer TIM4 when enabled.
* @brief PWM4 driver identifier.
* @note The driver PWM4 allocates the timer TIM4 when enabled.
*/
#if defined(USE_STM32_PWM4) || defined(__DOXYGEN__)
PWMDriver PWMD4;
@ -74,9 +75,9 @@ PWMDriver PWMD4;
/*===========================================================================*/
/**
* @brief Stops all channels.
* @brief Stops all channels.
*
* @param[in] pwmp pointer to a @p PWMDriver object
* @param[in] pwmp pointer to a @p PWMDriver object
*/
static void stop_channels(PWMDriver *pwmp) {
@ -92,10 +93,10 @@ static void stop_channels(PWMDriver *pwmp) {
#if USE_STM32_PWM2 || USE_STM32_PWM3 || USE_STM32_PWM4 || defined(__DOXYGEN__)
/**
* @brief Common TIM2...TIM4 IRQ handler.
* @note It is assumed that the various sources are only activated if the
* associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler.
* @brief Common TIM2...TIM4 IRQ handler.
* @note It is assumed that the various sources are only activated if the
* associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler.
*/
static void serve_interrupt(PWMDriver *pwmp) {
uint16_t sr;
@ -122,12 +123,12 @@ static void serve_interrupt(PWMDriver *pwmp) {
#if USE_STM32_PWM1
/**
* @brief TIM1 update interrupt handler.
* @note It is assumed that this interrupt is only activated if the callback
* pointer is not equal to @p NULL in order to not perform an extra
* check in a potentially critical interrupt handler.
* @brief TIM1 update interrupt handler.
* @note It is assumed that this interrupt is only activated if the callback
* pointer is not equal to @p NULL in order to not perform an extra
* check in a potentially critical interrupt handler.
*/
CH_IRQ_HANDLER(VectorA4) {
CH_IRQ_HANDLER(TIM1_UP_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -138,12 +139,12 @@ CH_IRQ_HANDLER(VectorA4) {
}
/**
* @brief TIM1 compare interrupt handler.
* @note It is assumed that the various sources are only activated if the
* associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler.
* @brief TIM1 compare interrupt handler.
* @note It is assumed that the various sources are only activated if the
* associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler.
*/
CH_IRQ_HANDLER(VectorAC) {
CH_IRQ_HANDLER(TIM1_CC_IRQHandler) {
uint16_t sr;
CH_IRQ_PROLOGUE();
@ -167,7 +168,7 @@ CH_IRQ_HANDLER(VectorAC) {
/**
* @brief TIM2 interrupt handler.
*/
CH_IRQ_HANDLER(VectorB0) {
CH_IRQ_HANDLER(TIM2_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -181,7 +182,7 @@ CH_IRQ_HANDLER(VectorB0) {
/**
* @brief TIM3 interrupt handler.
*/
CH_IRQ_HANDLER(VectorB4) {
CH_IRQ_HANDLER(TIM3_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -195,7 +196,7 @@ CH_IRQ_HANDLER(VectorB4) {
/**
* @brief TIM4 interrupt handler.
*/
CH_IRQ_HANDLER(VectorB8) {
CH_IRQ_HANDLER(TIM4_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -210,7 +211,7 @@ CH_IRQ_HANDLER(VectorB8) {
/*===========================================================================*/
/**
* @brief Low level PWM driver initialization.
* @brief Low level PWM driver initialization.
*/
void pwm_lld_init(void) {
@ -260,9 +261,9 @@ void pwm_lld_init(void) {
}
/**
* @brief Configures and activates the PWM peripheral.
* @brief Configures and activates the PWM peripheral.
*
* @param[in] pwmp pointer to a @p PWMDriver object
* @param[in] pwmp pointer to a @p PWMDriver object
*/
void pwm_lld_start(PWMDriver *pwmp) {
uint16_t ccer;
@ -354,9 +355,9 @@ void pwm_lld_start(PWMDriver *pwmp) {
}
/**
* @brief Deactivates the PWM peripheral.
* @brief Deactivates the PWM peripheral.
*
* @param[in] pwmp pointer to a @p PWMDriver object
* @param[in] pwmp pointer to a @p PWMDriver object
*/
void pwm_lld_stop(PWMDriver *pwmp) {
/* If in ready state then disables the PWM clock.*/
@ -395,7 +396,7 @@ void pwm_lld_stop(PWMDriver *pwmp) {
}
/**
* @brief Enables a PWM channel.
* @brief Enables a PWM channel.
*
* @param[in] pwmp pointer to a @p PWMDriver object
* @param[in] channel PWM channel identifier
@ -469,7 +470,7 @@ void pwm_lld_enable_channel(PWMDriver *pwmp,
}
/**
* @brief Disables a PWM channel.
* @brief Disables a PWM channel.
* @details The channel is disabled and its output line returned to the
* idle state.
*

10
os/hal/platforms/STM32/serial_lld.c
View File

@ -222,7 +222,7 @@ static void notify5(void) {
/*===========================================================================*/
#if USE_STM32_USART1 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorD4) {
CH_IRQ_HANDLER(USART1_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -233,7 +233,7 @@ CH_IRQ_HANDLER(VectorD4) {
#endif
#if USE_STM32_USART2 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorD8) {
CH_IRQ_HANDLER(USART2_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -244,7 +244,7 @@ CH_IRQ_HANDLER(VectorD8) {
#endif
#if USE_STM32_USART3 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorDC) {
CH_IRQ_HANDLER(USART3_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -256,7 +256,7 @@ CH_IRQ_HANDLER(VectorDC) {
#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
#if USE_STM32_UART4 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(Vector110) {
CH_IRQ_HANDLER(UART4_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -267,7 +267,7 @@ CH_IRQ_HANDLER(Vector110) {
#endif
#if USE_STM32_UART5 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(Vector114) {
CH_IRQ_HANDLER(UART5_IRQHandler) {
CH_IRQ_PROLOGUE();

36
os/hal/platforms/STM32/spi_lld.c
View File

@ -116,7 +116,7 @@ static void spi_start_wait(SPIDriver *spip, size_t n,
/**
* @brief SPI1 RX DMA interrupt handler (channel 2).
*/
CH_IRQ_HANDLER(Vector70) {
CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -124,8 +124,8 @@ CH_IRQ_HANDLER(Vector70) {
if ((DMA1->ISR & DMA_ISR_TEIF2) != 0) {
STM32_SPI1_DMA_ERROR_HOOK();
}
DMA1->IFCR |= DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 |
DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;
DMA1->IFCR = DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 |
DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;
CH_IRQ_EPILOGUE();
}
@ -133,13 +133,13 @@ CH_IRQ_HANDLER(Vector70) {
/**
* @brief SPI1 TX DMA interrupt handler (channel 3).
*/
CH_IRQ_HANDLER(Vector74) {
CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
CH_IRQ_PROLOGUE();
STM32_SPI1_DMA_ERROR_HOOK();
DMA1->IFCR |= DMA_IFCR_CGIF3 | DMA_IFCR_CTCIF3 |
DMA_IFCR_CHTIF3 | DMA_IFCR_CTEIF3;
DMA1->IFCR = DMA_IFCR_CGIF3 | DMA_IFCR_CTCIF3 |
DMA_IFCR_CHTIF3 | DMA_IFCR_CTEIF3;
CH_IRQ_EPILOGUE();
}
@ -149,7 +149,7 @@ CH_IRQ_HANDLER(Vector74) {
/**
* @brief SPI2 RX DMA interrupt handler (channel 4).
*/
CH_IRQ_HANDLER(Vector78) {
CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -157,8 +157,8 @@ CH_IRQ_HANDLER(Vector78) {
if ((DMA1->ISR & DMA_ISR_TEIF4) != 0) {
STM32_SPI2_DMA_ERROR_HOOK();
}
DMA1->IFCR |= DMA_IFCR_CGIF4 | DMA_IFCR_CTCIF4 |
DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4;
DMA1->IFCR = DMA_IFCR_CGIF4 | DMA_IFCR_CTCIF4 |
DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4;
CH_IRQ_EPILOGUE();
}
@ -166,13 +166,13 @@ CH_IRQ_HANDLER(Vector78) {
/**
* @brief SPI2 TX DMA interrupt handler (channel 5).
*/
CH_IRQ_HANDLER(Vector7C) {
CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
CH_IRQ_PROLOGUE();
STM32_SPI2_DMA_ERROR_HOOK();
DMA1->IFCR |= DMA_IFCR_CGIF5 | DMA_IFCR_CTCIF5 |
DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5;
DMA1->IFCR = DMA_IFCR_CGIF5 | DMA_IFCR_CTCIF5 |
DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5;
CH_IRQ_EPILOGUE();
}
@ -182,7 +182,7 @@ CH_IRQ_HANDLER(Vector7C) {
/**
* @brief SPI3 RX DMA interrupt handler (DMA2, channel 1).
*/
CH_IRQ_HANDLER(Vector120) {
CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
CH_IRQ_PROLOGUE();
@ -190,8 +190,8 @@ CH_IRQ_HANDLER(Vector120) {
if ((DMA2->ISR & DMA_ISR_TEIF1) != 0) {
STM32_SPI3_DMA_ERROR_HOOK();
}
DMA2->IFCR |= DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 |
DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;
DMA2->IFCR = DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 |
DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;
CH_IRQ_EPILOGUE();
}
@ -199,13 +199,13 @@ CH_IRQ_HANDLER(Vector120) {
/**
* @brief SPI3 TX DMA2 interrupt handler (DMA2, channel 2).
*/
CH_IRQ_HANDLER(Vector124) {
CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
CH_IRQ_PROLOGUE();
STM32_SPI3_DMA_ERROR_HOOK();
DMA2->IFCR |= DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 |
DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;
DMA2->IFCR = DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 |
DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;
CH_IRQ_EPILOGUE();
}

56
os/hal/platforms/STM32/stm32_dma.h
View File

@ -81,33 +81,49 @@ typedef struct {
/* Driver macros. */
/*===========================================================================*/
/** DMA1 registers block numeric address.*/
#define STM32_DMA1_BASE (AHBPERIPH_BASE + 0x0000)
/** Pointer to the DMA1 registers block.*/
#define STM32_DMA1 ((stm32_dma_t *)STM32_DMA1_BASE)
#define STM32_DMA1_CH1 (STM32_DMA1->channels[0])
#define STM32_DMA1_CH2 (STM32_DMA1->channels[1])
#define STM32_DMA1_CH3 (STM32_DMA1->channels[2])
#define STM32_DMA1_CH4 (STM32_DMA1->channels[3])
#define STM32_DMA1_CH5 (STM32_DMA1->channels[4])
#define STM32_DMA1_CH6 (STM32_DMA1->channels[5])
#define STM32_DMA1_CH7 (STM32_DMA1->channels[6])
/** Pointer to the DMA1 channel 1 registers block.*/
#define STM32_DMA1_CH1 (&STM32_DMA1->channels[0])
/** Pointer to the DMA1 channel 2 registers block.*/
#define STM32_DMA1_CH2 (&STM32_DMA1->channels[1])
/** Pointer to the DMA1 channel 3 registers block.*/
#define STM32_DMA1_CH3 (&STM32_DMA1->channels[2])
/** Pointer to the DMA1 channel 4 registers block.*/
#define STM32_DMA1_CH4 (&STM32_DMA1->channels[3])
/** Pointer to the DMA1 channel 5 registers block.*/
#define STM32_DMA1_CH5 (&STM32_DMA1->channels[4])
/** Pointer to the DMA1 channel 6 registers block.*/
#define STM32_DMA1_CH6 (&STM32_DMA1->channels[5])
/** Pointer to the DMA1 channel 7 registers block.*/
#define STM32_DMA1_CH7 (&STM32_DMA1->channels[6])
#if defined(STM32F10X_HD) || defined (STM32F10X_CL) || defined(__DOXYGEN__)
/** DMA2 registers block numeric address.*/
#define STM32_DMA2_BASE (AHBPERIPH_BASE + 0x0400)
/** Pointer to the DMA2 registers block.*/
#define STM32_DMA2 ((stm32_dma_t *)STM32_DMA2_BASE)
#define STM32_DMA2_CH1 (STM32_DMA2->channels[0])
#define STM32_DMA2_CH2 (STM32_DMA2->channels[1])
#define STM32_DMA2_CH3 (STM32_DMA2->channels[2])
#define STM32_DMA2_CH4 (STM32_DMA2->channels[3])
#define STM32_DMA2_CH5 (STM32_DMA2->channels[4])
/** Pointer to the DMA2 channel 1 registers block.*/
#define STM32_DMA2_CH1 (&STM32_DMA2->channels[0])
/** Pointer to the DMA2 channel 2 registers block.*/
#define STM32_DMA2_CH2 (&STM32_DMA2->channels[1])
/** Pointer to the DMA2 channel 3 registers block.*/
#define STM32_DMA2_CH3 (&STM32_DMA2->channels[2])
/** Pointer to the DMA2 channel 4 registers block.*/
#define STM32_DMA2_CH4 (&STM32_DMA2->channels[3])
/** Pointer to the DMA2 channel 5 registers block.*/
#define STM32_DMA2_CH5 (&STM32_DMA2->channels[4])
#endif
#define STM32_DMA_CHANNEL_1 0
#define STM32_DMA_CHANNEL_2 1
#define STM32_DMA_CHANNEL_3 2
#define STM32_DMA_CHANNEL_4 3
#define STM32_DMA_CHANNEL_5 4
#define STM32_DMA_CHANNEL_6 5
#define STM32_DMA_CHANNEL_7 6
#define STM32_DMA_CHANNEL_1 0 /**< @brief DMA channel 1. */
#define STM32_DMA_CHANNEL_2 1 /**< @brief DMA channel 2. */
#define STM32_DMA_CHANNEL_3 2 /**< @brief DMA channel 3. */
#define STM32_DMA_CHANNEL_4 3 /**< @brief DMA channel 4. */
#define STM32_DMA_CHANNEL_5 4 /**< @brief DMA channel 5. */
#define STM32_DMA_CHANNEL_6 5 /**< @brief DMA channel 6. */
#define STM32_DMA_CHANNEL_7 6 /**< @brief DMA channel 7. */
/**
* @brief DMA channel setup.
@ -126,7 +142,7 @@ typedef struct {
/**
* @brief DMA channel disable.
* @note Channel's pending interrupt are cleared.
* @note Channel's pending interrupts are cleared.
*/
#define dmaDisableChannel(dmap, ch) { \
(dmap)->channels[ch].CCR = 0; \

53
os/hal/platforms/STM32/uart_lld.c
View File

@ -47,22 +47,6 @@ UARTDriver UARTD1;
/* Driver local functions. */
/*===========================================================================*/
#define dma_setup(dmap, cndtr, cmar, ccr) { \
(dmap)->CNDTR = (uint32_t)(cndtr); \
(dmap)->CMAR = (uint32_t)(cmar); \
(dmap)->CCR = (uint32_t)(ccr); \
}
#define dma_disable(dmap) { \
(dmap)->CCR = 0; \
}
#define dma_rx_setup(uartp, cndtr, cmar, ccr) \
dma_setup((uartp)->ud_dmarx, (cndtr), (cmar), (uartp)->ud_dmaccr|(ccr))
#define dma_tx_setup(uartp, cndtr, cmar, ccr) { \
dma_setup((uartp)->ud_dmatx, (cndtr), (cmar), (uartp)->ud_dmaccr|(ccr))
/**
* @brief USART initialization.
* @details This function must be invoked with interrupts disabled.
@ -120,6 +104,43 @@ static void usart_stop(UARTDriver *uartp) {
/* Driver interrupt handlers. */
/*===========================================================================*/
#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
/**
* @brief USART1 RX DMA interrupt handler (channel 4).
*/
CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
CH_IRQ_PROLOGUE();
DMA1->IFCR |= DMA_IFCR_CGIF4 | DMA_IFCR_CTCIF4 |
DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4;
CH_IRQ_EPILOGUE();
}
/**
* @brief USART1 TX DMA interrupt handler (channel 5).
*/
CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
CH_IRQ_PROLOGUE();
DMA1->IFCR |= DMA_IFCR_CGIF5 | DMA_IFCR_CTCIF5 |
DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5;
CH_IRQ_EPILOGUE();
}
CH_IRQ_HANDLER(USART2_IRQHandler) {
CH_IRQ_PROLOGUE();
serve_interrupt(&SD2);
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/

5
readme.txt
View File

@ -76,16 +76,21 @@
3025549)(backported to 2.0.2).
- FIX: Added option to enforce the stack alignment to 32 or 64 bits in the
Cortex-Mx port (bug 3025133)(backported to 2.0.2).
- NEW: Centralized DMA macros in the STM32 HAL.
- NEW: New UART device driver model, this device driver allows unbuffered,
callback driven access to UART-type devices.
- NEW: Added friendly interrupt vectors names to the STM32 HAL (change request
3023944).
- NEW: Added support for SPI3 in the STM32 HAL.
- CHANGE: Redeclared the IRQ handlers in the various STM32 drivers using the
new friendly vector names.
- CHANGE: Removed the option -mabi=apcs-gnu from all the Cortex-Mx demos. The
option is not compatible with the 64 bits stack alignment now default in
the Cortex-Mx port. Note that the 64 bits alignment has a cost both as
performance and as space but it is the "standard".
- OPT: Small speed optimization in the STM32 SPI driver.
- OPT: Optimized DMA clearing in STM32 ADC and SPI drivers, there was no need
to read/modify/write the IFCR DMA register, it is write only.
- Fixed various documentation errors.
*** 2.1.0 ***