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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2093 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-07-27 08:36:01 +00:00
parent 5b4d534a2c
commit b91f48eb10
9 changed files with 169 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
os/hal/platforms/STM32/adc_lld.c
View File

@ -54,13 +54,13 @@ ADCDriver ADCD1;
/** /**
* @brief ADC1 DMA interrupt handler (channel 1). * @brief ADC1 DMA interrupt handler (channel 1).
*/ */
CH_IRQ_HANDLER(Vector6C) { CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
uint32_t isr; uint32_t isr;
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
isr = DMA1->ISR; isr = DMA1->ISR;
DMA1->IFCR |= DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 | DMA1->IFCR = DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 |
DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1; DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;
if ((isr & DMA_ISR_HTIF1) != 0) { if ((isr & DMA_ISR_HTIF1) != 0) {
/* Half transfer processing.*/ /* Half transfer processing.*/

9
os/hal/platforms/STM32/can_lld.c
View File

@ -20,6 +20,7 @@
/** /**
* @file STM32/can_lld.c * @file STM32/can_lld.c
* @brief STM32 CAN subsystem low level driver source. * @brief STM32 CAN subsystem low level driver source.
*
* @addtogroup STM32_CAN * @addtogroup STM32_CAN
* @{ * @{
*/ */
@ -53,7 +54,7 @@ CANDriver CAND1;
/* /*
* CAN1 TX interrupt handler. * CAN1 TX interrupt handler.
*/ */
CH_IRQ_HANDLER(Vector8C) { CH_IRQ_HANDLER(CAN1_TX_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -71,7 +72,7 @@ CH_IRQ_HANDLER(Vector8C) {
/* /*
* CAN1 RX0 interrupt handler. * CAN1 RX0 interrupt handler.
*/ */
CH_IRQ_HANDLER(Vector90) { CH_IRQ_HANDLER(CAN1_RX0_IRQHandler) {
uint32_t rf0r; uint32_t rf0r;
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -101,7 +102,7 @@ CH_IRQ_HANDLER(Vector90) {
/* /*
* CAN1 RX1 interrupt handler. * CAN1 RX1 interrupt handler.
*/ */
CH_IRQ_HANDLER(Vector94) { CH_IRQ_HANDLER(CAN1_RX1_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -113,7 +114,7 @@ CH_IRQ_HANDLER(Vector94) {
/* /*
* CAN1 SCE interrupt handler. * CAN1 SCE interrupt handler.
*/ */
CH_IRQ_HANDLER(Vector98) { CH_IRQ_HANDLER(CAN1_SCE_IRQHandler) {
uint32_t msr; uint32_t msr;
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();

6
os/hal/platforms/STM32/hal_lld_f103.h
View File

@ -103,8 +103,10 @@
#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ #define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ #define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ #define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */
#define USB_HP_CAN1_TX_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ #define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */
#define USB_LP_CAN1_RX0_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ #define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/
#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */
#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/
#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ #define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */
#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ #define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */
#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ #define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */

11
os/hal/platforms/STM32/pwm_lld.c
View File

@ -20,6 +20,7 @@
/** /**
* @file STM32/pwm_lld.c * @file STM32/pwm_lld.c
* @brief STM32 PWM subsystem low level driver header. * @brief STM32 PWM subsystem low level driver header.
*
* @addtogroup STM32_PWM * @addtogroup STM32_PWM
* @{ * @{
*/ */
@ -127,7 +128,7 @@ static void serve_interrupt(PWMDriver *pwmp) {
* pointer is not equal to @p NULL in order to not perform an extra * pointer is not equal to @p NULL in order to not perform an extra
* check in a potentially critical interrupt handler. * check in a potentially critical interrupt handler.
*/ */
CH_IRQ_HANDLER(VectorA4) { CH_IRQ_HANDLER(TIM1_UP_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -143,7 +144,7 @@ CH_IRQ_HANDLER(VectorA4) {
* associated callback pointer is not equal to @p NULL in order to not * associated callback pointer is not equal to @p NULL in order to not
* perform an extra check in a potentially critical interrupt handler. * perform an extra check in a potentially critical interrupt handler.
*/ */
CH_IRQ_HANDLER(VectorAC) { CH_IRQ_HANDLER(TIM1_CC_IRQHandler) {
uint16_t sr; uint16_t sr;
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -167,7 +168,7 @@ CH_IRQ_HANDLER(VectorAC) {
/** /**
* @brief TIM2 interrupt handler. * @brief TIM2 interrupt handler.
*/ */
CH_IRQ_HANDLER(VectorB0) { CH_IRQ_HANDLER(TIM2_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -181,7 +182,7 @@ CH_IRQ_HANDLER(VectorB0) {
/** /**
* @brief TIM3 interrupt handler. * @brief TIM3 interrupt handler.
*/ */
CH_IRQ_HANDLER(VectorB4) { CH_IRQ_HANDLER(TIM3_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -195,7 +196,7 @@ CH_IRQ_HANDLER(VectorB4) {
/** /**
* @brief TIM4 interrupt handler. * @brief TIM4 interrupt handler.
*/ */
CH_IRQ_HANDLER(VectorB8) { CH_IRQ_HANDLER(TIM4_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();

10
os/hal/platforms/STM32/serial_lld.c
View File

@ -222,7 +222,7 @@ static void notify5(void) {
/*===========================================================================*/ /*===========================================================================*/
#if USE_STM32_USART1 || defined(__DOXYGEN__) #if USE_STM32_USART1 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorD4) { CH_IRQ_HANDLER(USART1_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -233,7 +233,7 @@ CH_IRQ_HANDLER(VectorD4) {
#endif #endif
#if USE_STM32_USART2 || defined(__DOXYGEN__) #if USE_STM32_USART2 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorD8) { CH_IRQ_HANDLER(USART2_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -244,7 +244,7 @@ CH_IRQ_HANDLER(VectorD8) {
#endif #endif
#if USE_STM32_USART3 || defined(__DOXYGEN__) #if USE_STM32_USART3 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(VectorDC) { CH_IRQ_HANDLER(USART3_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -256,7 +256,7 @@ CH_IRQ_HANDLER(VectorDC) {
#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__) #if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
#if USE_STM32_UART4 || defined(__DOXYGEN__) #if USE_STM32_UART4 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(Vector110) { CH_IRQ_HANDLER(UART4_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -267,7 +267,7 @@ CH_IRQ_HANDLER(Vector110) {
#endif #endif
#if USE_STM32_UART5 || defined(__DOXYGEN__) #if USE_STM32_UART5 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(Vector114) { CH_IRQ_HANDLER(UART5_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();

24
os/hal/platforms/STM32/spi_lld.c
View File

@ -116,7 +116,7 @@ static void spi_start_wait(SPIDriver *spip, size_t n,
/** /**
* @brief SPI1 RX DMA interrupt handler (channel 2). * @brief SPI1 RX DMA interrupt handler (channel 2).
*/ */
CH_IRQ_HANDLER(Vector70) { CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -124,7 +124,7 @@ CH_IRQ_HANDLER(Vector70) {
if ((DMA1->ISR & DMA_ISR_TEIF2) != 0) { if ((DMA1->ISR & DMA_ISR_TEIF2) != 0) {
STM32_SPI1_DMA_ERROR_HOOK(); STM32_SPI1_DMA_ERROR_HOOK();
} }
DMA1->IFCR |= DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 | DMA1->IFCR = DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 |
DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2; DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -133,12 +133,12 @@ CH_IRQ_HANDLER(Vector70) {
/** /**
* @brief SPI1 TX DMA interrupt handler (channel 3). * @brief SPI1 TX DMA interrupt handler (channel 3).
*/ */
CH_IRQ_HANDLER(Vector74) { CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
STM32_SPI1_DMA_ERROR_HOOK(); STM32_SPI1_DMA_ERROR_HOOK();
DMA1->IFCR |= DMA_IFCR_CGIF3 | DMA_IFCR_CTCIF3 | DMA1->IFCR = DMA_IFCR_CGIF3 | DMA_IFCR_CTCIF3 |
DMA_IFCR_CHTIF3 | DMA_IFCR_CTEIF3; DMA_IFCR_CHTIF3 | DMA_IFCR_CTEIF3;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -149,7 +149,7 @@ CH_IRQ_HANDLER(Vector74) {
/** /**
* @brief SPI2 RX DMA interrupt handler (channel 4). * @brief SPI2 RX DMA interrupt handler (channel 4).
*/ */
CH_IRQ_HANDLER(Vector78) { CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -157,7 +157,7 @@ CH_IRQ_HANDLER(Vector78) {
if ((DMA1->ISR & DMA_ISR_TEIF4) != 0) { if ((DMA1->ISR & DMA_ISR_TEIF4) != 0) {
STM32_SPI2_DMA_ERROR_HOOK(); STM32_SPI2_DMA_ERROR_HOOK();
} }
DMA1->IFCR |= DMA_IFCR_CGIF4 | DMA_IFCR_CTCIF4 | DMA1->IFCR = DMA_IFCR_CGIF4 | DMA_IFCR_CTCIF4 |
DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4; DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -166,12 +166,12 @@ CH_IRQ_HANDLER(Vector78) {
/** /**
* @brief SPI2 TX DMA interrupt handler (channel 5). * @brief SPI2 TX DMA interrupt handler (channel 5).
*/ */
CH_IRQ_HANDLER(Vector7C) { CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
STM32_SPI2_DMA_ERROR_HOOK(); STM32_SPI2_DMA_ERROR_HOOK();
DMA1->IFCR |= DMA_IFCR_CGIF5 | DMA_IFCR_CTCIF5 | DMA1->IFCR = DMA_IFCR_CGIF5 | DMA_IFCR_CTCIF5 |
DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5; DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -182,7 +182,7 @@ CH_IRQ_HANDLER(Vector7C) {
/** /**
* @brief SPI3 RX DMA interrupt handler (DMA2, channel 1). * @brief SPI3 RX DMA interrupt handler (DMA2, channel 1).
*/ */
CH_IRQ_HANDLER(Vector120) { CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
@ -190,7 +190,7 @@ CH_IRQ_HANDLER(Vector120) {
if ((DMA2->ISR & DMA_ISR_TEIF1) != 0) { if ((DMA2->ISR & DMA_ISR_TEIF1) != 0) {
STM32_SPI3_DMA_ERROR_HOOK(); STM32_SPI3_DMA_ERROR_HOOK();
} }
DMA2->IFCR |= DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 | DMA2->IFCR = DMA_IFCR_CGIF1 | DMA_IFCR_CTCIF1 |
DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1; DMA_IFCR_CHTIF1 | DMA_IFCR_CTEIF1;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();
@ -199,12 +199,12 @@ CH_IRQ_HANDLER(Vector120) {
/** /**
* @brief SPI3 TX DMA2 interrupt handler (DMA2, channel 2). * @brief SPI3 TX DMA2 interrupt handler (DMA2, channel 2).
*/ */
CH_IRQ_HANDLER(Vector124) { CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
CH_IRQ_PROLOGUE(); CH_IRQ_PROLOGUE();
STM32_SPI3_DMA_ERROR_HOOK(); STM32_SPI3_DMA_ERROR_HOOK();
DMA2->IFCR |= DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 | DMA2->IFCR = DMA_IFCR_CGIF2 | DMA_IFCR_CTCIF2 |
DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2; DMA_IFCR_CHTIF2 | DMA_IFCR_CTEIF2;
CH_IRQ_EPILOGUE(); CH_IRQ_EPILOGUE();

56
os/hal/platforms/STM32/stm32_dma.h
View File

@ -81,33 +81,49 @@ typedef struct {
/* Driver macros. */ /* Driver macros. */
/*===========================================================================*/ /*===========================================================================*/
/** DMA1 registers block numeric address.*/
#define STM32_DMA1_BASE (AHBPERIPH_BASE + 0x0000) #define STM32_DMA1_BASE (AHBPERIPH_BASE + 0x0000)
/** Pointer to the DMA1 registers block.*/
#define STM32_DMA1 ((stm32_dma_t *)STM32_DMA1_BASE) #define STM32_DMA1 ((stm32_dma_t *)STM32_DMA1_BASE)
#define STM32_DMA1_CH1 (STM32_DMA1->channels[0]) /** Pointer to the DMA1 channel 1 registers block.*/
#define STM32_DMA1_CH2 (STM32_DMA1->channels[1]) #define STM32_DMA1_CH1 (&STM32_DMA1->channels[0])
#define STM32_DMA1_CH3 (STM32_DMA1->channels[2]) /** Pointer to the DMA1 channel 2 registers block.*/
#define STM32_DMA1_CH4 (STM32_DMA1->channels[3]) #define STM32_DMA1_CH2 (&STM32_DMA1->channels[1])
#define STM32_DMA1_CH5 (STM32_DMA1->channels[4]) /** Pointer to the DMA1 channel 3 registers block.*/
#define STM32_DMA1_CH6 (STM32_DMA1->channels[5]) #define STM32_DMA1_CH3 (&STM32_DMA1->channels[2])
#define STM32_DMA1_CH7 (STM32_DMA1->channels[6]) /** Pointer to the DMA1 channel 4 registers block.*/
#define STM32_DMA1_CH4 (&STM32_DMA1->channels[3])
/** Pointer to the DMA1 channel 5 registers block.*/
#define STM32_DMA1_CH5 (&STM32_DMA1->channels[4])
/** Pointer to the DMA1 channel 6 registers block.*/
#define STM32_DMA1_CH6 (&STM32_DMA1->channels[5])
/** Pointer to the DMA1 channel 7 registers block.*/
#define STM32_DMA1_CH7 (&STM32_DMA1->channels[6])
#if defined(STM32F10X_HD) || defined (STM32F10X_CL) || defined(__DOXYGEN__) #if defined(STM32F10X_HD) || defined (STM32F10X_CL) || defined(__DOXYGEN__)
/** DMA2 registers block numeric address.*/
#define STM32_DMA2_BASE (AHBPERIPH_BASE + 0x0400) #define STM32_DMA2_BASE (AHBPERIPH_BASE + 0x0400)
/** Pointer to the DMA2 registers block.*/
#define STM32_DMA2 ((stm32_dma_t *)STM32_DMA2_BASE) #define STM32_DMA2 ((stm32_dma_t *)STM32_DMA2_BASE)
#define STM32_DMA2_CH1 (STM32_DMA2->channels[0]) /** Pointer to the DMA2 channel 1 registers block.*/
#define STM32_DMA2_CH2 (STM32_DMA2->channels[1]) #define STM32_DMA2_CH1 (&STM32_DMA2->channels[0])
#define STM32_DMA2_CH3 (STM32_DMA2->channels[2]) /** Pointer to the DMA2 channel 2 registers block.*/
#define STM32_DMA2_CH4 (STM32_DMA2->channels[3]) #define STM32_DMA2_CH2 (&STM32_DMA2->channels[1])
#define STM32_DMA2_CH5 (STM32_DMA2->channels[4]) /** Pointer to the DMA2 channel 3 registers block.*/
#define STM32_DMA2_CH3 (&STM32_DMA2->channels[2])
/** Pointer to the DMA2 channel 4 registers block.*/
#define STM32_DMA2_CH4 (&STM32_DMA2->channels[3])
/** Pointer to the DMA2 channel 5 registers block.*/
#define STM32_DMA2_CH5 (&STM32_DMA2->channels[4])
#endif #endif
#define STM32_DMA_CHANNEL_1 0 #define STM32_DMA_CHANNEL_1 0 /**< @brief DMA channel 1. */
#define STM32_DMA_CHANNEL_2 1 #define STM32_DMA_CHANNEL_2 1 /**< @brief DMA channel 2. */
#define STM32_DMA_CHANNEL_3 2 #define STM32_DMA_CHANNEL_3 2 /**< @brief DMA channel 3. */
#define STM32_DMA_CHANNEL_4 3 #define STM32_DMA_CHANNEL_4 3 /**< @brief DMA channel 4. */
#define STM32_DMA_CHANNEL_5 4 #define STM32_DMA_CHANNEL_5 4 /**< @brief DMA channel 5. */
#define STM32_DMA_CHANNEL_6 5 #define STM32_DMA_CHANNEL_6 5 /**< @brief DMA channel 6. */
#define STM32_DMA_CHANNEL_7 6 #define STM32_DMA_CHANNEL_7 6 /**< @brief DMA channel 7. */
/** /**
* @brief DMA channel setup. * @brief DMA channel setup.
@ -126,7 +142,7 @@ typedef struct {
/** /**
* @brief DMA channel disable. * @brief DMA channel disable.
* @note Channel's pending interrupt are cleared. * @note Channel's pending interrupts are cleared.
*/ */
#define dmaDisableChannel(dmap, ch) { \ #define dmaDisableChannel(dmap, ch) { \
(dmap)->channels[ch].CCR = 0; \ (dmap)->channels[ch].CCR = 0; \

53
os/hal/platforms/STM32/uart_lld.c
View File

@ -47,22 +47,6 @@ UARTDriver UARTD1;
/* Driver local functions. */ /* Driver local functions. */
/*===========================================================================*/ /*===========================================================================*/
#define dma_setup(dmap, cndtr, cmar, ccr) { \
(dmap)->CNDTR = (uint32_t)(cndtr); \
(dmap)->CMAR = (uint32_t)(cmar); \
(dmap)->CCR = (uint32_t)(ccr); \
}
#define dma_disable(dmap) { \
(dmap)->CCR = 0; \
}
#define dma_rx_setup(uartp, cndtr, cmar, ccr) \
dma_setup((uartp)->ud_dmarx, (cndtr), (cmar), (uartp)->ud_dmaccr|(ccr))
#define dma_tx_setup(uartp, cndtr, cmar, ccr) { \
dma_setup((uartp)->ud_dmatx, (cndtr), (cmar), (uartp)->ud_dmaccr|(ccr))
/** /**
* @brief USART initialization. * @brief USART initialization.
* @details This function must be invoked with interrupts disabled. * @details This function must be invoked with interrupts disabled.
@ -120,6 +104,43 @@ static void usart_stop(UARTDriver *uartp) {
/* Driver interrupt handlers. */ /* Driver interrupt handlers. */
/*===========================================================================*/ /*===========================================================================*/
#if STM32_UART_USE_USART1 || defined(__DOXYGEN__)
/**
* @brief USART1 RX DMA interrupt handler (channel 4).
*/
CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
CH_IRQ_PROLOGUE();
DMA1->IFCR |= DMA_IFCR_CGIF4 | DMA_IFCR_CTCIF4 |
DMA_IFCR_CHTIF4 | DMA_IFCR_CTEIF4;
CH_IRQ_EPILOGUE();
}
/**
* @brief USART1 TX DMA interrupt handler (channel 5).
*/
CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
CH_IRQ_PROLOGUE();
DMA1->IFCR |= DMA_IFCR_CGIF5 | DMA_IFCR_CTCIF5 |
DMA_IFCR_CHTIF5 | DMA_IFCR_CTEIF5;
CH_IRQ_EPILOGUE();
}
CH_IRQ_HANDLER(USART2_IRQHandler) {
CH_IRQ_PROLOGUE();
serve_interrupt(&SD2);
CH_IRQ_EPILOGUE();
}
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported functions. */ /* Driver exported functions. */
/*===========================================================================*/ /*===========================================================================*/

5
readme.txt
View File

@ -76,16 +76,21 @@
3025549)(backported to 2.0.2). 3025549)(backported to 2.0.2).
- FIX: Added option to enforce the stack alignment to 32 or 64 bits in the - FIX: Added option to enforce the stack alignment to 32 or 64 bits in the
Cortex-Mx port (bug 3025133)(backported to 2.0.2). Cortex-Mx port (bug 3025133)(backported to 2.0.2).
- NEW: Centralized DMA macros in the STM32 HAL.
- NEW: New UART device driver model, this device driver allows unbuffered, - NEW: New UART device driver model, this device driver allows unbuffered,
callback driven access to UART-type devices. callback driven access to UART-type devices.
- NEW: Added friendly interrupt vectors names to the STM32 HAL (change request - NEW: Added friendly interrupt vectors names to the STM32 HAL (change request
3023944). 3023944).
- NEW: Added support for SPI3 in the STM32 HAL. - NEW: Added support for SPI3 in the STM32 HAL.
- CHANGE: Redeclared the IRQ handlers in the various STM32 drivers using the
new friendly vector names.
- CHANGE: Removed the option -mabi=apcs-gnu from all the Cortex-Mx demos. The - CHANGE: Removed the option -mabi=apcs-gnu from all the Cortex-Mx demos. The
option is not compatible with the 64 bits stack alignment now default in option is not compatible with the 64 bits stack alignment now default in
the Cortex-Mx port. Note that the 64 bits alignment has a cost both as the Cortex-Mx port. Note that the 64 bits alignment has a cost both as
performance and as space but it is the "standard". performance and as space but it is the "standard".
- OPT: Small speed optimization in the STM32 SPI driver. - OPT: Small speed optimization in the STM32 SPI driver.
- OPT: Optimized DMA clearing in STM32 ADC and SPI drivers, there was no need
to read/modify/write the IFCR DMA register, it is write only.
- Fixed various documentation errors. - Fixed various documentation errors.
*** 2.1.0 *** *** 2.1.0 ***