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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14415 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

This commit is contained in:
Giovanni Di Sirio 2021-05-22 04:13:26 +00:00
parent acd06a0219
commit bb6bb85529
2 changed files with 28 additions and 12 deletions
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38
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -33,6 +33,14 @@
*/ */
#define STM32_WS_THRESHOLDS 5 #define STM32_WS_THRESHOLDS 5
/**
* @brief FLASH_ACR reset value.
*/
#define STM32_FLASH_ACR_RESET (FLASH_ACR_DBG_SWEN | \
FLASH_ACR_DCEN | \
FLASH_ACR_ICEN | \
FLASH_ACR_LATENCY_0WS)
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/
@ -57,8 +65,7 @@ const halclkcfg_t hal_clkcfg_reset = {
.rcc_cfgr = RCC_CFGR_SW_HSI, .rcc_cfgr = RCC_CFGR_SW_HSI,
.rcc_pllcfgr = 0U, .rcc_pllcfgr = 0U,
.rcc_crrcr = 0U, .rcc_crrcr = 0U,
.flash_acr = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | .flash_acr = STM32_FLASH_ACR_RESET
FLASH_ACR_ICEN | FLASH_ACR_LATENCY_0WS
}; };
/** /**
@ -206,6 +213,19 @@ static const system_limits_t vos_range2 = {
#include "stm32_bd.inc" #include "stm32_bd.inc"
/**
* @brief Safe setting of flash ACR register.
*
* @param[in] acr value for the ACR register
*/
static void flash_set_acr(uint32_t acr) {
FLASH->ACR = acr;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (acr & FLASH_ACR_LATENCY_Msk)) {
/* Waiting for flash wait states setup.*/
}
}
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__) #if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) || defined(__DOXYGEN__)
/** /**
* @brief Recalculates the clock tree frequencies. * @brief Recalculates the clock tree frequencies.
@ -459,10 +479,7 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
hsi16_reset(); hsi16_reset();
/* Resetting flash ACR settings to the default value.*/ /* Resetting flash ACR settings to the default value.*/
FLASH->ACR = 0x00040600U; flash_set_acr(STM32_FLASH_ACR_RESET);
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != 0U) {
/* Waiting for flash wait states setup.*/
}
/* Resetting all other clock sources and PLLs.*/ /* Resetting all other clock sources and PLLs.*/
RCC->CRRCR = 0U; RCC->CRRCR = 0U;
@ -503,7 +520,7 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
RCC->CFGR = (RCC->CFGR & RCC_CFGR_SW_Msk) | (ccp->rcc_cfgr & ~RCC_CFGR_SW_Msk); RCC->CFGR = (RCC->CFGR & RCC_CFGR_SW_Msk) | (ccp->rcc_cfgr & ~RCC_CFGR_SW_Msk);
/* Final flash ACR settings.*/ /* Final flash ACR settings.*/
FLASH->ACR = ccp->flash_acr; flash_set_acr(ccp->flash_acr);
/* Final PWR modes.*/ /* Final PWR modes.*/
PWR->CR1 = ccp->pwr_cr1; PWR->CR1 = ccp->pwr_cr1;
@ -689,11 +706,8 @@ void stm32_clock_init(void) {
RCC->CCIPR2 = STM32_QSPISEL | STM32_I2C4SEL; RCC->CCIPR2 = STM32_QSPISEL | STM32_I2C4SEL;
/* Set flash WS's for SYSCLK source.*/ /* Set flash WS's for SYSCLK source.*/
FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN | flash_set_acr(FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_PRFTEN | STM32_FLASHBITS; FLASH_ACR_PRFTEN | STM32_FLASHBITS;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
(STM32_FLASHBITS & FLASH_ACR_LATENCY_Msk)) {
}
/* Switching to the configured SYSCLK source if it is different from HSI16.*/ /* Switching to the configured SYSCLK source if it is different from HSI16.*/
#if STM32_SW != STM32_SW_HSI16 #if STM32_SW != STM32_SW_HSI16

2
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -132,6 +132,8 @@ const halclkcfg_t hal_clkcfg_default = {
/** /**
* @brief Safe setting of flash ACR register. * @brief Safe setting of flash ACR register.
*
* @param[in] acr value for the ACR register
*/ */
static void flash_set_acr(uint32_t acr) { static void flash_set_acr(uint32_t acr) {