From bbf9515ebbbe37b3835f382d8724c5888b303744 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 21 Dec 2010 19:51:33 +0000 Subject: [PATCH] Keil port and demo (working but not complete). git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2517 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt | 2007 +++++++++++++++++++++ demos/ARMCM3-STM32F103-GCC/keil/ch.uvproj | 1040 +++++++++++ os/ports/RVCT/ARMCMx/STM32/cmparams.h | 56 + os/ports/RVCT/ARMCMx/STM32/vectors.s | 305 ++++ os/ports/RVCT/ARMCMx/chcore.c | 45 + os/ports/RVCT/ARMCMx/chcore.h | 325 ++++ os/ports/RVCT/ARMCMx/chcore_v7m.c | 46 + os/ports/RVCT/ARMCMx/chcore_v7m.h | 252 +++ os/ports/RVCT/ARMCMx/chcoreasm_v7m.s | 134 ++ os/ports/RVCT/ARMCMx/chtypes.h | 80 + os/ports/RVCT/ARMCMx/cstartup.s | 109 ++ os/ports/RVCT/ARMCMx/nvic.c | 75 + os/ports/RVCT/ARMCMx/nvic.h | 192 ++ 13 files changed, 4666 insertions(+) create mode 100644 demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt create mode 100644 demos/ARMCM3-STM32F103-GCC/keil/ch.uvproj create mode 100644 os/ports/RVCT/ARMCMx/STM32/cmparams.h create mode 100644 os/ports/RVCT/ARMCMx/STM32/vectors.s create mode 100644 os/ports/RVCT/ARMCMx/chcore.c create mode 100644 os/ports/RVCT/ARMCMx/chcore.h create mode 100644 os/ports/RVCT/ARMCMx/chcore_v7m.c create mode 100644 os/ports/RVCT/ARMCMx/chcore_v7m.h create mode 100644 os/ports/RVCT/ARMCMx/chcoreasm_v7m.s create mode 100644 os/ports/RVCT/ARMCMx/chtypes.h create mode 100644 os/ports/RVCT/ARMCMx/cstartup.s create mode 100644 os/ports/RVCT/ARMCMx/nvic.c create mode 100644 os/ports/RVCT/ARMCMx/nvic.h diff --git a/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt new file mode 100644 index 000000000..2402a0bd6 --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvopt @@ -0,0 +1,2007 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvproj new file mode 100644 index 000000000..452c4255f --- /dev/null +++ b/demos/ARMCM3-STM32F103-GCC/keil/ch.uvproj @@ -0,0 +1,1040 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + STM32F103RB + STMicroelectronics + IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3") + + "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code") + UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000) + 4231 + stm32f10x_lib.h + + + + + + + + + + + 0 + + + + ST\STM32F10x\ + ST\STM32F10x\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMSTM.DLL + -pSTM32F103RB + SARMCM3.DLL + + TARMSTM.DLL + -pSTM32F103RB + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + STLink\ST-LINKIII-KEIL.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 1 + 0x8000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x5000 + + + 0 + 0x20005000 + 0x1 + + + + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base + + ..\..\ARMCM3-STM32F103-GCC;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\STM32;..\..\..\os\hal\include;..\..\..\os\hal\platforms\STM32;..\..\..\boards\OLIMEX_STM32_P103;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\boards\OLIMEX_STM32_P103;..\..\..\os\ports\RVCT\ARMCMx\STM32 + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\OLIMEX_STM32_P103\board.c + + + board.h + 5 + ..\..\..\boards\OLIMEX_STM32_P103\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\STM32\vectors.s + + + chcoreasm_v7m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v7m.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + chcore_v7m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.c + + + nvic.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chcore_v7m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v7m.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.h + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + + + platform + + + adc_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\adc_lld.c + + + can_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\can_lld.c + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\hal_lld.c + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pal_lld.c + + + pwm_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\pwm_lld.c + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\serial_lld.c + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\spi_lld.c + + + stm32_dma.c + 1 + ..\..\..\os\hal\platforms\STM32\stm32_dma.c + + + uart_lld.c + 1 + ..\..\..\os\hal\platforms\STM32\uart_lld.c + + + adc_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\adc_lld.h + + + can_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\can_lld.h + + + core_cm3.h + 5 + ..\..\..\os\hal\platforms\STM32\core_cm3.h + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\hal_lld.h + + + hal_lld_f103.h + 5 + ..\..\..\os\hal\platforms\STM32\hal_lld_f103.h + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pal_lld.h + + + pwm_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\pwm_lld.h + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\serial_lld.h + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\spi_lld.h + + + stm32_dma.h + 5 + ..\..\..\os\hal\platforms\STM32\stm32_dma.h + + + stm32f10x.h + 5 + ..\..\..\os\hal\platforms\STM32\stm32f10x.h + + + uart_lld.h + 5 + ..\..\..\os\hal\platforms\STM32\uart_lld.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + + + + + + diff --git a/os/ports/RVCT/ARMCMx/STM32/cmparams.h b/os/ports/RVCT/ARMCMx/STM32/cmparams.h new file mode 100644 index 000000000..de07b7c67 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32/cmparams.h @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/cmparams.h + * @brief ARM Cortex-M3 parameters for the STM32. + * + * @defgroup ARMCMx_STM32 STM32 Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M3 specific parameters for the + * STM32 platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL CORTEX_M3 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU FALSE + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/STM32/vectors.s b/os/ports/RVCT/ARMCMx/STM32/vectors.s new file mode 100644 index 000000000..1abf3cc1e --- /dev/null +++ b/os/ports/RVCT/ARMCMx/STM32/vectors.s @@ -0,0 +1,305 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \ + !defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \ + !defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \ + !defined(STM32F10X_CL) +#define _FROM_ASM_ +#include "board.h" +#endif + + PRESERVE8 + + AREA RESET, DATA, READONLY + + IMPORT __initial_msp + IMPORT Reset_Handler + EXPORT __Vectors + +__Vectors + DCD __initial_msp + DCD Reset_Handler + DCD NMIVector + DCD HardFaultVector + DCD MemManageVector + DCD BusFaultVector + DCD UsageFaultVector + DCD Vector1C + DCD Vector20 + DCD Vector24 + DCD Vector28 + DCD SVCallVector + DCD DebugMonitorVector + DCD Vector34 + DCD PendSVVector + DCD SysTickVector + DCD Vector40 + DCD Vector44 + DCD Vector48 + DCD Vector4C + DCD Vector50 + DCD Vector54 + DCD Vector58 + DCD Vector5C + DCD Vector60 + DCD Vector64 + DCD Vector68 + DCD Vector6C + DCD Vector70 + DCD Vector74 + DCD Vector78 + DCD Vector7C + DCD Vector80 + DCD Vector84 + DCD Vector88 + DCD Vector8C + DCD Vector90 + DCD Vector94 + DCD Vector98 + DCD Vector9C + DCD VectorA0 + DCD VectorA4 + DCD VectorA8 + DCD VectorAC + DCD VectorB0 + DCD VectorB4 + DCD VectorB8 + DCD VectorBC + DCD VectorC0 + DCD VectorC4 + DCD VectorC8 + DCD VectorCC + DCD VectorD0 + DCD VectorD4 + DCD VectorD8 + DCD VectorDC + DCD VectorE0 + DCD VectorE4 + DCD VectorE8 +#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \ + defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorEC + DCD VectorF0 + DCD VectorF4 +#endif +#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL) + DCD VectorF8 + DCD VectorFC + DCD Vector100 + DCD Vector104 + DCD Vector108 + DCD Vector10C + DCD Vector110 + DCD Vector114 + DCD Vector118 + DCD Vector11C + DCD Vector120 + DCD Vector124 + DCD Vector128 + DCD Vector12C +#endif +#if defined(STM32F10X_CL) + DCD Vector130 + DCD Vector134 + DCD Vector138 + DCD Vector13C + DCD Vector140 + DCD Vector144 + DCD Vector148 + DCD Vector14C +#endif + + AREA |.text|, CODE, READONLY + THUMB + +/* + * Default interrupt handlers. + */ + EXPORT _unhandled_exception +_unhandled_exception PROC + EXPORT NMIVector [WEAK] + EXPORT HardFaultVector [WEAK] + EXPORT MemManageVector [WEAK] + EXPORT BusFaultVector [WEAK] + EXPORT UsageFaultVector [WEAK] + EXPORT Vector1C [WEAK] + EXPORT Vector20 [WEAK] + EXPORT Vector24 [WEAK] + EXPORT Vector28 [WEAK] + EXPORT SVCallVector [WEAK] + EXPORT DebugMonitorVector [WEAK] + EXPORT Vector34 [WEAK] + EXPORT PendSVVector [WEAK] + EXPORT SysTickVector [WEAK] + EXPORT Vector40 [WEAK] + EXPORT Vector44 [WEAK] + EXPORT Vector48 [WEAK] + EXPORT Vector4C [WEAK] + EXPORT Vector50 [WEAK] + EXPORT Vector54 [WEAK] + EXPORT Vector58 [WEAK] + EXPORT Vector5C [WEAK] + EXPORT Vector60 [WEAK] + EXPORT Vector64 [WEAK] + EXPORT Vector68 [WEAK] + EXPORT Vector6C [WEAK] + EXPORT Vector70 [WEAK] + EXPORT Vector74 [WEAK] + EXPORT Vector78 [WEAK] + EXPORT Vector7C [WEAK] + EXPORT Vector80 [WEAK] + EXPORT Vector84 [WEAK] + EXPORT Vector88 [WEAK] + EXPORT Vector8C [WEAK] + EXPORT Vector90 [WEAK] + EXPORT Vector94 [WEAK] + EXPORT Vector98 [WEAK] + EXPORT Vector9C [WEAK] + EXPORT VectorA0 [WEAK] + EXPORT VectorA4 [WEAK] + EXPORT VectorA8 [WEAK] + EXPORT VectorAC [WEAK] + EXPORT VectorB0 [WEAK] + EXPORT VectorB4 [WEAK] + EXPORT VectorB8 [WEAK] + EXPORT VectorBC [WEAK] + EXPORT VectorC0 [WEAK] + EXPORT VectorC4 [WEAK] + EXPORT VectorC8 [WEAK] + EXPORT VectorCC [WEAK] + EXPORT VectorD0 [WEAK] + EXPORT VectorD4 [WEAK] + EXPORT VectorD8 [WEAK] + EXPORT VectorDC [WEAK] + EXPORT VectorE0 [WEAK] + EXPORT VectorE4 [WEAK] + EXPORT VectorE8 [WEAK] + EXPORT VectorEC [WEAK] + EXPORT VectorF0 [WEAK] + EXPORT VectorF4 [WEAK] + EXPORT VectorF8 [WEAK] + EXPORT VectorFC [WEAK] + EXPORT Vector100 [WEAK] + EXPORT Vector104 [WEAK] + EXPORT Vector108 [WEAK] + EXPORT Vector10C [WEAK] + EXPORT Vector110 [WEAK] + EXPORT Vector114 [WEAK] + EXPORT Vector118 [WEAK] + EXPORT Vector11C [WEAK] + EXPORT Vector120 [WEAK] + EXPORT Vector124 [WEAK] + EXPORT Vector128 [WEAK] + EXPORT Vector12C [WEAK] + EXPORT Vector130 [WEAK] + EXPORT Vector134 [WEAK] + EXPORT Vector138 [WEAK] + EXPORT Vector13C [WEAK] + EXPORT Vector140 [WEAK] + EXPORT Vector144 [WEAK] + EXPORT Vector148 [WEAK] + EXPORT Vector14C [WEAK] + +NMIVector +HardFaultVector +MemManageVector +BusFaultVector +UsageFaultVector +Vector1C +Vector20 +Vector24 +Vector28 +SVCallVector +DebugMonitorVector +Vector34 +PendSVVector +SysTickVector +Vector40 +Vector44 +Vector48 +Vector4C +Vector50 +Vector54 +Vector58 +Vector5C +Vector60 +Vector64 +Vector68 +Vector6C +Vector70 +Vector74 +Vector78 +Vector7C +Vector80 +Vector84 +Vector88 +Vector8C +Vector90 +Vector94 +Vector98 +Vector9C +VectorA0 +VectorA4 +VectorA8 +VectorAC +VectorB0 +VectorB4 +VectorB8 +VectorBC +VectorC0 +VectorC4 +VectorC8 +VectorCC +VectorD0 +VectorD4 +VectorD8 +VectorDC +VectorE0 +VectorE4 +VectorE8 +VectorEC +VectorF0 +VectorF4 +VectorF8 +VectorFC +Vector100 +Vector104 +Vector108 +Vector10C +Vector110 +Vector114 +Vector118 +Vector11C +Vector120 +Vector124 +Vector128 +Vector12C +Vector130 +Vector134 +Vector138 +Vector13C +Vector140 +Vector144 +Vector148 +Vector14C + b _unhandled_exception + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/chcore.c b/os/ports/RVCT/ARMCMx/chcore.c new file mode 100644 index 000000000..2f2122ae4 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore.c @@ -0,0 +1,45 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore.c + * @brief ARM Cortex-Mx port code. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief Halts the system. + * @note The function is declared as a weak symbol, it is possible + * to redefine it in your application code. + */ +#if !defined(__DOXYGEN__) +__weak +#endif +void port_halt(void) { + + port_disable(); + while (TRUE) { + } +} + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore.h b/os/ports/RVCT/ARMCMx/chcore.h new file mode 100644 index 000000000..d07d585a9 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore.h @@ -0,0 +1,325 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore.h + * @brief ARM Cortex-Mx port macros and structures. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +#include "nvic.h" + +/*===========================================================================*/ +/* Port constants. */ +/*===========================================================================*/ + +#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */ +#define CORTEX_M1 1 /**< @brief Cortex-M1 variant. */ +#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */ +#define CORTEX_M4 4 /**< @brief Cortex-M4 variant. */ + +/* Inclusion of the Cortex-Mx implementation specific parameters.*/ +#include "cmparams.h" + +/* Cortex model check, only M0 and M3 supported right now.*/ +#if (CORTEX_MODEL == CORTEX_M0) || (CORTEX_MODEL == CORTEX_M3) +#elif (CORTEX_MODEL == CORTEX_M1) || (CORTEX_MODEL == CORTEX_M4) +#warning "untested Cortex-M model" +#else +#error "unknown or unsupported Cortex-M model" +#endif + +/*===========================================================================*/ +/* Port statically derived parameters. */ +/*===========================================================================*/ + +/** + * @brief Total priority levels. + */ +#define CORTEX_PRIORITY_LEVELS (1 << CORTEX_PRIORITY_BITS) + +/** + * @brief Minimum priority level. + * @details This minimum priority level is calculated from the number of + * priority bits supported by the specific Cortex-Mx implementation. + */ +#define CORTEX_MINIMUM_PRIORITY (CORTEX_PRIORITY_LEVELS - 1) + +/** + * @brief Maximum priority level. + * @details The maximum allowed priority level is always zero. + */ +#define CORTEX_MAXIMUM_PRIORITY 0 + +/** + * @brief Disabled value for BASEPRI register. + * @note ARMv7-M architecture only. + */ +#define CORTEX_BASEPRI_DISABLED 0 + +/*===========================================================================*/ +/* Port macros. */ +/*===========================================================================*/ + +/** + * @brief Priority level verification macro. + */ +#define CORTEX_IS_VALID_PRIORITY(n) \ + (((n) >= 0) && ((n) < CORTEX_PRIORITY_LEVELS)) + +/** + * @brief Priority level to priority mask conversion macro. + */ +#define CORTEX_PRIORITY_MASK(n) \ + ((n) << (8 - CORTEX_PRIORITY_BITS)) + +/*===========================================================================*/ +/* Port configurable parameters. */ +/*===========================================================================*/ + +/** + * @brief Enables the use of the WFI instruction in the idle thread loop. + */ +#ifndef CORTEX_ENABLE_WFI_IDLE +#define CORTEX_ENABLE_WFI_IDLE FALSE +#endif + +/** + * @brief SYSTICK handler priority. + * @note The default SYSTICK handler priority is calculated as the priority + * level in the middle of the numeric priorities range. + */ +#ifndef CORTEX_PRIORITY_SYSTICK +#define CORTEX_PRIORITY_SYSTICK (CORTEX_PRIORITY_LEVELS >> 1) +#else +/* If it is externally redefined then better perform a validity check on it.*/ +#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SYSTICK) +#error "invalid priority level specified for CORTEX_PRIORITY_SYSTICK" +#endif +#endif + +/** + * @brief SVCALL handler priority. + * @note The default SVCALL handler priority is calculated as + * @p CORTEX_MAXIMUM_PRIORITY+1, in the ARMv7-M port this reserves + * the @p CORTEX_MAXIMUM_PRIORITY priority level as fast interrupts + * priority level. + * @note The SVCALL vector is only used in the ARMv7-M port, it is available + * to user in the ARMv6-M port. + */ +#ifndef CORTEX_PRIORITY_SVCALL +#define CORTEX_PRIORITY_SVCALL (CORTEX_MAXIMUM_PRIORITY + 1) +#else +/* If it is externally redefined then better perform a validity check on it.*/ +#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_SVCALL) +#error "invalid priority level specified for CORTEX_PRIORITY_SVCALL" +#endif +#endif + +/** + * @brief PENDSV handler priority. + * @note The default PENDSV handler priority is set at the + * @p CORTEX_MINIMUM_PRIORITY priority level. + * @note The PENDSV vector is only used in the ARMv7-M legacy port, it is + * available to user in the ARMv6-M and ARMv7-M ports. + * @note In the ARMv7-M legacy port this value should be not changed from + * the minimum priority level. + */ +#ifndef CORTEX_PRIORITY_PENDSV +#define CORTEX_PRIORITY_PENDSV CORTEX_MINIMUM_PRIORITY +#else +/* If it is externally redefined then better perform a validity check on it.*/ +#if !CORTEX_IS_VALID_PRIORITY(CORTEX_PRIORITY_PENDSV) +#error "invalid priority level specified for CORTEX_PRIORITY_PENDSV" +#endif +#endif + +/** + * @brief BASEPRI level within kernel lock. + * @note This value must not mask the SVCALL priority level or the + * kernel would hard fault. + * @note ARMv7-M architecture only. + */ +#ifndef CORTEX_BASEPRI_KERNEL +#define CORTEX_BASEPRI_KERNEL \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) +#endif + +/** + * @brief Stack alignment enforcement. + * @note The default value is 64 in order to comply with EABI, reducing + * the value to 32 can save some RAM space if you don't care about + * binary compatibility with EABI compiled libraries. + * @note Allowed values are 32 or 64. + */ +#ifndef CORTEX_STACK_ALIGNMENT +#define CORTEX_STACK_ALIGNMENT 64 +#endif + +/*===========================================================================*/ +/* Port exported info. */ +/*===========================================================================*/ + +/** + * @brief Macro defining a generic ARM architecture. + */ +#define CH_ARCHITECTURE_ARM + +#if defined(__DOXYGEN__) +/** + * @brief Macro defining the specific ARM architecture. + * @note This macro is for documentation only, the real name changes + * depending on the selected architecture, the possible names are: + * - CH_ARCHITECTURE_ARM_v6M. + * - CH_ARCHITECTURE_ARM_v7M. + * . + */ +#define CH_ARCHITECTURE_ARM_vxm + +/** + * @brief Name of the implemented architecture. + * @note The value is for documentation only, the real value changes + * depending on the selected architecture, the possible values are: + * - "ARMv6-M". + * - "ARMv7-M". + * - "ARMv7-ME". + * . + */ +#define CH_ARCHITECTURE_NAME "ARMvx-M" + +/** + * @brief Name of the architecture variant (optional). + * @note The value is for documentation only, the real value changes + * depending on the selected architecture, the possible values are: + * - "Cortex-M0" + * - "Cortex-M1" + * - "Cortex-M3" + * - "Cortex-M4" + * . + */ +#define CH_CORE_VARIANT_NAME "Cortex-Mx" + +#elif CORTEX_MODEL == CORTEX_M4 +#define CH_ARCHITECTURE_ARM_v7M +#define CH_ARCHITECTURE_NAME "ARMv7-ME" +#define CH_CORE_VARIANT_NAME "Cortex-M4" +#elif CORTEX_MODEL == CORTEX_M3 +#define CH_ARCHITECTURE_ARM_v7M +#define CH_ARCHITECTURE_NAME "ARMv7-M" +#define CH_CORE_VARIANT_NAME "Cortex-M3" +#elif CORTEX_MODEL == CORTEX_M1 +#define CH_ARCHITECTURE_ARM_v6M +#define CH_ARCHITECTURE_NAME "ARMv6-M" +#define CH_CORE_VARIANT_NAME "Cortex-M1" +#elif CORTEX_MODEL == CORTEX_M0 +#define CH_ARCHITECTURE_ARM_v6M +#define CH_ARCHITECTURE_NAME "ARMv6-M" +#define CH_CORE_VARIANT_NAME "Cortex-M0" +#endif + +/*===========================================================================*/ +/* Port implementation part (common). */ +/*===========================================================================*/ + +/** + * @brief Stack and memory alignment enforcement. + */ +#if (CORTEX_STACK_ALIGNMENT == 64) || defined(__DOXYGEN__) +#if defined(__DOXYGEN__) +/* Dummy declaration, for Doxygen only.*/ +typedef uint64_t stkalign_t; +#else +typedef uint64_t stkalign_t __attribute__ ((aligned (8))); +#endif +#elif CORTEX_STACK_ALIGNMENT == 32 +typedef uint32_t stkalign_t __attribute__ ((aligned (4))); +#else +#error "invalid stack alignment selected" +#endif + +/** + * @brief Generic ARM register. + */ +typedef void *regarm_t; + +#if defined(__DOXYGEN__) +/** + * @brief Interrupt saved context. + * @details This structure represents the stack frame saved during a + * preemption-capable interrupt handler. + * @note It is implemented to match the Cortex-Mx exception context. + */ +struct extctx { + /* Dummy definition, just for Doxygen.*/ +}; + +/** + * @brief System saved context. + * @details This structure represents the inner stack frame during a context + * switching. + */ +struct intctx { + /* Dummy definition, just for Doxygen.*/ +}; +#endif + +/** + * @brief Platform dependent part of the @p Thread structure. + * @details In this port the structure just holds a pointer to the @p intctx + * structure representing the stack pointer at context switch time. + */ +struct context { + struct intctx *r13; +}; + +/** + * @brief Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1) + +/** + * @brief Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (INT_REQUIRED_STACK)) + +/** + * @brief Static working area allocation. + * @details This macro is used to allocate a static thread working area + * aligned as both position and size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)] + +/* Includes the architecture-specific implementation part.*/ +#if defined(CH_ARCHITECTURE_ARM_v6M) +#include "chcore_v6m.h" +#elif defined(CH_ARCHITECTURE_ARM_v7M) +#include "chcore_v7m.h" +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.c b/os/ports/RVCT/ARMCMx/chcore_v7m.c new file mode 100644 index 000000000..fe267b9e9 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.c @@ -0,0 +1,46 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore_v7m.c + * @brief ARMv7-M architecture port code. + * + * @addtogroup IAR_ARMCMx_V7M_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h new file mode 100644 index 000000000..57b18f980 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -0,0 +1,252 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chcore_v7m.h + * @brief ARMv7-M architecture port macros and structures. + * + * @addtogroup IAR_ARMCMx_V7M_CORE + * @{ + */ + +#ifndef _CHCORE_V7M_H_ +#define _CHCORE_V7M_H_ + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +struct extctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +struct intctx { + regarm_t r4; + regarm_t r5; + regarm_t r6; +#ifndef CH_CURRP_REGISTER_CACHE + regarm_t r7; +#endif + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; +}; +#endif + +/** + * @brief Platform dependent part of the @p chThdCreateI() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (void *)pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = (void *)_port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p INT_REQUIRED_STACK. + * @note In this port it is set to 8 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#ifndef IDLE_THREAD_STACK_SIZE +#define IDLE_THREAD_STACK_SIZE 8 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 16 because the function + * @p chSchDoRescheduleI() can have a stack frame, expecially with + * compiler optimizations disabled. + */ +#ifndef INT_REQUIRED_STACK +#define INT_REQUIRED_STACK 16 +#endif + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + NVICSetSystemHandlerPriority(HANDLER_SVCALL, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL)); \ + NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it raises the base priority to kernel level. + */ +#define port_lock() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_KERNEL; \ +} + +/** + * @brief Kernel-unlock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + * @note In this port this it lowers the base priority to user level. + */ +#define port_unlock() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_DISABLED; \ +} + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_unlock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + * @note Of course non maskable interrupt sources are not included. + * @note In this port it disables all the interrupt sources by raising + * the priority mask to level 0. + */ +#define port_disable() __disable_irq() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + * @note Interrupt sources above kernel level remains enabled. + * @note In this port it raises/lowers the base priority to kernel level. + */ +#define port_suspend() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_KERNEL; \ + __enable_irq(); \ +} + +/** + * @brief Enables all the interrupt sources. + * @note In this port it lowers the base priority to user level. + */ +#define port_enable() { \ + register uint32_t basepri __asm("basepri"); \ + basepri = CORTEX_BASEPRI_DISABLED; \ + __enable_irq(); \ +} + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() __wfi() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#define port_switch(ntp, otp) _port_switch(ntp, otp) + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_V7M_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s new file mode 100644 index 000000000..1e00ccea3 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s @@ -0,0 +1,134 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Imports the Cortex-Mx parameters header and performs the same calculations + * done in chcore.h. + */ +#include "cmparams.h" + +#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS)) + +#ifndef CORTEX_PRIORITY_SVCALL +#define CORTEX_PRIORITY_SVCALL 1 +#endif + +#ifndef CORTEX_BASEPRI_KERNEL +#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL+1) +#endif + +#define CORTEX_BASEPRI_DISABLED 0 + +EXTCTX_SIZE EQU 32 +CONTEXT_OFFSET EQU 12 +SCB_ICSR EQU 0xE000ED04 +ICSR_RETTOBASE EQU 0x00000800 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchIsRescRequiredExI + IMPORT chSchDoRescheduleI + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, r8, r9, r10, r11, lr} + str sp, [r1, #CONTEXT_OFFSET] + ldr sp, [r0, #CONTEXT_OFFSET] + pop {r4, r5, r6, r7, r8, r9, r10, r11, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 + mov r0, r5 + blx r4 + bl chThdExit + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr +_port_switch_from_isr PROC + bl chSchDoRescheduleI + svc #0 + ENDP + +/* + * Reschedule verification and setup after an IRQ. + */ + EXPORT _port_irq_epilogue +_port_irq_epilogue PROC + movs r3, #CORTEX_BASEPRI_KERNEL + msr BASEPRI, r3 + mov r3, #SCB_ICSR :AND: 0xFFFF + movt r3, #SCB_ICSR :SHR: 16 + ldr r3, [r3, #0] + tst r3, #ICSR_RETTOBASE + bne skipexit + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 + bx lr +skipexit + push {r3, lr} + bl chSchIsRescRequiredExI + cmp r0, #0 + beq noreschedule + mrs r3, PSP + subs r3, r3, #EXTCTX_SIZE + msr PSP, r3 + ldr r2, =_port_switch_from_isr + str r2, [r3, #24] + mov r2, #0x01000000 + str r2, [r3, #28] + pop {r3, pc} +noreschedule + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 + pop {r3, pc} + ENDP + +/* + * SVC vector. + * Discarding the current exception context and positioning the stack to + * point to the real one. + */ + EXPORT SVCallVector +SVCallVector PROC + mrs r3, PSP + adds r3, r3, #EXTCTX_SIZE + msr PSP, r3 + movs r3, #CORTEX_BASEPRI_DISABLED + msr BASEPRI, r3 + bx lr + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/chtypes.h b/os/ports/RVCT/ARMCMx/chtypes.h new file mode 100644 index 000000000..3386f5d4b --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chtypes.h @@ -0,0 +1,80 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/chtypes.h + * @brief ARM Cortex-Mx port system types. + * + * @addtogroup IAR_ARMCMx_CORE + * @{ + */ + +#ifndef _CHTYPES_H_ +#define _CHTYPES_H_ + +#define __need_NULL +#define __need_size_t +#define __need_ptrdiff_t +#include + +#include + +typedef int32_t bool_t; /**< Fast boolean type. */ +typedef uint8_t tmode_t; /**< Thread flags. */ +typedef uint8_t tstate_t; /**< Thread state. */ +typedef uint8_t trefs_t; /**< Thread references counter. */ +typedef uint32_t tprio_t; /**< Thread priority. */ +typedef int32_t msg_t; /**< Inter-thread message. */ +typedef int32_t eventid_t; /**< Event Id. */ +typedef uint32_t eventmask_t; /**< Events mask. */ +typedef uint32_t systime_t; /**< System time. */ +typedef int32_t cnt_t; /**< Resources counter. */ + +/** + * @brief Inline function modifier. + */ +#define INLINE __inline + +/** + * @brief ROM constant modifier. + * @note It is set to use the "const" keyword in this port. + */ +#define ROMCONST const + +/** + * @brief Packed structure modifier (within). + * @note It uses the "packed" GCC attribute. + */ +#define PACK_STRUCT_STRUCT __attribute__((packed)) + +/** + * @brief Packed structure modifier (before). + * @note Empty in this port. + */ +#define PACK_STRUCT_BEGIN + +/** + * @brief Packed structure modifier (after). + * @note Empty in this port. + */ +#define PACK_STRUCT_END + +#endif /* _CHTYPES_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/cstartup.s b/os/ports/RVCT/ARMCMx/cstartup.s new file mode 100644 index 000000000..95a39e831 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/cstartup.s @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +;/* <<< Use Configuration Wizard in Context Menu >>> */ + +;// Main Stack Configuration +;// Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +main_stack_size EQU 0x00000400 + +;// Process Stack Configuration +;// Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +proc_stack_size EQU 0x00000400 + +;// C-runtime heap size +;// C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8> +;// +heap_size EQU 0x00000400 + + AREA MSTACK, NOINIT, READWRITE, ALIGN=3 +main_stack_mem SPACE main_stack_size + EXPORT __initial_msp +__initial_msp + + AREA CSTACK, NOINIT, READWRITE, ALIGN=3 +proc_stack_mem SPACE proc_stack_size + EXPORT __initial_sp +__initial_sp + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE heap_size +__heap_limit + +CONTROL_MODE_PRIVILEGED EQU 0 +CONTROL_MODE_UNPRIVILEGED EQU 1 +CONTROL_USE_MSP EQU 0 +CONTROL_USE_PSP EQU 2 + + PRESERVE8 + THUMB + + AREA |.text|, CODE, READONLY + +/* + * Reset handler. + */ + IMPORT __main + EXPORT Reset_Handler +Reset_Handler PROC + cpsid i + ldr r0, =__initial_sp + msr PSP, r0 + movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP + msr CONTROL, r0 + isb + bl __early_init + b __main + ENDP + +__early_init PROC + EXPORT __early_init [WEAK] + bx lr + ENDP + + ALIGN + +/* + * User Initial Stack & Heap. + */ + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + ldr r0, =Heap_Mem + ldr r1, =(proc_stack_mem + proc_stack_size) + ldr r2, =(Heap_Mem + heap_size) + ldr r3, =proc_stack_mem + bx lr + + ALIGN + + ENDIF + + END diff --git a/os/ports/RVCT/ARMCMx/nvic.c b/os/ports/RVCT/ARMCMx/nvic.c new file mode 100644 index 000000000..93dbd6ba4 --- /dev/null +++ b/os/ports/RVCT/ARMCMx/nvic.c @@ -0,0 +1,75 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/nvic.c + * @brief Cortex-Mx NVIC support code. + * + * @addtogroup IAR_ARMCMx_NVIC + * @{ + */ + +#include "ch.h" +#include "nvic.h" + +/** + * @brief Sets the priority of an interrupt handler and enables it. + * + * @param n the interrupt number + * @param prio the interrupt priority mask + * + * @note The parameters are not tested for correctness. + */ +void NVICEnableVector(uint32_t n, uint32_t prio) { + unsigned sh = (n & 3) << 3; + + NVIC_IPR(n >> 2) = (NVIC_IPR(n >> 2) & ~(0xFF << sh)) | (prio << sh); + NVIC_ICPR(n >> 5) = 1 << (n & 0x1F); + NVIC_ISER(n >> 5) = 1 << (n & 0x1F); +} + +/** + * @brief Disables an interrupt handler. + * + * @param n the interrupt number + * + * @note The parameters are not tested for correctness. + */ +void NVICDisableVector(uint32_t n) { + unsigned sh = (n & 3) << 3; + + NVIC_ICER(n >> 5) = 1 << (n & 0x1F); + NVIC_IPR(n >> 2) = NVIC_IPR(n >> 2) & ~(0xFF << sh); +} + +/** + * @brief Changes the priority of a system handler. + * + * @param handler the system handler number + * @param prio the system handler priority mask + * @note The parameters are not tested for correctness. + */ +void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio) { + unsigned sh = (handler & 3) * 8; + + SCB_SHPR(handler >> 2) = (SCB_SHPR(handler >> 2) & + ~(0xFF << sh)) | (prio << sh); +} + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/nvic.h b/os/ports/RVCT/ARMCMx/nvic.h new file mode 100644 index 000000000..321a0ed7b --- /dev/null +++ b/os/ports/RVCT/ARMCMx/nvic.h @@ -0,0 +1,192 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file IAR/ARMCMx/nvic.h + * @brief Cortex-Mx NVIC support macros and structures. + * + * @addtogroup IAR_ARMCMx_NVIC + * @{ + */ + +#ifndef _NVIC_H_ +#define _NVIC_H_ + +/* + * System vector constants for @p NVICSetSystemHandlerPriority(). + */ +#define HANDLER_MEM_MANAGE 0 /**< MEM MANAGE vector id. */ +#define HANDLER_BUS_FAULT 1 /**< BUS FAULT vector id. */ +#define HANDLER_USAGE_FAULT 2 /**< USAGE FAULT vector id. */ +#define HANDLER_RESERVED_3 3 +#define HANDLER_RESERVED_4 4 +#define HANDLER_RESERVED_5 5 +#define HANDLER_RESERVED_6 6 +#define HANDLER_SVCALL 7 /**< SVCALL vector id. */ +#define HANDLER_DEBUG_MONITOR 8 /**< DEBUG MONITOR vector id. */ +#define HANDLER_RESERVED_9 9 +#define HANDLER_PENDSV 10 /**< PENDSV vector id. */ +#define HANDLER_SYSTICK 11 /**< SYS TCK vector id. */ + +typedef volatile uint8_t IOREG8; /**< 8 bits I/O register type. */ +typedef volatile uint32_t IOREG32; /**< 32 bits I/O register type. */ + +/** + * @brief NVIC ITCR register. + */ +#define NVIC_ITCR (*((IOREG32 *)0xE000E004)) + +/** + * @brief NVIC STIR register. + */ +#define NVIC_STIR (*((IOREG32 *)0xE000EF00)) + +/** + * @brief Structure representing the SYSTICK I/O space. + */ +typedef struct { + IOREG32 CSR; + IOREG32 RVR; + IOREG32 CVR; + IOREG32 CBVR; +} CM3_ST; + +/** + * @brief SYSTICK peripheral base address. + */ +#define STBase ((CM3_ST *)0xE000E010) +#define ST_CSR (STBase->CSR) +#define ST_RVR (STBase->RVR) +#define ST_CVR (STBase->CVR) +#define ST_CBVR (STBase->CBVR) + +#define CSR_ENABLE_MASK (0x1 << 0) +#define ENABLE_OFF_BITS (0 << 0) +#define ENABLE_ON_BITS (1 << 0) +#define CSR_TICKINT_MASK (0x1 << 1) +#define TICKINT_DISABLED_BITS (0 << 1) +#define TICKINT_ENABLED_BITS (1 << 1) +#define CSR_CLKSOURCE_MASK (0x1 << 2) +#define CLKSOURCE_EXT_BITS (0 << 2) +#define CLKSOURCE_CORE_BITS (1 << 2) +#define CSR_COUNTFLAG_MASK (0x1 << 16) + +#define RVR_RELOAD_MASK (0xFFFFFF << 0) + +#define CVR_CURRENT_MASK (0xFFFFFF << 0) + +#define CBVR_TENMS_MASK (0xFFFFFF << 0) +#define CBVR_SKEW_MASK (0x1 << 30) +#define CBVR_NOREF_MASK (0x1 << 31) + +/** + * @brief Structure representing the NVIC I/O space. + */ +typedef struct { + IOREG32 ISER[8]; + IOREG32 unused1[24]; + IOREG32 ICER[8]; + IOREG32 unused2[24]; + IOREG32 ISPR[8]; + IOREG32 unused3[24]; + IOREG32 ICPR[8]; + IOREG32 unused4[24]; + IOREG32 IABR[8]; + IOREG32 unused5[56]; + IOREG32 IPR[60]; +} CM3_NVIC; + +/** + * @brief NVIC peripheral base address. + */ +#define NVICBase ((CM3_NVIC *)0xE000E100) +#define NVIC_ISER(n) (NVICBase->ISER[n]) +#define NVIC_ICER(n) (NVICBase->ICER[n]) +#define NVIC_ISPR(n) (NVICBase->ISPR[n]) +#define NVIC_ICPR(n) (NVICBase->ICPR[n]) +#define NVIC_IABR(n) (NVICBase->IABR[n]) +#define NVIC_IPR(n) (NVICBase->IPR[n]) + +/** + * @brief Structure representing the System Control Block I/O space. + */ +typedef struct { + IOREG32 CPUID; + IOREG32 ICSR; + IOREG32 VTOR; + IOREG32 AIRCR; + IOREG32 SCR; + IOREG32 CCR; + IOREG32 SHPR[3]; + IOREG32 SHCSR; + IOREG32 CFSR; + IOREG32 HFSR; + IOREG32 DFSR; + IOREG32 MMFAR; + IOREG32 BFAR; + IOREG32 AFSR; +} CM3_SCB; + +/** + * @brief SCB peripheral base address. + */ +#define SCBBase ((CM3_SCB *)0xE000ED00) +#define SCB_CPUID (SCBBase->CPUID) +#define SCB_ICSR (SCBBase->ICSR) +#define SCB_VTOR (SCBBase->VTOR) +#define SCB_AIRCR (SCBBase->AIRCR) +#define SCB_SCR (SCBBase->SCR) +#define SCB_CCR (SCBBase->CCR) +#define SCB_SHPR(n) (SCBBase->SHPR[n]) +#define SCB_SHCSR (SCBBase->SHCSR) +#define SCB_CFSR (SCBBase->CFSR) +#define SCB_HFSR (SCBBase->HFSR) +#define SCB_DFSR (SCBBase->DFSR) +#define SCB_MMFAR (SCBBase->MMFAR) +#define SCB_BFAR (SCBBase->BFAR) +#define SCB_AFSR (SCBBase->AFSR) + +#define ICSR_VECTACTIVE_MASK (0x1FF << 0) +#define ICSR_RETTOBASE (0x1 << 11) +#define ICSR_VECTPENDING_MASK (0x1FF << 12) +#define ICSR_ISRPENDING (0x1 << 22) +#define ICSR_ISRPREEMPT (0x1 << 23) +#define ICSR_PENDSTCLR (0x1 << 25) +#define ICSR_PENDSTSET (0x1 << 26) +#define ICSR_PENDSVCLR (0x1 << 27) +#define ICSR_PENDSVSET (0x1 << 28) +#define ICSR_NMIPENDSET (0x1 << 31) + +#define AIRCR_VECTKEY 0x05FA0000 +#define AIRCR_PRIGROUP_MASK (0x7 << 8) +#define AIRCR_PRIGROUP(n) ((n) << 8) + +#ifdef __cplusplus +extern "C" { +#endif + void NVICEnableVector(uint32_t n, uint32_t prio); + void NVICDisableVector(uint32_t n); + void NVICSetSystemHandlerPriority(uint32_t handler, uint32_t prio); +#ifdef __cplusplus +} +#endif + +#endif /* _NVIC_H_ */ + +/** @} */