Fixed TIMPRE behavior.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12059 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
parent
ed72edd29f
commit
bc6b6552fe
|
@ -221,8 +221,8 @@
|
|||
#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
|
||||
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
|
||||
(STM32_PPRE1 == STM32_PPRE1_DIV2) || \
|
||||
(STM32_PPRE1 == STM32_PPRE1_DIV4) || \
|
||||
defined(__DOXYGEN__)
|
||||
((STM32_PPRE1 == STM32_PPRE1_DIV4) && \
|
||||
(STM32_TIMPRE_PRESCALE4 == TRUE)) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK1 STM32_HCLK
|
||||
#else
|
||||
#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
|
||||
|
@ -230,8 +230,8 @@
|
|||
|
||||
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
|
||||
(STM32_PPRE2 == STM32_PPRE2_DIV2) || \
|
||||
(STM32_PPRE2 == STM32_PPRE2_DIV4) || \
|
||||
defined(__DOXYGEN__)
|
||||
((STM32_PPRE2 == STM32_PPRE2_DIV4) && \
|
||||
(STM32_TIMPRE_PRESCALE4 == TRUE)) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK2 STM32_HCLK
|
||||
#else
|
||||
#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
|
||||
|
|
|
@ -92,12 +92,13 @@
|
|||
/* Clock tree attributes.*/
|
||||
#define STM32_HAS_RCC_PLLSAI TRUE
|
||||
#define STM32_HAS_RCC_PLLI2S TRUE
|
||||
#define STM32_HAS_RCC_DCKCFGR TRU§E
|
||||
#define STM32_HAS_RCC_DCKCFGR TRUE
|
||||
#define STM32_HAS_RCC_DCKCFGR2 FALSE
|
||||
#define STM32_HAS_RCC_I2SSRC TRUE
|
||||
#define STM32_HAS_RCC_I2SPLLSRC FALSE
|
||||
#define STM32_HAS_RCC_CK48MSEL TRUE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S FALSE
|
||||
#define STM32_TIMPRE_PRESCALE4 FALSE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -479,6 +480,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC FALSE
|
||||
#define STM32_HAS_RCC_CK48MSEL TRUE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S FALSE
|
||||
#define STM32_TIMPRE_PRESCALE4 FALSE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -837,6 +839,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC FALSE
|
||||
#define STM32_HAS_RCC_CK48MSEL FALSE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S FALSE
|
||||
#define STM32_TIMPRE_PRESCALE4 FALSE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -1214,6 +1217,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC TRUE
|
||||
#define STM32_HAS_RCC_CK48MSEL TRUE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S TRUE
|
||||
#define STM32_TIMPRE_PRESCALE4 TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -1603,6 +1607,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC TRUE
|
||||
#define STM32_HAS_RCC_CK48MSEL TRUE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S TRUE
|
||||
#define STM32_TIMPRE_PRESCALE4 TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -1937,6 +1942,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC FALSE
|
||||
#define STM32_HAS_RCC_CK48MSEL FALSE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S FALSE
|
||||
#define STM32_TIMPRE_PRESCALE4 TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -2247,6 +2253,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC FALSE
|
||||
#define STM32_HAS_RCC_CK48MSEL FALSE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S FALSE
|
||||
#define STM32_TIMPRE_PRESCALE4 TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -2527,6 +2534,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC FALSE
|
||||
#define STM32_HAS_RCC_CK48MSEL FALSE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S FALSE
|
||||
#define STM32_TIMPRE_PRESCALE4 FALSE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
@ -2880,6 +2888,7 @@
|
|||
#define STM32_HAS_RCC_I2SPLLSRC FALSE
|
||||
#define STM32_HAS_RCC_CK48MSEL FALSE
|
||||
#define STM32_RCC_CK48MSEL_USES_I2S FALSE
|
||||
#define STM32_TIMPRE_PRESCALE4 TRUE
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_ADC_HANDLER Vector88
|
||||
|
|
Loading…
Reference in New Issue