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G4 demo now working. Improved assertions in USARTv2 driver. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13035 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2019-09-28 11:23:36 +00:00
parent b5ec31f16e
commit bcc03038e5
11 changed files with 181 additions and 163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
demos/STM32/RT-STM32G431RB-NUCLEO64/Makefile
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@ -101,7 +101,7 @@ include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32g4xx.m
# HAL-OSAL files (optional). # HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/platform.mk include $(CHIBIOS)/os/hal/ports/STM32/STM32G4xx/platform.mk
include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G474RE/board.mk include $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_G431RB/board.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional). # RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk include $(CHIBIOS)/os/rt/rt.mk
@ -114,7 +114,7 @@ include $(CHIBIOS)/test/rt/rt_test.mk
include $(CHIBIOS)/test/oslib/oslib_test.mk include $(CHIBIOS)/test/oslib/oslib_test.mk
# Define linker script file here # Define linker script file here
LDSCRIPT= $(STARTUPLD)/STM32G474xE.ld LDSCRIPT= $(STARTUPLD)/STM32G431xB.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global # C sources that can be compiled in ARM or THUMB mode depending on the global
# setting. # setting.

14
demos/STM32/RT-STM32G431RB-NUCLEO64/cfg/mcuconf.h
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@ -58,7 +58,7 @@
#define STM32_PLLQ_VALUE 8 #define STM32_PLLQ_VALUE 8
#define STM32_PLLR_VALUE 2 #define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1 #define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@ -72,12 +72,12 @@
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK #define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK #define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK #define STM32_UART5SEL STM32_UART5SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK #define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK #define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK #define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK #define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK #define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK #define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK #define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
#define STM32_FDCANSEL STM32_FDCANSEL_HSE #define STM32_FDCANSEL STM32_FDCANSEL_HSE

2
demos/STM32/RT-STM32G431RB-NUCLEO64/main.c
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@ -65,7 +65,7 @@ int main(void) {
* sleeping in a loop and check the button state. * sleeping in a loop and check the button state.
*/ */
while (true) { while (true) {
if (!palReadLine(LINE_BUTTON)) { if (palReadLine(LINE_BUTTON)) {
test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite); test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite);
test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite); test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite);
} }

14
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
View File

@ -58,7 +58,7 @@
#define STM32_PLLQ_VALUE 8 #define STM32_PLLQ_VALUE 8
#define STM32_PLLR_VALUE 2 #define STM32_PLLR_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1 #define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@ -72,12 +72,12 @@
#define STM32_USART3SEL STM32_USART3SEL_SYSCLK #define STM32_USART3SEL STM32_USART3SEL_SYSCLK
#define STM32_UART4SEL STM32_UART4SEL_SYSCLK #define STM32_UART4SEL STM32_UART4SEL_SYSCLK
#define STM32_UART5SEL STM32_UART5SEL_SYSCLK #define STM32_UART5SEL STM32_UART5SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK #define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK #define STM32_I2C1SEL STM32_I2C1SEL_PCLK1
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK #define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK #define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK #define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK #define STM32_SAI1SEL STM32_SAI1SEL_SYSCLK
#define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK #define STM32_I2S23SEL STM32_I2S23SEL_SYSCLK
#define STM32_FDCANSEL STM32_FDCANSEL_HSE #define STM32_FDCANSEL STM32_FDCANSEL_HSE

2
demos/STM32/RT-STM32G474RE-NUCLEO64/debug/RT-STM32G474RE-NUCLEO64 (OpenOCD, Flash and Run).launch
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@ -33,7 +33,7 @@
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList/&gt;"/> <stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;contentList&gt;&lt;content id=&quot;brr-usart_init-(format)&quot; val=&quot;4&quot;/&gt;&lt;/contentList&gt;"/>
<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/> <stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;globalVariableList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList/&gt;&#10;"/> <stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList/&gt;&#10;"/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>

149
demos/STM32/RT-STM32G474RE-NUCLEO64/main.c
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@ -1,74 +1,75 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
You may obtain a copy of the License at You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0 http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and See the License for the specific language governing permissions and
limitations under the License. limitations under the License.
*/ */
#include "ch.h" #include "ch.h"
#include "hal.h" #include "hal.h"
#include "rt_test_root.h" #include "rt_test_root.h"
#include "oslib_test_root.h" #include "oslib_test_root.h"
/* /*
* Green LED blinker thread, times are in milliseconds. * Green LED blinker thread, times are in milliseconds.
*/ */
static THD_WORKING_AREA(waThread1, 128); static THD_WORKING_AREA(waThread1, 128);
static THD_FUNCTION(Thread1, arg) { static THD_FUNCTION(Thread1, arg) {
(void)arg; (void)arg;
chRegSetThreadName("blinker"); chRegSetThreadName("blinker");
while (true) { while (true) {
palClearLine(LINE_LED_GREEN); palClearLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
palSetLine(LINE_LED_GREEN); palSetLine(LINE_LED_GREEN);
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
} }
} }
/* /*
* Application entry point. * Application entry point.
*/ */
int main(void) { int main(void) {
/* /*
* System initializations. * System initializations.
* - HAL initialization, this also initializes the configured device drivers * - HAL initialization, this also initializes the configured device drivers
* and performs the board-specific initializations. * and performs the board-specific initializations.
* - Kernel initialization, the main() function becomes a thread and the * - Kernel initialization, the main() function becomes a thread and the
* RTOS is active. * RTOS is active.
*/ */
halInit(); halInit();
chSysInit(); chSysInit();
/* /*
* Activates the serial driver 2 using the driver default configuration. * Activates the serial driver 2 using the driver default configuration.
*/ */
sdStart(&LPSD1, NULL); sdStart(&LPSD1, NULL);
/* /*
* Creates the blinker thread. * Creates the blinker thread.
*/ */
chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
/* /*
* Normal main() thread activity, in this demo it does nothing except * Normal main() thread activity, in this demo it does nothing except
* sleeping in a loop and check the button state. * sleeping in a loop and check the button state.
*/ */
while (true) { while (true) {
if (!palReadLine(LINE_BUTTON)) { if (palReadLine(LINE_BUTTON)) {
test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite); test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite);
test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite); test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite);
} }
chThdSleepMilliseconds(500); chThdSleepMilliseconds(500);
} }
} }

28
os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
View File

@ -230,26 +230,34 @@ static uint8_t sd_out_buflp1[STM32_SERIAL_LPUART1_OUT_BUF_SIZE];
* @param[in] config the architecture-dependent serial driver configuration * @param[in] config the architecture-dependent serial driver configuration
*/ */
static void usart_init(SerialDriver *sdp, const SerialConfig *config) { static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
uint32_t fck; uint32_t brr;
USART_TypeDef *u = sdp->usart; USART_TypeDef *u = sdp->usart;
/* Baud rate setting.*/ /* Baud rate setting.*/
#if STM32_SERIAL_USE_LPUART1 #if STM32_SERIAL_USE_LPUART1
if (sdp == &LPSD1) { if (sdp == &LPSD1) {
fck = (uint32_t)(((uint64_t)sdp->clock * 256) / config->speed); osalDbgAssert((sdp->clock >= config->speed * 3U) &&
(sdp->clock <= config->speed * 4096U),
"invalid baud rate vs input clock");
brr = (uint32_t)(((uint64_t)sdp->clock * 256) / config->speed);
osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value");
} }
else else
#endif #endif
{ {
fck = (uint32_t)(sdp->clock / config->speed); brr = (uint32_t)(sdp->clock / config->speed);
}
/* Correcting USARTDIV when oversampling by 8 instead of 16. /* Correcting BRR value when oversampling by 8 instead of 16.
Fraction is still 4 bits wide, but only lower 3 bits used. Fraction is still 4 bits wide, but only lower 3 bits used.
Mantissa is doubled, but Fraction is left the same.*/ Mantissa is doubled, but Fraction is left the same.*/
if (config->cr1 & USART_CR1_OVER8) if (config->cr1 & USART_CR1_OVER8)
fck = ((fck & ~7) * 2) | (fck & 7); brr = ((brr & ~7) * 2) | (brr & 7);
u->BRR = fck;
osalDbgAssert(brr < 0x1000, "invalid BRR value");
}
u->BRR = brr;
/* Note that some bits are enforced.*/ /* Note that some bits are enforced.*/
u->CR2 = config->cr2 | USART_CR2_LBDIE; u->CR2 = config->cr2 | USART_CR2_LBDIE;

20
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -222,17 +222,17 @@ void stm32_clock_init(void) {
#endif #endif
/* Other clock-related settings (dividers, MCO etc).*/ /* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE2 | STM32_PPRE1 | RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE; STM32_HPRE;
/* CCIPR register initialization, note, must take care of the _OFF /* CCIPR registers initialization, note.*/
pseudo settings.*/ RCC->CCIPR = STM32_ADC345SEL | STM32_ADC12SEL | STM32_CLK48SEL |
RCC->CCIPR = STM32_ADC345SEL | STM32_ADC12SEL | STM32_CLK48SEL | STM32_FDCANSEL | STM32_I2S23SEL | STM32_SAI1SEL |
STM32_FDCANSEL | STM32_I2S23SEL | STM32_SAI1SEL | STM32_LPTIM1SEL | STM32_I2C3SEL | STM32_I2C2SEL |
STM32_LPTIM1SEL | STM32_I2C3SEL | STM32_I2C2SEL | STM32_I2C1SEL | STM32_LPUART1SEL | STM32_UART5SEL |
STM32_I2C1SEL | STM32_LPUART1SEL | STM32_UART5SEL | STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL |
STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL | STM32_USART1SEL;
STM32_USART1SEL; RCC->CCIPR2 = STM32_QSPISEL | STM32_I2C4SEL;
/* Set flash WS's for SYSCLK source */ /* Set flash WS's for SYSCLK source */
FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN |

88
os/hal/ports/STM32/STM32G4xx/hal_lld.h
View File

@ -150,16 +150,16 @@
#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U) #define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U) #define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
#define STM32_PPRE1_MASK (7U << 7U) /**< PPRE1 field mask. */ #define STM32_PPRE1_MASK (7U << 8U) /**< PPRE1 field mask. */
#define STM32_PPRE1_FIELD(n) ((n) << 7U) /**< PPRE1 field value. */ #define STM32_PPRE1_FIELD(n) ((n) << 8U) /**< PPRE1 field value. */
#define STM32_PPRE1_DIV1 STM32_PPRE1_FIELD(0U) #define STM32_PPRE1_DIV1 STM32_PPRE1_FIELD(0U)
#define STM32_PPRE1_DIV2 STM32_PPRE1_FIELD(4U) #define STM32_PPRE1_DIV2 STM32_PPRE1_FIELD(4U)
#define STM32_PPRE1_DIV4 STM32_PPRE1_FIELD(5U) #define STM32_PPRE1_DIV4 STM32_PPRE1_FIELD(5U)
#define STM32_PPRE1_DIV8 STM32_PPRE1_FIELD(6U) #define STM32_PPRE1_DIV8 STM32_PPRE1_FIELD(6U)
#define STM32_PPRE1_DIV16 STM32_PPRE1_FIELD(7U) #define STM32_PPRE1_DIV16 STM32_PPRE1_FIELD(7U)
#define STM32_PPRE2_MASK (7U << 12U) /**< PPRE2 field mask. */ #define STM32_PPRE2_MASK (7U << 11U) /**< PPRE2 field mask. */
#define STM32_PPRE2_FIELD(n) ((n) << 12U) /**< PPRE2 field value. */ #define STM32_PPRE2_FIELD(n) ((n) << 11U) /**< PPRE2 field value. */
#define STM32_PPRE2_DIV1 STM32_PPRE1_FIELD(0U) #define STM32_PPRE2_DIV1 STM32_PPRE1_FIELD(0U)
#define STM32_PPRE2_DIV2 STM32_PPRE1_FIELD(4U) #define STM32_PPRE2_DIV2 STM32_PPRE1_FIELD(4U)
#define STM32_PPRE2_DIV4 STM32_PPRE1_FIELD(5U) #define STM32_PPRE2_DIV4 STM32_PPRE1_FIELD(5U)
@ -200,58 +200,58 @@
* @{ * @{
*/ */
#define STM32_USART1SEL_MASK (3U << 0U) /**< USART1SEL mask. */ #define STM32_USART1SEL_MASK (3U << 0U) /**< USART1SEL mask. */
#define STM32_USART1SEL_PCLK (0U << 0U) /**< USART1 source is PCLK. */ #define STM32_USART1SEL_PCLK2 (0U << 0U) /**< USART1 source is PCLK2. */
#define STM32_USART1SEL_SYSCLK (1U << 0U) /**< USART1 source is SYSCLK. */ #define STM32_USART1SEL_SYSCLK (1U << 0U) /**< USART1 source is SYSCLK. */
#define STM32_USART1SEL_HSI16 (2U << 0U) /**< USART1 source is HSI16. */ #define STM32_USART1SEL_HSI16 (2U << 0U) /**< USART1 source is HSI16. */
#define STM32_USART1SEL_LSE (3U << 0U) /**< USART1 source is LSE. */ #define STM32_USART1SEL_LSE (3U << 0U) /**< USART1 source is LSE. */
#define STM32_USART2SEL_MASK (3U << 2U) /**< USART2 mask. */ #define STM32_USART2SEL_MASK (3U << 2U) /**< USART2 mask. */
#define STM32_USART2SEL_PCLK (0U << 2U) /**< USART2 source is PCLK. */ #define STM32_USART2SEL_PCLK1 (0U << 2U) /**< USART2 source is PCLK1. */
#define STM32_USART2SEL_SYSCLK (1U << 2U) /**< USART2 source is SYSCLK. */ #define STM32_USART2SEL_SYSCLK (1U << 2U) /**< USART2 source is SYSCLK. */
#define STM32_USART2SEL_HSI16 (2U << 2U) /**< USART2 source is HSI16. */ #define STM32_USART2SEL_HSI16 (2U << 2U) /**< USART2 source is HSI16. */
#define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */ #define STM32_USART2SEL_LSE (3U << 2U) /**< USART2 source is LSE. */
#define STM32_USART3SEL_MASK (3U << 4U) /**< USART3 mask. */ #define STM32_USART3SEL_MASK (3U << 4U) /**< USART3 mask. */
#define STM32_USART3SEL_PCLK (0U << 4U) /**< USART3 source is PCLK. */ #define STM32_USART3SEL_PCLK1 (0U << 4U) /**< USART3 source is PCLK1. */
#define STM32_USART3SEL_SYSCLK (1U << 4U) /**< USART3 source is SYSCLK. */ #define STM32_USART3SEL_SYSCLK (1U << 4U) /**< USART3 source is SYSCLK. */
#define STM32_USART3SEL_HSI16 (2U << 4U) /**< USART3 source is HSI16. */ #define STM32_USART3SEL_HSI16 (2U << 4U) /**< USART3 source is HSI16. */
#define STM32_USART3SEL_LSE (3U << 4U) /**< USART3 source is LSE. */ #define STM32_USART3SEL_LSE (3U << 4U) /**< USART3 source is LSE. */
#define STM32_UART4SEL_MASK (3U << 6U) /**< UART4 mask. */ #define STM32_UART4SEL_MASK (3U << 6U) /**< UART4 mask. */
#define STM32_UART4SEL_PCLK (0U << 6U) /**< UART4 source is PCLK. */ #define STM32_UART4SEL_PCLK1 (0U << 6U) /**< UART4 source is PCLK1. */
#define STM32_UART4SEL_SYSCLK (1U << 6U) /**< UART4 source is SYSCLK. */ #define STM32_UART4SEL_SYSCLK (1U << 6U) /**< UART4 source is SYSCLK. */
#define STM32_UART4SEL_HSI16 (2U << 6U) /**< UART4 source is HSI16. */ #define STM32_UART4SEL_HSI16 (2U << 6U) /**< UART4 source is HSI16. */
#define STM32_UART4SEL_LSE (3U << 6U) /**< UART4 source is LSE. */ #define STM32_UART4SEL_LSE (3U << 6U) /**< UART4 source is LSE. */
#define STM32_UART5SEL_MASK (3U << 8U) /**< UART5 mask. */ #define STM32_UART5SEL_MASK (3U << 8U) /**< UART5 mask. */
#define STM32_UART5SEL_PCLK (0U << 8U) /**< UART5 source is PCLK. */ #define STM32_UART5SEL_PCLK1 (0U << 8U) /**< UART5 source is PCLK1. */
#define STM32_UART5SEL_SYSCLK (1U << 8U) /**< UART5 source is SYSCLK. */ #define STM32_UART5SEL_SYSCLK (1U << 8U) /**< UART5 source is SYSCLK. */
#define STM32_UART5SEL_HSI16 (2U << 8U) /**< UART5 source is HSI16. */ #define STM32_UART5SEL_HSI16 (2U << 8U) /**< UART5 source is HSI16. */
#define STM32_UART5SEL_LSE (3U << 8U) /**< UART5 source is LSE. */ #define STM32_UART5SEL_LSE (3U << 8U) /**< UART5 source is LSE. */
#define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */ #define STM32_LPUART1SEL_MASK (3U << 10U) /**< LPUART1 mask. */
#define STM32_LPUART1SEL_PCLK (0U << 10U) /**< LPUART1 source is PCLK. */ #define STM32_LPUART1SEL_PCLK1 (0U << 10U) /**< LPUART1 source is PCLK1. */
#define STM32_LPUART1SEL_SYSCLK (1U << 10U) /**< LPUART1 source is SYSCLK. */ #define STM32_LPUART1SEL_SYSCLK (1U << 10U) /**< LPUART1 source is SYSCLK. */
#define STM32_LPUART1SEL_HSI16 (2U << 10U) /**< LPUART1 source is HSI16. */ #define STM32_LPUART1SEL_HSI16 (2U << 10U) /**< LPUART1 source is HSI16. */
#define STM32_LPUART1SEL_LSE (3U << 10U) /**< LPUART1 source is LSE. */ #define STM32_LPUART1SEL_LSE (3U << 10U) /**< LPUART1 source is LSE. */
#define STM32_I2C1SEL_MASK (3U << 12U) /**< I2C1SEL mask. */ #define STM32_I2C1SEL_MASK (3U << 12U) /**< I2C1SEL mask. */
#define STM32_I2C1SEL_PCLK (0U << 12U) /**< I2C1 source is PCLK. */ #define STM32_I2C1SEL_PCLK1 (0U << 12U) /**< I2C1 source is PCLK1. */
#define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */ #define STM32_I2C1SEL_SYSCLK (1U << 12U) /**< I2C1 source is SYSCLK. */
#define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */ #define STM32_I2C1SEL_HSI16 (2U << 12U) /**< I2C1 source is HSI16. */
#define STM32_I2C2SEL_MASK (3U << 14U) /**< I2C2SEL mask. */ #define STM32_I2C2SEL_MASK (3U << 14U) /**< I2C2SEL mask. */
#define STM32_I2C2SEL_PCLK (0U << 14U) /**< I2C2 source is PCLK. */ #define STM32_I2C2SEL_PCLK1 (0U << 14U) /**< I2C2 source is PCLK1. */
#define STM32_I2C2SEL_SYSCLK (1U << 14U) /**< I2C2 source is SYSCLK. */ #define STM32_I2C2SEL_SYSCLK (1U << 14U) /**< I2C2 source is SYSCLK. */
#define STM32_I2C2SEL_HSI16 (2U << 14U) /**< I2C2 source is HSI16. */ #define STM32_I2C2SEL_HSI16 (2U << 14U) /**< I2C2 source is HSI16. */
#define STM32_I2C3SEL_MASK (3U << 16U) /**< I2C3SEL mask. */ #define STM32_I2C3SEL_MASK (3U << 16U) /**< I2C3SEL mask. */
#define STM32_I2C3SEL_PCLK (0U << 16U) /**< I2C3 source is PCLK. */ #define STM32_I2C3SEL_PCLK1 (0U << 16U) /**< I2C3 source is PCLK1. */
#define STM32_I2C3SEL_SYSCLK (1U << 16U) /**< I2C3 source is SYSCLK. */ #define STM32_I2C3SEL_SYSCLK (1U << 16U) /**< I2C3 source is SYSCLK. */
#define STM32_I2C3SEL_HSI16 (2U << 16U) /**< I2C3 source is HSI16. */ #define STM32_I2C3SEL_HSI16 (2U << 16U) /**< I2C3 source is HSI16. */
#define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */ #define STM32_LPTIM1SEL_MASK (3U << 18U) /**< LPTIM1SEL mask. */
#define STM32_LPTIM1SEL_PCLK (0U << 18U) /**< LPTIM1 source is PCLK. */ #define STM32_LPTIM1SEL_PCLK1 (0U << 18U) /**< LPTIM1 source is PCLK1. */
#define STM32_LPTIM1SEL_LSI (1U << 18U) /**< LPTIM1 source is LSI. */ #define STM32_LPTIM1SEL_LSI (1U << 18U) /**< LPTIM1 source is LSI. */
#define STM32_LPTIM1SEL_HSI16 (2U << 18U) /**< LPTIM1 source is HSI16. */ #define STM32_LPTIM1SEL_HSI16 (2U << 18U) /**< LPTIM1 source is HSI16. */
#define STM32_LPTIM1SEL_LSE (3U << 18U) /**< LPTIM1 source is LSE. */ #define STM32_LPTIM1SEL_LSE (3U << 18U) /**< LPTIM1 source is LSE. */
@ -292,7 +292,7 @@
* @{ * @{
*/ */
#define STM32_I2C4SEL_MASK (3U << 0U) /**< I2C4SEL mask. */ #define STM32_I2C4SEL_MASK (3U << 0U) /**< I2C4SEL mask. */
#define STM32_I2C4SEL_PCLK (0U << 0U) /**< I2C4 source is PCLK. */ #define STM32_I2C4SEL_PCLK1 (0U << 0U) /**< I2C4 source is PCLK1. */
#define STM32_I2C4SEL_SYSCLK (1U << 0U) /**< I2C4 source is SYSCLK. */ #define STM32_I2C4SEL_SYSCLK (1U << 0U) /**< I2C4 source is SYSCLK. */
#define STM32_I2C4SEL_HSI16 (2U << 0U) /**< I2C4 source is HSI16. */ #define STM32_I2C4SEL_HSI16 (2U << 0U) /**< I2C4 source is HSI16. */
@ -390,7 +390,7 @@
* @brief Main clock source selection. * @brief Main clock source selection.
* @note If the selected clock source is not the PLL then the PLL is not * @note If the selected clock source is not the PLL then the PLL is not
* initialized and started. * initialized and started.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 170MHz system clock from
* the internal 16MHz HSI clock. * the internal 16MHz HSI clock.
*/ */
#if !defined(STM32_SW) || defined(__DOXYGEN__) #if !defined(STM32_SW) || defined(__DOXYGEN__)
@ -401,7 +401,7 @@
* @brief Clock source for the PLL. * @brief Clock source for the PLL.
* @note This setting has only effect if the PLL is selected as the * @note This setting has only effect if the PLL is selected as the
* system clock source. * system clock source.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 170MHz system clock from
* the internal 16MHz HSI clock. * the internal 16MHz HSI clock.
*/ */
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) #if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
@ -411,7 +411,7 @@
/** /**
* @brief PLLM divider value. * @brief PLLM divider value.
* @note The allowed values are 1..16. * @note The allowed values are 1..16.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 170MHz system clock from
* the internal 16MHz HSI clock. * the internal 16MHz HSI clock.
*/ */
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
@ -421,7 +421,7 @@
/** /**
* @brief PLLN multiplier value. * @brief PLLN multiplier value.
* @note The allowed values are 8..127. * @note The allowed values are 8..127.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 170MHz system clock from
* the internal 16MHz HSI clock. * the internal 16MHz HSI clock.
*/ */
#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__)
@ -455,7 +455,7 @@
/** /**
* @brief PLLR divider value. * @brief PLLR divider value.
* @note The allowed values are 2, 4, 6, 8. * @note The allowed values are 2, 4, 6, 8.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 170MHz system clock from
* the internal 16MHz HSI clock. * the internal 16MHz HSI clock.
*/ */
#if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__) #if !defined(STM32_PLLR_VALUE) || defined(__DOXYGEN__)
@ -464,7 +464,7 @@
/** /**
* @brief AHB prescaler value. * @brief AHB prescaler value.
* @note The default value is calculated for a 168MHz system clock from * @note The default value is calculated for a 170MHz system clock from
* the internal 16MHz HSI clock. * the internal 16MHz HSI clock.
*/ */
#if !defined(STM32_HPRE) || defined(__DOXYGEN__) #if !defined(STM32_HPRE) || defined(__DOXYGEN__)
@ -475,7 +475,7 @@
* @brief APB1 prescaler value. * @brief APB1 prescaler value.
*/ */
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) #if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
#define STM32_PPRE1 STM32_PPRE1_DIV1 #define STM32_PPRE1 STM32_PPRE1_DIV2
#endif #endif
/** /**
@ -1461,8 +1461,8 @@
/** /**
* @brief USART1 clock frequency. * @brief USART1 clock frequency.
*/ */
#if (STM32_USART1SEL == STM32_USART1SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__)
#define STM32_USART1CLK STM32_PCLK #define STM32_USART1CLK STM32_PCLK2
#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK #elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK #define STM32_USART1CLK STM32_SYSCLK
@ -1480,8 +1480,8 @@
/** /**
* @brief USART2 clock frequency. * @brief USART2 clock frequency.
*/ */
#if (STM32_USART2SEL == STM32_USART2SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_USART2CLK STM32_PCLK #define STM32_USART2CLK STM32_PCLK1
#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK #elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
#define STM32_USART2CLK STM32_SYSCLK #define STM32_USART2CLK STM32_SYSCLK
@ -1499,8 +1499,8 @@
/** /**
* @brief USART3 clock frequency. * @brief USART3 clock frequency.
*/ */
#if (STM32_USART3SEL == STM32_USART3SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_USART3CLK STM32_PCLK #define STM32_USART3CLK STM32_PCLK1
#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK #elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK
#define STM32_USART3CLK STM32_SYSCLK #define STM32_USART3CLK STM32_SYSCLK
@ -1518,8 +1518,8 @@
/** /**
* @brief UART4 clock frequency. * @brief UART4 clock frequency.
*/ */
#if (STM32_UART4SEL == STM32_UART4SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_UART4CLK STM32_PCLK #define STM32_UART4CLK STM32_PCLK1
#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK #elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK
#define STM32_UART4CLK STM32_SYSCLK #define STM32_UART4CLK STM32_SYSCLK
@ -1537,8 +1537,8 @@
/** /**
* @brief UART5 clock frequency. * @brief UART5 clock frequency.
*/ */
#if (STM32_UART5SEL == STM32_UART5SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_UART5CLK STM32_PCLK #define STM32_UART5CLK STM32_PCLK1
#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK #elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK
#define STM32_UART5CLK STM32_SYSCLK #define STM32_UART5CLK STM32_SYSCLK
@ -1556,8 +1556,8 @@
/** /**
* @brief LPUART1 clock frequency. * @brief LPUART1 clock frequency.
*/ */
#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_LPUART1CLK STM32_PCLK #define STM32_LPUART1CLK STM32_PCLK1
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK #elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
#define STM32_LPUART1CLK STM32_SYSCLK #define STM32_LPUART1CLK STM32_SYSCLK
@ -1575,8 +1575,8 @@
/** /**
* @brief I2C1 clock frequency. * @brief I2C1 clock frequency.
*/ */
#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C1CLK STM32_PCLK #define STM32_I2C1CLK STM32_PCLK1
#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK #elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
#define STM32_I2C1CLK STM32_SYSCLK #define STM32_I2C1CLK STM32_SYSCLK
@ -1591,8 +1591,8 @@
/** /**
* @brief I2C2 clock frequency. * @brief I2C2 clock frequency.
*/ */
#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C2CLK STM32_PCLK #define STM32_I2C2CLK STM32_PCLK1
#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK #elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK
#define STM32_I2C2CLK STM32_SYSCLK #define STM32_I2C2CLK STM32_SYSCLK
@ -1607,8 +1607,8 @@
/** /**
* @brief I2C3 clock frequency. * @brief I2C3 clock frequency.
*/ */
#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C3CLK STM32_PCLK #define STM32_I2C3CLK STM32_PCLK1
#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK #elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK
#define STM32_I2C3CLK STM32_SYSCLK #define STM32_I2C3CLK STM32_SYSCLK
@ -1623,8 +1623,8 @@
/** /**
* @brief I2C4 clock frequency. * @brief I2C4 clock frequency.
*/ */
#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_I2C4CLK STM32_PCLK #define STM32_I2C4CLK STM32_PCLK1
#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK #elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK
#define STM32_I2C4CLK STM32_SYSCLK #define STM32_I2C4CLK STM32_SYSCLK
@ -1639,8 +1639,8 @@
/** /**
* @brief LPTIM1 clock frequency. * @brief LPTIM1 clock frequency.
*/ */
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK) || defined(__DOXYGEN__) #if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__)
#define STM32_LPTIM1CLK STM32_PCLK #define STM32_LPTIM1CLK STM32_PCLK1
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI #elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
#define STM32_LPTIM1CLK STM32_LSICLK #define STM32_LPTIM1CLK STM32_LSICLK

20
os/hal/ports/STM32/STM32G4xx/stm32_isr.h
View File

@ -83,15 +83,15 @@
#define STM32_DMA1_CH5_HANDLER Vector7C #define STM32_DMA1_CH5_HANDLER Vector7C
#define STM32_DMA1_CH6_HANDLER Vector80 #define STM32_DMA1_CH6_HANDLER Vector80
#define STM32_DMA1_CH7_HANDLER Vector84 #define STM32_DMA1_CH7_HANDLER Vector84
#define STM32_DMA1_CH8_HANDLER Vector1B0 #define STM32_DMA1_CH8_HANDLER Vector1C0
#define STM32_DMA2_CH1_HANDLER Vector120 #define STM32_DMA2_CH1_HANDLER Vector120
#define STM32_DMA2_CH2_HANDLER Vector124 #define STM32_DMA2_CH2_HANDLER Vector124
#define STM32_DMA2_CH3_HANDLER Vector128 #define STM32_DMA2_CH3_HANDLER Vector128
#define STM32_DMA2_CH4_HANDLER Vector12C #define STM32_DMA2_CH4_HANDLER Vector12C
#define STM32_DMA2_CH5_HANDLER Vector130 #define STM32_DMA2_CH5_HANDLER Vector130
#define STM32_DMA2_CH6_HANDLER Vector1B4 #define STM32_DMA2_CH6_HANDLER Vector1C4
#define STM32_DMA2_CH7_HANDLER Vector1B8 #define STM32_DMA2_CH7_HANDLER Vector1C8
#define STM32_DMA2_CH8_HANDLER Vector1BC #define STM32_DMA2_CH8_HANDLER Vector1CC
#define STM32_DMA1_CH1_NUMBER 11 #define STM32_DMA1_CH1_NUMBER 11
#define STM32_DMA1_CH2_NUMBER 12 #define STM32_DMA1_CH2_NUMBER 12
@ -150,8 +150,8 @@
#define STM32_I2C1_ERROR_HANDLER VectorC0 #define STM32_I2C1_ERROR_HANDLER VectorC0
#define STM32_I2C2_EVENT_HANDLER VectorC4 #define STM32_I2C2_EVENT_HANDLER VectorC4
#define STM32_I2C2_ERROR_HANDLER VectorC8 #define STM32_I2C2_ERROR_HANDLER VectorC8
#define STM32_I2C3_EVENT_HANDLER Vector1A0 #define STM32_I2C3_EVENT_HANDLER Vector1B0
#define STM32_I2C3_ERROR_HANDLER Vector1A4 #define STM32_I2C3_ERROR_HANDLER Vector1B4
#define STM32_I2C4_EVENT_HANDLER Vector188 #define STM32_I2C4_EVENT_HANDLER Vector188
#define STM32_I2C4_ERROR_HANDLER Vector18C #define STM32_I2C4_ERROR_HANDLER Vector18C
@ -164,6 +164,12 @@
#define STM32_I2C4_EVENT_NUMBER 82 #define STM32_I2C4_EVENT_NUMBER 82
#define STM32_I2C4_ERROR_NUMBER 83 #define STM32_I2C4_ERROR_NUMBER 83
/*
* QUADSPI unit.
*/
#define STM32_QUADSPI1_HANDLER Vector1BC
#define STM32_QUADSPI1_NUMBER 95
/* /*
* TIM units. * TIM units.
*/ */
@ -213,7 +219,7 @@
#define STM32_USART3_HANDLER VectorDC #define STM32_USART3_HANDLER VectorDC
#define STM32_UART4_HANDLER Vector110 #define STM32_UART4_HANDLER Vector110
#define STM32_UART5_HANDLER Vector114 #define STM32_UART5_HANDLER Vector114
#define STM32_LPUART1_HANDLER Vector19C #define STM32_LPUART1_HANDLER Vector1AC
#define STM32_USART1_NUMBER 37 #define STM32_USART1_NUMBER 37
#define STM32_USART2_NUMBER 38 #define STM32_USART2_NUMBER 38

3
readme.txt
View File

@ -74,6 +74,9 @@
***************************************************************************** *****************************************************************************
*** Next *** *** Next ***
- HAL: Added script to generate board files from command line, just run
./os/hal/boards/genboard.sh with the board directory name as
parameter.
- HAL: Modified the ST driver to support, optionally, multiple additional - HAL: Modified the ST driver to support, optionally, multiple additional
callback-capable channels. callback-capable channels.
- RT: Removed regarm_t type from port layer and replaced with uint32_t, this - RT: Removed regarm_t type from port layer and replaced with uint32_t, this