diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld_type3.h b/os/hal/ports/STM32/STM32H7xx/hal_lld_type3.h index 58d7d0c79..2ecd42c31 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld_type3.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld_type3.h @@ -283,6 +283,8 @@ #define RCC_CDCCIP1R_SPDIFSEL_VALUE(n) ((n) << RCC_CDCCIP1R_SPDIFSEL_Pos) #define RCC_CDCCIP1R_SPI45SEL_VALUE(n) ((n) << RCC_CDCCIP1R_SPI45SEL_Pos) #define RCC_CDCCIP1R_SPI123SEL_VALUE(n) ((n) << RCC_CDCCIP1R_SPI123SEL_Pos) +#define RCC_CDCCIP1R_SAI2BSEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2BSEL_Pos) +#define RCC_CDCCIP1R_SAI2ASEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2ASEL_Pos) #define RCC_CDCCIP1R_SAI1SEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI1SEL_Pos) #define RCC_CDCCIP2R_LPTIM1SEL_VALUE(n) ((n) << RCC_CDCCIP2R_LPTIM1SEL_Pos) @@ -294,8 +296,6 @@ #define RCC_CDCCIP2R_USART234578SEL_VALUE(n) ((n) << RCC_CDCCIP2R_USART234578SEL_Pos) #define RCC_SRDCCIPR_SPI6SEL_VALUE(n) ((n) << RCC_SRDCCIPR_SPI6SEL_Pos) -#define RCC_CDCCIP1R_SAI2BSEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2BSEL_Pos) -#define RCC_CDCCIP1R_SAI2ASEL_VALUE(n) ((n) << RCC_CDCCIP1R_SAI2ASEL_Pos) #define RCC_SRDCCIPR_ADCSEL_VALUE(n) ((n) << RCC_SRDCCIPR_ADCSEL_Pos) #define RCC_SRDCCIPR_LPTIM3SEL_VALUE(n) ((n) << RCC_SRDCCIPR_LPTIM3SEL_Pos) #define RCC_SRDCCIPR_LPTIM2SEL_VALUE(n) ((n) << RCC_SRDCCIPR_LPTIM2SEL_Pos) @@ -1051,13 +1051,6 @@ #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 #endif -/** - * @brief DFSDM2 clock source. - */ -#if !defined(STM32_DFSDM2SEL) || defined(__DOXYGEN__) -#define STM32_DFSDM2SEL STM32_DFSDM2SEL_PCLK4 -#endif - /** * @brief SPDIF clock source. */ @@ -1080,10 +1073,17 @@ #endif /** - * @brief SAI2 clock source. + * @brief SAI2BSEL clock source. */ -#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__) -#define STM32_SAI2SEL 0U /* Not present.*/ +#if !defined(STM32_SAI2BSEL) || defined(__DOXYGEN__) +#define STM32_SAI2BSEL STM32_SAI2BSEL_PLL1_Q_CK +#endif + +/** + * @brief SAI2ASEL clock source. + */ +#if !defined(STM32_SAI2ASEL) || defined(__DOXYGEN__) +#define STM32_SAI2ASEL STM32_SAI2ASEL_PLL1_Q_CK #endif /** @@ -1150,17 +1150,10 @@ #endif /** - * @brief SAI2BSEL clock source. + * @brief DFSDM2 clock source. */ -#if !defined(STM32_SAI2BSEL) || defined(__DOXYGEN__) -#define STM32_SAI2BSEL STM32_SAI2BSEL_PLL1_Q_CK -#endif - -/** - * @brief SAI2ASEL clock source. - */ -#if !defined(STM32_SAI2ASEL) || defined(__DOXYGEN__) -#define STM32_SAI2ASEL STM32_SAI2ASEL_PLL1_Q_CK +#if !defined(STM32_DFSDM2SEL) || defined(__DOXYGEN__) +#define STM32_DFSDM2SEL STM32_DFSDM2SEL_PCLK4 #endif /** diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h index a86ea35ba..d2566b6ba 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h @@ -46,11 +46,6 @@ #define STM32_HAS_M4 TRUE #endif -/** - * @name STM32H7xx capabilities - * @{ - */ - /*===========================================================================*/ /* Common. */ /*===========================================================================*/ @@ -346,15 +341,12 @@ #define STM32_HAS_DCMI TRUE #endif /* defined(STM32H743xx) || defined(STM32H753xx) */ -/** @} */ /*===========================================================================*/ -/* STM32H723xx, STM32H733xx, STM32H725xx, STM32H735xx. */ +/* STM32H723xx, STM32H733xx, STM32H725xx, STM32H735xx. */ /*===========================================================================*/ #if defined(STM32H723xx) || defined(STM32H733xx) || \ defined(STM32H725xx) || defined(STM32H735xx) || \ - defined(STM32H7A3xx) || defined(STM32H7B3xx) || \ - defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || \ defined(__DOXYGEN__) /* ADC attributes.*/ @@ -371,7 +363,7 @@ /* CAN attributes.*/ #define STM32_HAS_FDCAN1 TRUE #define STM32_HAS_FDCAN2 TRUE -#define STM32_HAS_FDCAN3 TRUE +#define STM32_HAS_FDCAN3 FALSE #define STM32_FDCAN_FLS_NBR 128U #define STM32_FDCAN_FLE_NBR 128U #define STM32_FDCAN_RF0_NBR 64U @@ -585,7 +577,243 @@ #endif /* defined(STM32H723xx) || defined(STM32H733xx) || defined(STM32H725xx) || defined(STM32H735xx) */ -/** @} */ + +/*===========================================================================*/ +/* STM32H7A3xx, STM32H7B3xx, STM32H7A3xxQ, STM32H7B3xxQ. */ +/*===========================================================================*/ +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || \ + defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || \ + defined(__DOXYGEN__) + +/* ADC attributes.*/ +#define STM32_ADC_RENAMED_REGS TRUE +#define STM32_HAS_ADC1 TRUE +#define STM32_HAS_ADC2 TRUE +#define STM32_HAS_ADC3 FALSE /* NOT an error, it is a different ADC type.*/ +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_FDCAN1 TRUE +#define STM32_HAS_FDCAN2 TRUE +#define STM32_HAS_FDCAN3 FALSE +#define STM32_FDCAN_FLS_NBR 128U +#define STM32_FDCAN_FLE_NBR 128U +#define STM32_FDCAN_RF0_NBR 64U +#define STM32_FDCAN_RF1_NBR 64U +#define STM32_FDCAN_RB_NBR 64U +#define STM32_FDCAN_TEF_NBR 32U +#define STM32_FDCAN_TB_NBR 32U +#define STM32_FDCAN_TM_NBR 64U + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* BDMA attributes.*/ +#define STM32_HAS_BDMA1 TRUE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE + +#define STM32_HAS_DMA1 TRUE +#define STM32_HAS_DMA2 TRUE + +/* MDMA attributes.*/ +#define STM32_HAS_MDMA1 TRUE + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_ENHANCED +#define STM32_EXTI_NUM_LINES 34 +#define STM32_EXTI_IMR1_MASK 0x1F800000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOI TRUE +#define STM32_HAS_GPIOJ TRUE +#define STM32_HAS_GPIOK TRUE +#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \ + RCC_AHB4ENR_GPIOBEN | \ + RCC_AHB4ENR_GPIOCEN | \ + RCC_AHB4ENR_GPIODEN | \ + RCC_AHB4ENR_GPIOEEN | \ + RCC_AHB4ENR_GPIOFEN | \ + RCC_AHB4ENR_GPIOGEN | \ + RCC_AHB4ENR_GPIOHEN | \ + RCC_AHB4ENR_GPIOIEN | \ + RCC_AHB4ENR_GPIOJEN | \ + RCC_AHB4ENR_GPIOKEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 TRUE +#define STM32_HAS_I2C4 TRUE + +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 TRUE +#define STM32_HAS_OCTOSPI2 TRUE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE +#define STM32_HAS_QUADSPI2 FALSE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 TRUE +#define STM32_HAS_SDMMC2 TRUE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S TRUE +#define STM32_SPI1_I2S_FULLDUPLEX TRUE + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX TRUE + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S TRUE +#define STM32_SPI3_I2S_FULLDUPLEX TRUE + +#define STM32_HAS_SPI4 TRUE +#define STM32_SPI4_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI5 TRUE +#define STM32_SPI5_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI6 TRUE +#define STM32_SPI6_SUPPORTS_I2S FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM8 TRUE +#define STM32_TIM8_IS_32BITS FALSE +#define STM32_TIM8_CHANNELS 6 + +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 1 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_UART5 TRUE +#define STM32_HAS_USART6 TRUE +#define STM32_HAS_UART7 TRUE +#define STM32_HAS_UART8 TRUE +#define STM32_HAS_UART9 TRUE +#define STM32_HAS_USART10 TRUE +#define STM32_HAS_LPUART1 TRUE + +/* USB attributes.*/ +#define STM32_OTG_STEPPING 2 +#define STM32_HAS_OTG1 FALSE + +#define STM32_HAS_OTG2 TRUE +#define STM32_OTG2_ENDPOINTS 8 + +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC TRUE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D TRUE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC TRUE +#define STM32_FSMC_IS_FMC TRUE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE + +/* DCMI attributes.*/ +#define STM32_HAS_DCMI TRUE + +#endif /* defined(STM32H723xx) || defined(STM32H733xx) || + defined(STM32H725xx) || defined(STM32H735xx) */ /*===========================================================================*/ /* STM32H750xx. */