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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2356 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-11-13 08:59:15 +00:00
parent 688c495b28
commit be60d348aa
8 changed files with 32 additions and 28 deletions
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24
boards/ST_STM8L_DISCOVERY/board.h
View File

@ -101,7 +101,7 @@
*/
#define VAL_GPIOAODR 0
#define VAL_GPIOADDR 0 /* All inputs. */
#define VAL_GPIOACR1 0xFF /* All pull-up. */
#define VAL_GPIOACR1 0xFF /* All pull-up/push-pull. */
#define VAL_GPIOACR2 0
/*
@ -109,15 +109,15 @@
*/
#define VAL_GPIOBODR 0
#define VAL_GPIOBDDR 0 /* All inputs. */
#define VAL_GPIOBCR1 0xFF /* All pull-up. */
#define VAL_GPIOBCR1 0xFF /* All pull-up/push-pull. */
#define VAL_GPIOBCR2 0
/*
* Port C initial setup.
*/
#define VAL_GPIOCODR (1 < PC_LED4)
#define VAL_GPIOCODR 0
#define VAL_GPIOCDDR (1 < PC_LED4)
#define VAL_GPIOCCR1 0xFF /* All pull-up/open drain. */
#define VAL_GPIOCCR1 0xFF /* All pull-up/push-pull. */
#define VAL_GPIOCCR2 0
/*
@ -125,15 +125,15 @@
*/
#define VAL_GPIODODR 0
#define VAL_GPIODDDR 0 /* All inputs. */
#define VAL_GPIODCR1 0xFF /* All pull-up. */
#define VAL_GPIODCR1 0xFF /* All pull-up/push-pull. */
#define VAL_GPIODCR2 0
/*
* Port E initial setup.
*/
#define VAL_GPIOEODR (1 < PE_LED3)
#define VAL_GPIOEODR 0
#define VAL_GPIOEDDR (1 < PE_LED3)
#define VAL_GPIOECR1 0xFF /* All pull-up/open drain. */
#define VAL_GPIOECR1 0xFF /* All pull-up/push-pull. */
#define VAL_GPIOECR2 0
/*
@ -141,17 +141,9 @@
*/
#define VAL_GPIOFODR 0
#define VAL_GPIOFDDR 0 /* All inputs. */
#define VAL_GPIOFCR1 0xFF /* All pull-up. */
#define VAL_GPIOFCR1 0xFF /* All pull-up/push-pull. */
#define VAL_GPIOFCR2 0
/*
* Port G initial setup (not present but still initialized).
*/
#define VAL_GPIOGODR 0
#define VAL_GPIOGDDR 0 /* All inputs. */
#define VAL_GPIOGCR1 0xFF /* All pull-up. */
#define VAL_GPIOGCR2 0
#ifdef __cplusplus
extern "C" {
#endif

2
demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h
View File

@ -90,7 +90,7 @@
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#define HAL_USE_SERIAL FALSE
#endif
/**

4
demos/STM8L-STM8L152-DISCOVERY-STVD/demo/main.c
View File

@ -51,6 +51,10 @@ void main(void) {
*/
hwinit();
palClearPad(GPIOC, PC_LED4);
palSetPad(GPIOE, PE_LED3);
while(1);
/*
* OS initialization.
*/

2
demos/STM8L-STM8L152-DISCOVERY-STVD/demo/mcuconf.h
View File

@ -28,7 +28,7 @@
/*
* HAL general settings.
*/
#define STM8L_CLOCK_INIT TRUE
#define STM8L_NO_CLOCK_INIT TRUE
#define STM8L_HSI_ENABLED TRUE
#define STM8L_LSI_ENABLED TRUE
#define STM8L_HSE_ENABLED FALSE

10
os/hal/platforms/STM8L/hal_lld.c
View File

@ -49,10 +49,14 @@ ROMCONST PALConfig pal_default_config =
{VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
{VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
{VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
#if STM8L_HAS_GPIOG
{VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
#if defined(STM8L15X_MDP) || defined(STM8L15X_HD)
#if STM8L_HAS_GPIOI
{VAL_GPIOHODR, 0, VAL_GPIOHDDR, VAL_GPIOHCR1, VAL_GPIOHCR2},
#if STM8L_HAS_GPIOH
{VAL_GPIOIODR, 0, VAL_GPIOIDDR, VAL_GPIOICR1, VAL_GPIOICR2},
#endif
#endif
#endif
}
};
@ -80,7 +84,7 @@ ROMCONST PALConfig pal_default_config =
*/
void hal_lld_init(void) {
#if STM8L_CLOCK_INIT
#if !STM8L_NO_CLOCK_INIT
/* Makes sure that HSI is stable before proceeding.*/
CLK->ICKCR |= CLK_ICKCR_HSION;
while ((CLK->ICKCR & CLK_ICKCR_HSIRDY) == 0)
@ -141,7 +145,7 @@ void hal_lld_init(void) {
#if !STM8L_HSI_ENABLED
CLK->ICKCR &= ~CLK_ICKCR_HSION;
#endif
#endif /* STM8L_CLOCK_INIT */
#endif /* !STM8L_NO_CLOCK_INIT */
}
/** @} */

4
os/hal/platforms/STM8L/hal_lld.h
View File

@ -102,10 +102,10 @@
/*===========================================================================*/
/**
* @brief Enables the clock initialization in the HAL.
* @brief Disables the clock initialization in the HAL.
*/
#if !defined(STM8L_NO_CLOCK_INIT) || defined(__DOXYGEN__)
#define STM8L_CLOCK_INIT TRUE
#define STM8L_NO_CLOCK_INIT FALSE
#endif
/**

2
os/hal/platforms/STM8L/hal_lld_stm8l_md.h
View File

@ -55,7 +55,7 @@
#define STM8L_HAS_GPIOD TRUE
#define STM8L_HAS_GPIOE TRUE
#define STM8L_HAS_GPIOF TRUE
#define STM8L_HAS_GPIOG TRUE
#define STM8L_HAS_GPIOG FALSE
#define STM8L_HAS_GPIOH FALSE
#define STM8L_HAS_GPIOI FALSE

10
os/hal/platforms/STM8L/pal_lld.h
View File

@ -58,10 +58,14 @@
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
#if defined(STM8L15X_MD) || defined(__DOXYGEN__)
GPIO_TypeDef P[7];
#elif defined(STM8L15X_MDP) || defined(STM8L15X_HD)
#if STM8L_HAS_GPIOI || defined(__DOXYGEN__)
GPIO_TypeDef P[9];
#elif STM8L_HAS_GPIOH || defined(__DOXYGEN__)
GPIO_TypeDef P[8];
#elif STM8L_HAS_GPIOG || defined(__DOXYGEN__)
GPIO_TypeDef P[7];
#else
GPIO_TypeDef P[6];
#endif
} PALConfig;