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Updated STM32WLxx demo and test projects. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14879 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
vrepetenko 2021-10-07 19:41:53 +00:00
parent 6e9f4d4c5f
commit beb6839449
17 changed files with 439 additions and 435 deletions
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2
demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/halconf.h
View File

@ -163,7 +163,7 @@
* @brief Enables the SPI subsystem.
*/
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
#define HAL_USE_SPI TRUE
#define HAL_USE_SPI FALSE
#endif
/**

43
demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -40,7 +40,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0 | PWR_CR2_PVDE)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
@ -50,7 +50,7 @@
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
@ -75,7 +75,6 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clock sources.
*/
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -158,7 +158,7 @@
/*
* I2C driver system settings.
*/
#define STM32_I2C_USE_I2C1 TRUE
#define STM32_I2C_USE_I2C1 FALSE
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -200,18 +198,25 @@
* SERIAL driver system settings.
*/
#define STM32_SERIAL_USE_USART1 FALSE
#define STM32_SERIAL_USE_USART2 FALSE
#define STM32_SERIAL_USE_LPUART1 TRUE
#define STM32_SERIAL_USE_USART2 TRUE
#define STM32_SERIAL_USE_LPUART1 FALSE
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI1 FALSE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -249,7 +256,7 @@
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 TRUE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_LPUART1 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

8
demos/STM32/RT-STM32WL55JC-NUCLEO64/main.c
View File

@ -70,8 +70,8 @@ int main(void) {
/*
* Activates the serial driver using the driver default configuration.
*/
sdStart(&LPSD1, NULL);
sdWrite(&LPSD1, (uint8_t*)"Initialized\r\n", 13);
sdStart(&SD2, NULL);
sdWrite(&SD2, (uint8_t*)"Initialized\r\n", 13);
/*
* Creates the blinker thread.
@ -84,8 +84,8 @@ int main(void) {
*/
while (true) {
if (PAL_LOW == palReadLine(LINE_BUTTON_1)) {
test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite);
test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite);
test_execute((BaseSequentialStream *)&SD2, &rt_test_suite);
test_execute((BaseSequentialStream *)&SD2, &oslib_test_suite);
}
chThdSleepMilliseconds(500);
}

63
testhal/STM32/STM32WLxx/I2S/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/STM32WLxx/SPI/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/STM32WLxx/SYSTICKv2/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

61
testhal/STM32/STM32WLxx/WDG/cfg/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG TRUE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/multi/ADC/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/multi/DAC/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/multi/EFL-MFS/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/multi/PAL/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/multi/TRNG/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

63
testhal/STM32/multi/UART/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -127,12 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -176,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -206,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -220,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -264,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

39
testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -15,7 +15,7 @@
*/
/*
* STM32L4xx drivers configuration.
* STM32WLxx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -40,7 +40,7 @@
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0 | PWR_CR2_PVDE)
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
@ -50,7 +50,7 @@
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
@ -75,7 +75,6 @@
#define STM32_MCOPRE STM32_MCOPRE_DIV1
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
/*
* Peripherals clock sources.
*/
@ -115,7 +114,7 @@
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM16_PRIORITY 7
#define STM32_IRQ_TIM17_PRIORITY 9
#define STM32_IRQ_TIM17_PRIORITY 7
#define STM32_IRQ_LPTIM1_PRIORITY 7
#define STM32_IRQ_LPTIM2_PRIORITY 7
#define STM32_IRQ_LPTIM3_PRIORITY 7
@ -127,14 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -178,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -208,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -222,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -251,7 +256,7 @@
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE
#define STM32_UART_USE_USART2 TRUE
#define STM32_UART_USE_USART2 FALSE
#define STM32_UART_USE_LPUART1 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
@ -266,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

4
testrt/IRQ_STORM/make/stm32wl55jc_nucleo64.make
View File

@ -109,9 +109,6 @@ include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
#include $(CHIBIOS)/os/test/test.mk
#include $(CHIBIOS)/test/rt/rt_test.mk
#include $(CHIBIOS)/test/oslib/oslib_test.mk
include $(CHIBIOS)/os/hal/lib/streams/streams.mk
# Define linker script file here.
@ -120,7 +117,6 @@ LDSCRIPT= $(STARTUPLD)/STM32WLxxxC.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
CSRC = $(ALLCSRC) \
$(TESTSRC) \
$(CONFDIR)/portab.c \
main.c

75
testrt/VT_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -15,7 +15,7 @@
*/
/*
* STM32L4xx drivers configuration.
* STM32WLxx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -115,7 +114,7 @@
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM16_PRIORITY 7
#define STM32_IRQ_TIM17_PRIORITY 9
#define STM32_IRQ_TIM17_PRIORITY 7
#define STM32_IRQ_LPTIM1_PRIORITY 7
#define STM32_IRQ_LPTIM2_PRIORITY 7
#define STM32_IRQ_LPTIM3_PRIORITY 7
@ -127,14 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -152,10 +150,10 @@
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM1 TRUE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM16 TRUE
#define STM32_GPT_USE_TIM17 TRUE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
@ -178,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -208,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -222,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -266,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */

75
testrt/VT_STORM/cfg/stm32wl55jc_nucleo64_v2/mcuconf.h
View File

@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -15,7 +15,7 @@
*/
/*
* STM32L4xx drivers configuration.
* STM32WLxx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
@ -37,38 +37,37 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
#define STM32_TARGET_CORE 1
#define STM32_VOS STM32_VOS_RANGE1
#define STM32_PWR_CR2 (PWR_CR2_PLS_LVL0)
#define STM32_PWR_PUCRA (0UL)
#define STM32_PWR_PDCRA (0UL)
#define STM32_PWR_PUCRB (0UL)
#define STM32_PWR_PDCRB (0UL)
#define STM32_PWR_PUCRC (0UL)
#define STM32_PWR_PDCRC (0UL)
#define STM32_PWR_PUCRH (0UL)
#define STM32_PWR_PDCRH (0UL)
#define STM32_HSI16_ENABLED FALSE
#define STM32_LSI_ENABLED TRUE
#define STM32_PWR_PUCRA (0U)
#define STM32_PWR_PDCRA (0U)
#define STM32_PWR_PUCRB (0U)
#define STM32_PWR_PDCRB (0U)
#define STM32_PWR_PUCRC (0U)
#define STM32_PWR_PDCRC (0U)
#define STM32_PWR_PUCRH (0U)
#define STM32_PWR_PDCRH (0U)
#define STM32_HSI16_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSIPRE STM32_LSIPRE_NODIV
#define STM32_HSE32_ENABLED FALSE
#define STM32_HSE32_ENABLED TRUE
#define STM32_HSE32SRC STM32_HSE32_XTAL
#define STM32_LSE_ENABLED TRUE
#define STM32_MSIPLL_ENABLED FALSE
#define STM32_MSIRANGE STM32_MSIRANGE_16M
#define STM32_MSIPLL_ENABLED TRUE
#define STM32_MSIRANGE STM32_MSIRANGE_4M
#define STM32_MSISRANGE STM32_MSISRANGE_4M
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_MSI
#define STM32_PLLM_VALUE 1
#define STM32_PLLN_VALUE 6
#define STM32_PLLN_VALUE 24
#define STM32_PLLR_VALUE 2
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
#define STM32_C2HPRE STM32_C2HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
#define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_STOPWUCK STM32_STOPWUCK_MSI
@ -79,7 +78,7 @@
/*
* Peripherals clock sources.
*/
#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
#define STM32_ADCSEL STM32_ADCSEL_NOCLK
#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
@ -89,7 +88,7 @@
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK1
#define STM32_SPI2S2SEL STM32_SPI2S2SEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
#define STM32_RNGSEL STM32_RNGSEL_LSE
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
@ -115,7 +114,7 @@
#define STM32_IRQ_TIM1_CC_PRIORITY 7
#define STM32_IRQ_TIM2_PRIORITY 7
#define STM32_IRQ_TIM16_PRIORITY 7
#define STM32_IRQ_TIM17_PRIORITY 9
#define STM32_IRQ_TIM17_PRIORITY 7
#define STM32_IRQ_LPTIM1_PRIORITY 7
#define STM32_IRQ_LPTIM2_PRIORITY 7
#define STM32_IRQ_LPTIM3_PRIORITY 7
@ -127,14 +126,13 @@
/*
* ADC driver system settings.
*/
#define STM32_ADC_COMPACT_SAMPLES FALSE
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC12_IRQ_PRIORITY 5
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_ADC_PRESCALER_VALUE 2
/*
* DAC driver system settings.
@ -152,10 +150,10 @@
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM1 TRUE
#define STM32_GPT_USE_TIM2 FALSE
#define STM32_GPT_USE_TIM16 TRUE
#define STM32_GPT_USE_TIM17 TRUE
#define STM32_GPT_USE_TIM16 FALSE
#define STM32_GPT_USE_TIM17 FALSE
/*
* I2C driver system settings.
@ -178,8 +176,6 @@
*/
#define STM32_ICU_USE_TIM1 FALSE
#define STM32_ICU_USE_TIM2 FALSE
#define STM32_ICU_USE_TIM16 FALSE
#define STM32_ICU_USE_TIM17 FALSE
/*
* PWM driver system settings.
@ -208,6 +204,13 @@
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_LPUART1_PRIORITY 12
/*
* SIO driver system settings.
*/
#define STM32_SIO_USE_USART1 FALSE
#define STM32_SIO_USE_USART2 FALSE
#define STM32_SIO_USE_LPUART1 FALSE
/*
* SPI driver system settings.
*/
@ -222,8 +225,10 @@
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
@ -266,10 +271,4 @@
*/
#define STM32_WDG_USE_IWDG FALSE
/* STM32FLASH driver settings */
#define STM32FLASH_SECTORS_COUNT 128
#define STM32FLASH_SECTOR_SIZE (2 * 1024)
#define STM32FLASH_PAGE_SIZE 8
#endif /* MCUCONF_H */