andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1911 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-05-09 17:52:30 +00:00
parent 691538eb39
commit bf0c75c33e
8 changed files with 262 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
boards/OLIMEX_STM32_P103/board.h
View File

@ -33,9 +33,8 @@
/*
* Board frequencies.
*/
#define LSECLK 32768
#define HSECLK 8000000
#define HSICLK 8000000
#define STM32_LSECLK 32768
#define STM32_HSECLK 8000000
/*
* IO pins assignments.

1
demos/ARMCM3-STM32F103-GCC/mcuconf.h
View File

@ -34,7 +34,6 @@
/*
* HAL driver system settings.
*/
#define STM32_SYSCLK 72
/*
* ADC driver system settings.

2
docs/Doxyfile
View File

@ -31,7 +31,7 @@ PROJECT_NAME = ChibiOS/RT
# This could be handy for archiving the generated documentation or
# if some version control system is used.
PROJECT_NUMBER = 1.5.6
PROJECT_NUMBER = 1.5.7
# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
# base path where the generated documentation will be put.

22
os/hal/platforms/STM32/hal_lld.c
View File

@ -74,7 +74,7 @@ const STM32GPIOConfig pal_default_config =
void hal_lld_init(void) {
/* SysTick initialization using the system clock.*/
SysTick->LOAD = SYSCLK / CH_FREQUENCY - 1;
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk |
@ -99,20 +99,22 @@ void stm32_clock_init(void) {
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
; /* Waits until HSE stable. */
/* PLL setup.*/
RCC->CFGR = RCC_CFGR_PLLSRC | PLLPREBITS | PLLMULBITS;
#if STM32_SW == STM32_SW_PLL
/* PLL setup, only if the PLL is the selected source of the system clock
else it is left disabled.*/
RCC->CFGR = ((STM32_PLLMUL - 2) << 18) | STM32_PLLXTPRE | STM32_PLLSRC;
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY))
; /* Waits until PLL stable. */
/* Clock sources.*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 |
RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 |
RCC_CFGR_MCO_NOCLOCK | USBPREBITS;
#endif
/* Clock settings.*/
RCC->CFGR = ((STM32_PLLMUL - 2) << 18) | STM32_PLLXTPRE | STM32_PLLSRC |
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
/* Flash setup and final clock selection. */
FLASH->ACR = FLASHBITS; /* Flash wait states depending on clock. */
RCC->CFGR |= RCC_CFGR_SW_PLL; /* Switches the PLL clock ON. */
while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL)
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
RCC->CFGR |= STM32_SW; /* Switches on the clock sources. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
;
}

247
os/hal/platforms/STM32/hal_lld.h
View File

@ -27,10 +27,8 @@
#ifndef _HAL_LLD_H_
#define _HAL_LLD_H_
/*
* Tricks required to make the TRUE/FALSE declaration inside the library
* compatible.
*/
/* Tricks required to make the TRUE/FALSE declaration inside the library
compatible.*/
#undef FALSE
#undef TRUE
#include "stm32f10x.h"
@ -47,24 +45,252 @@
/**
* @brief Platform name.
*/
#define PLATFORM_NAME "STM32"
#if defined(STM32F10X_LD)
#define PLATFORM_NAME "STM32 LD"
#elif defined(STM32F10X_MD)
#define PLATFORM_NAME "STM32 MD"
#elif defined(STM32F10X_HD)
#define PLATFORM_NAME "STM32 HD"
#elif defined(STM32F10X_CL)
#define PLATFORM_NAME "STM32 CL"
#else
#define PLATFORM_NAME "STM32"
#endif
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
#define STM32_ADCPRE_DIV9 (3 << 14) /**< HCLK divided by 8. */
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @brief System clock setting.
* @note Only 48MHz and 72MHz are currently supported.
* @brief Main clock source selection.
* @note If the selected clock source is not the PLL the the PLL is not
* initialized and started.
*/
#if !defined(STM32_SYSCLK) || defined(__DOXYGEN__)
#define STM32_SYSCLK 72
#define STM32_SW STM32_SW_PLL
/**
* @brief Clock source for the PLL.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
*/
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
#define STM32_PLLSRC STM32_PLLSRC_HSE
#endif
/**
* @brief Crystal PLL pre-divider.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
*/
#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#endif
/**
* @brief Desired PLL output frequency.
* @note The PLL multiplier is calculated from the input clock and this
* value.
* @note This setting has only effect if the PLL is selected as the
* system clock source.
*/
#if !defined(STM32_PLLCLKOUT) || defined(__DOXYGEN__)
#define STM32_PLLCLKOUT 72000000
#endif
/**
* @brief AHB prescaler value.
* @note It is recommended to not change this default.
*/
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
#define STM32_HPRE STM32_HPRE_DIV1
#endif
/**
* @brief APB1 prescaler value.
* @note It is recommended to not change this default.
*/
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
#define STM32_PPRE1 STM32_PPRE1_DIV2
#endif
/**
* @brief APB2 prescaler value.
* @note It is recommended to not change this default.
*/
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
#define STM32_PPRE2 STM32_PPRE2_DIV2
#endif
/**
* @brief ADC prescaler value.
* @note It is recommended to not change this default.
*/
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
#define STM32_ADCPRE STM32_ADCPRE_DIV2
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
#error "invalid STM32_PLLXTPRE value specified"
#endif
/**
* @brief PLL input clock frequency.
*/
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
#else
#define STM32_PLLCLKIN (STM32_HSECLK / 2)
#endif
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
#else
#error "invalid STM32_PLLSRC value specified"
#endif
/**
* @brief PLL multiplier.
*/
#define STM32_PLLMUL (STM32_PLLCLKOUT / STM32_PLLCLKIN)
#if (STM32_PLLMUL % 1) != 0
#error "the requested PLL output frequency is not a multiple of the input frequency"
#endif
#if (STM32_PLLMUL < 2) || (STM32_PLLMUL > 16)
#error "the calculated PLL multiplier is out of the allowed range (2...16)"
#endif
/**
* @brief PLL output clock.
*/
#define STM32_PLLCLK (STM32_PLLCLKIN * STM32_PLLMUL)
/**
* @brief System clock source.
*/
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
#define STM32_SYSCLK STM32_PLLCLK
#elif (STM32_SW == STM32_SW_HSI)
#define STM32_SYSCLK STM32_HSICLK
#elif (STM32_SW == STM32_SW_HSE)
#define STM32_SYSCLK STM32_HSECLK
#else
#error "invalid STM32_SYSCLK_SW value specified"
#endif
#if STM32_SYSCLK > 72000000
#error "STM32_SYSCLK above maximum rated frequency (72MHz)"
#endif
/**
* @brief AHB frequency.
*/
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
#define STM32_HCLK (STM32_SYSCLK / 1)
#elif STM32_HPRE == STM32_HPRE_DIV2
#define STM32_HCLK (STM32_SYSCLK / 2)
#elif STM32_HPRE == STM32_HPRE_DIV4
#define STM32_HCLK (STM32_SYSCLK / 4)
#elif STM32_HPRE == STM32_HPRE_DIV8
#define STM32_HCLK (STM32_SYSCLK / 8)
#elif STM32_HPRE == STM32_HPRE_DIV16
#define STM32_HCLK (STM32_SYSCLK / 16)
#elif STM32_HPRE == STM32_HPRE_DIV64
#define STM32_HCLK (STM32_SYSCLK / 64)
#elif STM32_HPRE == STM32_HPRE_DIV128
#define STM32_HCLK (STM32_SYSCLK / 128)
#elif STM32_HPRE == STM32_HPRE_DIV256
#define STM32_HCLK (STM32_SYSCLK / 256)
#elif STM32_HPRE == STM32_HPRE_DIV512
#define STM32_HCLK (STM32_SYSCLK / 512)
#else
#error "invalid STM32_HPRE value specified"
#endif
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_PCLK1 (STM32_HCLK / 1)
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
#define STM32_PCLK1 (STM32_HCLK / 2)
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
#define STM32_PCLK1 (STM32_HCLK / 4)
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
#define STM32_PCLK1 (STM32_HCLK / 8)
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
#define STM32_PCLK1 (STM32_HCLK / 16)
#else
#error "invalid STM32_PPRE1 value specified"
#endif
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
#define STM32_PCLK2 (STM32_HCLK / 1)
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
#define STM32_PCLK2 (STM32_HCLK / 2)
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
#define STM32_PCLK2 (STM32_HCLK / 4)
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
#define STM32_PCLK2 (STM32_HCLK / 8)
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
#define STM32_PCLK2 (STM32_HCLK / 16)
#else
#error "invalid STM32_PPRE2 value specified"
#endif
/**
* @brief Flash settings.
*/
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
#define STM32_FLASHBITS 0x00000010
#elif STM32_HCLK <= 48000000
#define STM32_FLASHBITS 0x00000011
#else
#define STM32_FLASHBITS 0x00000012
#endif
#if 0
/*
* NOTES: PLLPRE can be 1 or 2, PLLMUL can be 2..16.
*/
@ -74,7 +300,7 @@
#elif STM32_SYSCLK == 72
#define PLLMUL 9
#else
#error "unsupported STM32_SYSCLK setting"
#define PLLMUL 555
#endif
#define PLLCLK ((HSECLK / PLLPRE) * PLLMUL)
#define SYSCLK PLLCLK
@ -96,6 +322,7 @@
#define USBPREBITS 0
#define FLASHBITS 0x00000012
#endif
#endif
/*===========================================================================*/
/* Driver data structures and types. */

8
os/hal/platforms/STM32/serial_lld.c
View File

@ -92,16 +92,16 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
* Baud rate setting.
*/
if (sdp->usart == USART1)
u->BRR = APB2CLK / config->sc_speed;
u->BRR = STM32_PCLK2 / config->sc_speed;
else
u->BRR = APB1CLK / config->sc_speed;
u->BRR = STM32_PCLK1 / config->sc_speed;
/*
* Note that some bits are enforced.
*/
u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
USART_CR1_RXNEIE | USART_CR1_TE |
USART_CR1_RE;
USART_CR1_RXNEIE | USART_CR1_TE |
USART_CR1_RE;
u->CR2 = config->sc_cr2 | USART_CR2_LBDIE;
u->CR3 = config->sc_cr3 | USART_CR3_EIE;
(void)u->SR; /* SR reset step 1.*/

4
os/kernel/include/ch.h
View File

@ -39,7 +39,7 @@
/**
* @brief Kernel version string.
*/
#define CH_KERNEL_VERSION "1.5.6unstable"
#define CH_KERNEL_VERSION "1.5.7unstable"
/**
* @brief Kernel version major number.
@ -54,7 +54,7 @@
/**
* @brief Kernel version patch number.
*/
#define CH_KERNEL_PATCH 6
#define CH_KERNEL_PATCH 7
/*
* Common values.

4
readme.txt
View File

@ -58,6 +58,10 @@
*** Releases ***
*****************************************************************************
*** 1.5.7 ***
- NEW: Improved clock initialization for the STM32, now it is possible to
configure the clock using any clock source and any HSE frequency.
*** 1.5.6 ***
- FIX: Fixed centralized ARM makefile (bug 2992747)(backported in 1.4.3).
- FIX: Fixed write problems in MMC_SPI driver (bug 2991714)(backported in