git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6659 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -357,7 +357,7 @@
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<MiscControls>--c99</MiscControls>
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<Define>__heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_RAM1$$Base</Define>
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<Undefine></Undefine>
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<IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x;..\..\..\..\os\ext\CMSIS\include;..\..\..\..\os\ext\CMSIS\ST;..\..\..\..\os\rt\ports\ARMCMx;..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT;..\..\..\..\os\rt\include;..\..\..\..\os\hal\osal\rt;..\..\..\..\os\hal\include;..\..\..\..\os\hal\boards\ST_STM32F3_DISCOVERY;..\..\..\..\os\hal\ports\common\ARMCMx;..\..\..\..\os\hal\ports\STM32\STM32F30x;..\..\..\..\os\hal\ports\STM32\LLD;..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2;..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2;..\..\..\..\os\hal\ports\STM32\LLD\RTCv2;..\..\..\..\os\hal\ports\STM32\LLD\SPIv2;..\..\..\..\os\hal\ports\STM32\LLD\TIMv1;..\..\..\..\os\hal\ports\STM32\LLD\USARTv2;..\..\..\..\os\hal\ports\STM32\LLD\USBv1</IncludePath>
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<IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x;..\..\..\..\os\ext\CMSIS\include;..\..\..\..\os\ext\CMSIS\ST;..\..\..\..\os\rt\ports\ARMCMx;..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT;..\..\..\..\os\rt\include;..\..\..\..\os\hal\osal\rt;..\..\..\..\os\hal\include;..\..\..\..\os\hal\boards\ST_STM32F3_DISCOVERY;..\..\..\..\os\hal\ports\common\ARMCMx;..\..\..\..\os\hal\ports\STM32\STM32F30x;..\..\..\..\os\hal\ports\STM32\LLD;..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2;..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2;..\..\..\..\os\hal\ports\STM32\LLD\RTCv2;..\..\..\..\os\hal\ports\STM32\LLD\SPIv2;..\..\..\..\os\hal\ports\STM32\LLD\TIMv1;..\..\..\..\os\hal\ports\STM32\LLD\USARTv2;..\..\..\..\os\hal\ports\STM32\LLD\USBv1;..\..\..\..\test</IncludePath>
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</VariousControls>
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</Cads>
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<Aads>
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@ -908,6 +908,11 @@
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<FileType>1</FileType>
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<FilePath>..\..\..\..\os\hal\ports\common\ARMCMx\nvic.c</FilePath>
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</File>
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<File>
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<FileName>nvic.h</FileName>
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<FileType>5</FileType>
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<FilePath>..\..\..\..\os\hal\ports\common\ARMCMx\nvic.h</FilePath>
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</File>
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</Files>
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</Group>
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<Group>
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@ -55,7 +55,7 @@
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* @param[in] n the interrupt number
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* @param[in] prio the interrupt priority mask
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*/
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void nvicEnableVector(IRQn_Type n, uint32_t prio) {
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void nvicEnableVector(uint32_t n, uint32_t prio) {
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NVIC->IP[n] = NVIC_PRIORITY_MASK(prio);
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NVIC->ICPR[n >> 5] = 1 << (n & 0x1F);
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@ -68,22 +68,10 @@ void nvicEnableVector(IRQn_Type n, uint32_t prio) {
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*
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* @param[in] n the interrupt number
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*/
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void nvicDisableVector(IRQn_Type n) {
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void nvicDisableVector(uint32_t n) {
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NVIC->ICER[n >> 5] = 1 << (n & 0x1F);
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NVIC->IP[n] = 0;
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}
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/**
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* @brief Changes the priority of a system handler.
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* @note The parameters are not tested for correctness.
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*
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* @param[in] handler the system handler number
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* @param[in] prio the system handler priority mask
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*/
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void nvicSetSystemHandlerPriority(IRQn_Type handler, uint32_t prio) {
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SCB->SHP[((uint32_t)(handler) & 15) - 4] = NVIC_PRIORITY_MASK(prio);
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}
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/** @} */
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@ -57,9 +57,8 @@
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#ifdef __cplusplus
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extern "C" {
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#endif
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void nvicEnableVector(IRQn_Type n, uint32_t prio);
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void nvicDisableVector(IRQn_Type n);
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void nvicSetSystemHandlerPriority(IRQn_Type handler, uint32_t prio);
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void nvicEnableVector(uint32_t n, uint32_t prio);
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void nvicDisableVector(uint32_t n);
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#ifdef __cplusplus
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}
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#endif
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