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Added EFL driver for STM32F0xx. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14461 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-06-03 09:33:46 +00:00
parent 128da3d596
commit c03d38f78f
4 changed files with 664 additions and 2 deletions
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477
os/hal/ports/STM32/STM32F0xx/hal_efl_lld.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.c
* @brief STM32F0xx Embedded Flash subsystem low level driver source.
*
* @addtogroup HAL_EFL
* @{
*/
#include <string.h>
#include "hal.h"
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define STM32_FLASH_LINE_MASK (STM32_FLASH_LINE_SIZE - 1U)
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/**
* @brief EFL1 driver identifier.
*/
EFlashDriver EFLD1;
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
static const flash_descriptor_t efl_lld_descriptor = {
.attributes = FLASH_ATTR_ERASED_IS_ONE |
FLASH_ATTR_MEMORY_MAPPED,
.page_size = STM32_FLASH_LINE_SIZE,
.sectors_count = STM32_FLASH_NUMBER_OF_BANKS *
STM32_FLASH_SECTORS_PER_BANK,
.sectors = NULL,
.sectors_size = STM32_FLASH_SECTOR_SIZE,
.address = (uint8_t *)FLASH_BASE,
.size = STM32_FLASH_NUMBER_OF_BANKS *
STM32_FLASH_SECTORS_PER_BANK *
STM32_FLASH_SECTOR_SIZE
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static inline void stm32_flash_lock(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_LOCK;
}
static inline void stm32_flash_unlock(EFlashDriver *eflp) {
eflp->flash->KEYR |= FLASH_KEY1;
eflp->flash->KEYR |= FLASH_KEY2;
}
static inline void stm32_flash_enable_pgm(EFlashDriver *eflp) {
eflp->flash->CR |= FLASH_CR_PG;
}
static inline void stm32_flash_disable_pgm(EFlashDriver *eflp) {
eflp->flash->CR &= ~FLASH_CR_PG;
}
static inline void stm32_flash_clear_status(EFlashDriver *eflp) {
eflp->flash->SR = 0x0000FFFFU;
}
static inline void stm32_flash_wait_busy(EFlashDriver *eflp) {
/* Wait for busy bit clear.*/
while ((eflp->flash->SR & FLASH_SR_BSY) != 0U) {
}
}
static inline flash_error_t stm32_flash_check_errors(EFlashDriver *eflp) {
uint32_t sr = eflp->flash->SR;
/* Clearing error conditions.*/
eflp->flash->SR = sr & 0x0000FFFFU;
/* Decoding relevant errors.*/
if ((sr & FLASH_SR_WRPERR) != 0U) {
return FLASH_ERROR_HW_FAILURE;
}
if ((sr & FLASH_SR_PGERR) != 0U) {
return eflp->state == FLASH_PGM ? FLASH_ERROR_PROGRAM : FLASH_ERROR_ERASE;
}
return FLASH_NO_ERROR;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level Embedded Flash driver initialization.
*
* @notapi
*/
void efl_lld_init(void) {
/* Driver initialization.*/
eflObjectInit(&EFLD1);
EFLD1.flash = FLASH;
}
/**
* @brief Configures and activates the Embedded Flash peripheral.
*
* @param[in] eflp pointer to a @p EFlashDriver structure
*
* @notapi
*/
void efl_lld_start(EFlashDriver *eflp) {
stm32_flash_unlock(eflp);
FLASH->CR = 0x00000000U;
}
/**
* @brief Deactivates the Embedded Flash peripheral.
*
* @param[in] eflp pointer to a @p EFlashDriver structure
*
* @notapi
*/
void efl_lld_stop(EFlashDriver *eflp) {
stm32_flash_lock(eflp);
}
/**
* @brief Gets the flash descriptor structure.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @return A flash device descriptor.
* @retval Pointer to single bank if DBM not enabled.
* @retval Pointer to bank1 if DBM enabled.
*
* @notapi
*/
const flash_descriptor_t *efl_lld_get_descriptor(void *instance) {
(void)instance;
return &efl_lld_descriptor;
}
/**
* @brief Read operation.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] offset offset within full flash address space
* @param[in] n number of bytes to be read
* @param[out] rp pointer to the data buffer
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_READ if the read operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err = FLASH_NO_ERROR;
osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U));
osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No reading while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_READ state while the operation is performed.*/
devp->state = FLASH_READ;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Actual read implementation.*/
memcpy((void *)rp, (const void *)efl_lld_descriptor.address + offset, n);
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
/**
* @brief Program operation.
* @note The device supports ECC, it is only possible to write erased
* pages once except when writing all zeroes.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] offset offset within full flash address space
* @param[in] n number of bytes to be programmed
* @param[in] pp pointer to the data buffer
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_PROGRAM if the program operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err = FLASH_NO_ERROR;
osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U));
osalDbgCheck((size_t)offset + n <= (size_t)efl_lld_descriptor.size);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No programming while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_PGM state while the operation is performed.*/
devp->state = FLASH_PGM;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Enabling PGM mode in the controller.*/
stm32_flash_enable_pgm(devp);
/* Actual program implementation.*/
while (n > 0U) {
volatile uint16_t *address;
union {
uint16_t hw[STM32_FLASH_LINE_SIZE / sizeof (uint16_t)];
uint8_t b[STM32_FLASH_LINE_SIZE / sizeof (uint8_t)];
} line;
/* Unwritten bytes are initialized to all ones.*/
line.hw[0] = 0xFFFFU;
/* Programming address aligned to flash lines.*/
address = (volatile uint16_t *)(efl_lld_descriptor.address +
(offset & ~STM32_FLASH_LINE_MASK));
/* Copying data inside the prepared line.*/
do {
line.b[offset & STM32_FLASH_LINE_MASK] = *pp;
offset++;
n--;
pp++;
}
while ((n > 0U) & ((offset & STM32_FLASH_LINE_MASK) != 0U));
/* Programming line.*/
address[0] = line.hw[0];
stm32_flash_wait_busy(devp);
err = stm32_flash_check_errors(devp);
if (err != FLASH_NO_ERROR) {
break;
}
}
/* Disabling PGM mode in the controller.*/
stm32_flash_disable_pgm(devp);
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
/**
* @brief Starts a whole-device erase operation.
* @note This function only erases bank 2 if it is present. Bank 1 is not
* allowed since it is normally where the primary program is located.
* Pages on bank 1 can be individually erased.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_start_erase_all(void *instance) {
(void) instance;
return FLASH_ERROR_UNIMPLEMENTED;
}
/**
* @brief Starts an sector erase operation.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] sector sector to be erased
* this is an index within the total sectors
* in a flash bank
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
osalDbgCheck(instance != NULL);
osalDbgCheck(sector < efl_lld_descriptor.sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No erasing while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* FLASH_PGM state while the operation is performed.*/
devp->state = FLASH_ERASE;
/* Clearing error status bits.*/
stm32_flash_clear_status(devp);
/* Enable page erase.*/
devp->flash->CR |= FLASH_CR_PER;
/* Set the page.*/
devp->flash->AR = (uint32_t)(efl_lld_descriptor.address +
flashGetSectorOffset(getBaseFlash(devp), sector));
/* Start the erase.*/
devp->flash->CR |= FLASH_CR_STRT;
return FLASH_NO_ERROR;
}
/**
* @brief Queries the driver for erase operation progress.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[out] msec recommended time, in milliseconds, that
* should be spent before calling this
* function again, can be @p NULL
* @return An error code.
* @retval FLASH_NO_ERROR if there is no erase operation in progress.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_ERASE if the erase operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @api
*/
flash_error_t efl_lld_query_erase(void *instance, uint32_t *msec) {
EFlashDriver *devp = (EFlashDriver *)instance;
flash_error_t err = FLASH_NO_ERROR;
/* If there is an erase in progress then the device must be checked.*/
if (devp->state == FLASH_ERASE) {
/* Checking for operation in progress.*/
if ((devp->flash->SR & FLASH_SR_BSY) == 0U) {
/* Disabling the various erase control bits.*/
devp->flash->CR &= ~(FLASH_CR_OPTER | FLASH_CR_OPTPG |
FLASH_CR_MER | FLASH_CR_PER);
/* Back to ready state.*/
devp->state = FLASH_READY;
}
else {
/* Recommended time before polling again. This is a simplified
implementation.*/
if (msec != NULL) {
*msec = (uint32_t)STM32_FLASH_WAIT_TIME_MS;
}
err = FLASH_BUSY_ERASING;
}
}
return err;
}
/**
* @brief Returns the erase state of a sector.
*
* @param[in] ip pointer to a @p EFlashDriver instance
* @param[in] sector sector to be verified
* @return An error code.
* @retval FLASH_NO_ERROR if the sector is erased.
* @retval FLASH_BUSY_ERASING if there is an erase operation in progress.
* @retval FLASH_ERROR_VERIFY if the verify operation failed.
* @retval FLASH_ERROR_HW_FAILURE if access to the memory failed.
*
* @notapi
*/
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector) {
EFlashDriver *devp = (EFlashDriver *)instance;
uint32_t *address;
flash_error_t err = FLASH_NO_ERROR;
unsigned i;
osalDbgCheck(instance != NULL);
osalDbgCheck(sector < efl_lld_descriptor.sectors_count);
osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE),
"invalid state");
/* No verifying while erasing.*/
if (devp->state == FLASH_ERASE) {
return FLASH_BUSY_ERASING;
}
/* Address of the sector.*/
address = (uint32_t *)(efl_lld_descriptor.address +
flashGetSectorOffset(getBaseFlash(devp), sector));
/* FLASH_READ state while the operation is performed.*/
devp->state = FLASH_READ;
/* Scanning the sector space.*/
uint32_t sector_size = flashGetSectorSize(getBaseFlash(devp), sector);
for (i = 0U; i < sector_size / sizeof(uint32_t); i++) {
if (*address != 0xFFFFFFFFU) {
err = FLASH_ERROR_VERIFY;
break;
}
address++;
}
/* Ready state again.*/
devp->state = FLASH_READY;
return err;
}
#endif /* HAL_USE_EFL == TRUE */
/** @} */

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os/hal/ports/STM32/STM32F0xx/hal_efl_lld.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_efl_lld.h
* @brief STM32F1xx Embedded Flash subsystem low level driver header.
*
* @addtogroup HAL_EFL
* @{
*/
#ifndef HAL_EFL_LLD_H
#define HAL_EFL_LLD_H
#if (HAL_USE_EFL == TRUE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name STM32F1xx configuration options
* @{
*/
/**
* @brief Suggested wait time during erase operations polling.
*/
#if !defined(STM32_FLASH_WAIT_TIME_MS) || defined(__DOXYGEN__)
#define STM32_FLASH_WAIT_TIME_MS 1
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if !defined(STM32_FLASH_SECTOR_SIZE)
#error "STM32_FLASH_SECTOR_SIZE not defined in registry"
#endif
#if !defined(STM32_FLASH_NUMBER_OF_BANKS)
#error "STM32_FLASH_NUMBER_OF_BANKS not defined in registry"
#endif
#if !defined(STM32_FLASH_SECTORS_PER_BANK)
#error "STM32_FLASH_SECTORS_PER_BANK not defined in registry"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Low level fields of the embedded flash driver structure.
*/
#define efl_lld_driver_fields \
/* Flash registers.*/ \
FLASH_TypeDef *flash
/**
* @brief Low level fields of the embedded flash configuration structure.
*/
#define efl_lld_config_fields \
/* Dummy configuration, it is not needed.*/ \
uint32_t dummy
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#if !defined(__DOXYGEN__)
extern EFlashDriver EFLD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void efl_lld_init(void);
void efl_lld_start(EFlashDriver *eflp);
void efl_lld_stop(EFlashDriver *eflp);
const flash_descriptor_t *efl_lld_get_descriptor(void *instance);
flash_error_t efl_lld_read(void *instance, flash_offset_t offset,
size_t n, uint8_t *rp);
flash_error_t efl_lld_program(void *instance, flash_offset_t offset,
size_t n, const uint8_t *pp);
flash_error_t efl_lld_start_erase_all(void *instance);
flash_error_t efl_lld_start_erase_sector(void *instance,
flash_sector_t sector);
flash_error_t efl_lld_query_erase(void *instance, uint32_t *wait_time);
flash_error_t efl_lld_verify_erase(void *instance, flash_sector_t sector);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_EFL == TRUE */
#endif /* HAL_EFL_LLD_H */
/** @} */

3
os/hal/ports/STM32/STM32F0xx/platform.mk
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@ -1,7 +1,8 @@
# Required platform files.
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/stm32_isr.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c
$(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_efl_lld.c \
# Required include directories.
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \

66
os/hal/ports/STM32/STM32F0xx/stm32_registry.h
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@ -1,5 +1,5 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2021 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@ -129,6 +129,14 @@
#define STM32_EXTI_NUM_LINES 20
#define STM32_EXTI_IMR1_MASK 0xFFF50000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 4U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 16 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -446,6 +454,14 @@
#define STM32_EXTI_NUM_LINES 32
#define STM32_EXTI_IMR1_MASK 0x0FF40000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 4U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 16 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -663,6 +679,14 @@
#define STM32_EXTI_NUM_LINES 32
#define STM32_EXTI_IMR1_MASK 0x7FF40000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 4U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 16 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -888,6 +912,14 @@
#define STM32_EXTI_NUM_LINES 32
#define STM32_EXTI_IMR1_MASK 0x7FF40000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 4U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 16 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -1122,6 +1154,14 @@
#define STM32_EXTI_NUM_LINES 32
#define STM32_EXTI_IMR1_MASK 0x0F940000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 4U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 16 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -1364,6 +1404,14 @@
#define STM32_EXTI_NUM_LINES 32
#define STM32_EXTI_IMR1_MASK 0x7F840000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 2U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 64 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -1636,6 +1684,14 @@
#define STM32_EXTI_NUM_LINES 32
#define STM32_EXTI_IMR1_MASK 0x7F840000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 2U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 64 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
@ -1924,6 +1980,14 @@
#define STM32_EXTI_NUM_LINES 32
#define STM32_EXTI_IMR1_MASK 0x7F840000U
/* Flash attributes.*/
#define STM32_FLASH_NUMBER_OF_BANKS 1
#define STM32_FLASH_SECTOR_SIZE 4096U
#define STM32_FLASH_LINE_SIZE 2U
#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
#define STM32_FLASH_SECTORS_PER_BANK 64 /* Maximum, can be redefined.*/
#endif
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE