Removed external.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13590 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
323de2c526
commit
c0d0ec896d
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@ -0,0 +1,36 @@
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|||
[#ftl]
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||||
[#--
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||||
ChibiOS/RT - Copyright (C) 2006..2018 Giovanni Di Sirio
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||||
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||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
--]
|
||||
|
||||
[#--
|
||||
-- Emits the ChibiOS standard license text.
|
||||
-- The license text is indented by 4 spaces.
|
||||
--]
|
||||
[#macro EmitLicenseAsText]
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
[/#macro]
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||||
|
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@ -0,0 +1,126 @@
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[#ftl]
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||||
[#--
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||||
ChibiOS/RT - Copyright (C) 2006..2018 Giovanni Di Sirio
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||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
--]
|
||||
|
||||
[#--
|
||||
-- Returns the trimmed text "s" making sure it is terminated by a dot.
|
||||
-- The empty string is always returned as an empty string, the dot is not
|
||||
-- added.
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||||
--]
|
||||
[#function WithDot s]
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||||
[#local s = s?trim /]
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||||
[#if s == ""]
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[#return s /]
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||||
[/#if]
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||||
[#if s?ends_with(".")]
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[#return s /]
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[/#if]
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[#return s + "." /]
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[/#function]
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||||
|
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[#--
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||||
-- Returns the trimmed text "s" making sure it is not terminated by a dot.
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||||
--]
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||||
[#function WithoutDot s]
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||||
[#local s = s?trim /]
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||||
[#if s?ends_with(".")]
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[#return s?substring(0, s?length - 1) /]
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[/#if]
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[#return s /]
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||||
[/#function]
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||||
|
||||
[#--
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||||
-- Returns the trimmed text "s" making sure it is terminated by a dot if the
|
||||
-- text is composed of multiple phrases, if the text is composed of a single
|
||||
-- phrase then makes sure it is *not* terminated by a dot.
|
||||
-- A phrase is recognized by the pattern ". " into the text.
|
||||
-- The empty string is always returned as an empty string, the dot is never
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-- added.
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--]
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||||
[#function IntelligentDot s]
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[#local s = s?trim /]
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[#if s?contains(". ")]
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[#return WithDot(s) /]
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[/#if]
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[#return WithoutDot(s) /]
|
||||
[/#function]
|
||||
|
||||
[#--
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||||
-- Formats a text string in a sequence of strings no longer than "len" (first
|
||||
-- line) or "lenn" (subsequent lines).
|
||||
-- White spaces are normalized between words, sequences of white spaces become
|
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-- a single space.
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--]
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[#function StringToText len1 lenn s]
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[#local words=s?word_list /]
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[#local line="" /]
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[#local lines=[] /]
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[#list words as word]
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[#if lines?size == 0]
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[#local len = len1 /]
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[#else]
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[#local len = lenn /]
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[/#if]
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[#if (line?length + word?length + 1 > len)]
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[#local lines = lines + [line?trim] /]
|
||||
[#local line = word + " " /]
|
||||
[#else]
|
||||
[#local line = line + word + " " /]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#if line != ""]
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||||
[#local lines = lines + [line?trim] /]
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||||
[/#if]
|
||||
[#return lines /]
|
||||
[/#function]
|
||||
|
||||
[#--
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||||
-- Emits a string "s" as a formatted text, the first line is prefixed by the
|
||||
-- "p1" parameter, subsequent lines are prefixed by the "pn" paramenter.
|
||||
-- Emitted lines are no longer than the "len" parameter.
|
||||
-- White spaces are normalized between words.
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||||
--]
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[#macro FormatStringAsText p1 pn s len]
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||||
[#local lines = StringToText(len - p1?length, len - pn?length, s) /]
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||||
[#list lines as line]
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[#if line_index == 0]
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||||
${p1}${line}
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[#else]
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${pn}${line}
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||||
[/#if]
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||||
[/#list]
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||||
[/#macro]
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||||
|
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[#--
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||||
-- Emits a C function body code reformatting the indentation using the
|
||||
-- specified tab size and line prefix.
|
||||
--]
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||||
[#macro EmitIndentedCCode start tab ccode]
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||||
[#assign lines = ccode?string?split("^", "rm") /]
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||||
[#list lines as line]
|
||||
[#if (line_index > 0) || (line?trim?length > 0)]
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[#if line?trim?length > 0]
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||||
[#if line[0] == "#"]
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||||
${line?chop_linebreak}
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[#else]
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||||
${start + line?chop_linebreak}
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[/#if]
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[#else]
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||||
|
||||
[/#if]
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||||
[/#if]
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||||
[/#list]
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[/#macro]
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@ -0,0 +1,327 @@
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|||
[#ftl]
|
||||
[#--
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||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
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||||
|
||||
This file is part of ChibiOS.
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||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
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||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
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||||
--]
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||||
[@pp.dropOutputFile /]
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[#import "/@lib/libutils.ftl" as utils /]
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[#import "/@lib/liblicense.ftl" as license /]
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[@pp.changeOutputFile name="board.c" /]
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||||
/*
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||||
[@license.EmitLicenseAsText /]
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||||
*/
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||||
|
||||
/*
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* This file has been automatically generated using ChibiStudio board
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||||
* generator plugin. Do not edit manually.
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*/
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||||
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[#list doc1.board.headers.header as header]
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#include "${header[0]?string?trim}"
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[/#list]
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#include "hal.h"
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[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
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#include "stm32_gpio.h"
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[/#if]
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||||
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/*===========================================================================*/
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||||
/* Driver local definitions. */
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||||
/*===========================================================================*/
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||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
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||||
/*===========================================================================*/
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||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
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||||
/*===========================================================================*/
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||||
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[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
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/**
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* @brief Type of STM32 GPIO port setup.
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*/
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typedef struct {
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uint32_t moder;
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uint32_t otyper;
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uint32_t ospeedr;
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uint32_t pupdr;
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uint32_t odr;
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uint32_t afrl;
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uint32_t afrh;
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} gpio_setup_t;
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/**
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* @brief Type of STM32 GPIO initialization data.
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*/
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typedef struct {
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#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
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gpio_setup_t PAData;
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#endif
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#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
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gpio_setup_t PBData;
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#endif
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#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
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gpio_setup_t PCData;
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#endif
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#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
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gpio_setup_t PDData;
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#endif
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#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
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gpio_setup_t PEData;
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#endif
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#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
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gpio_setup_t PFData;
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#endif
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#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
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gpio_setup_t PGData;
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#endif
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#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
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gpio_setup_t PHData;
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#endif
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#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
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gpio_setup_t PIData;
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||||
#endif
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||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
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gpio_setup_t PJData;
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||||
#endif
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||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
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||||
gpio_setup_t PKData;
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||||
#endif
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||||
} gpio_config_t;
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||||
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||||
[/#if]
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||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
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||||
/**
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||||
* @brief STM32 GPIO static initialization data.
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||||
*/
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||||
static const gpio_config_t gpio_default_config = {
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||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
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||||
/**
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||||
* @brief PAL setup.
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||||
* @details Digital I/O ports static configuration as defined in @p board.h.
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||||
* This variable is used by the HAL when initializing the PAL driver.
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||||
*/
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||||
const PALConfig pal_default_config = {
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||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
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||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
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||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
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||||
#endif
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||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
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||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
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||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
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||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 3U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 3U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB1(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
[#if doc1.board.ethernet_phy[0]??]
|
||||
|
||||
/*
|
||||
* Ethernet PHY type.
|
||||
*/
|
||||
#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]}
|
||||
[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"]
|
||||
#define BOARD_PHY_RMII
|
||||
[/#if]
|
||||
[/#if]
|
||||
[#if doc1.board.usb_phy[0]?? && doc1.board.usb_phy.bus_type[0]?string == "ULPI"]
|
||||
|
||||
/*
|
||||
* The board has an ULPI USB PHY.
|
||||
*/
|
||||
#define BOARD_OTG2_USES_ULPI
|
||||
[/#if]
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* Board voltages.
|
||||
* Required for performance limits calculation.
|
||||
*/
|
||||
#define STM32_VDD ${doc1.board.clocks.@VDD[0]}U
|
||||
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB1(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,391 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
[#if doc1.board.ethernet_phy[0]??]
|
||||
|
||||
/*
|
||||
* Ethernet PHY type.
|
||||
*/
|
||||
#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]}
|
||||
[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"]
|
||||
#define BOARD_PHY_RMII
|
||||
[/#if]
|
||||
[/#if]
|
||||
[#if doc1.board.usb_phy[0]?? && doc1.board.usb_phy.bus_type[0]?string == "ULPI"]
|
||||
|
||||
/*
|
||||
* The board has an ULPI USB PHY.
|
||||
*/
|
||||
#define BOARD_OTG2_USES_ULPI
|
||||
[/#if]
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 3U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* Board voltages.
|
||||
* Required for performance limits calculation.
|
||||
*/
|
||||
#define STM32_VDD ${doc1.board.clocks.@VDD[0]}U
|
||||
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetIOP(STM32_GPIO_EN_MASK);
|
||||
rccEnableIOP(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note Add your board-specific code, if any.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 11U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB2(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
stm32_gpio_init();
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,393 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
[#if doc1.board.ethernet_phy[0]??]
|
||||
|
||||
/*
|
||||
* Ethernet PHY type.
|
||||
*/
|
||||
#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]}
|
||||
[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"]
|
||||
#define BOARD_PHY_RMII
|
||||
[/#if]
|
||||
[/#if]
|
||||
[#if doc1.board.usb_phy[0]?? && doc1.board.usb_phy.bus_type[0]?string == "ULPI"]
|
||||
|
||||
/*
|
||||
* The board has an ULPI USB PHY.
|
||||
*/
|
||||
#define BOARD_OTG2_USES_ULPI
|
||||
[/#if]
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 3U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* Board voltages.
|
||||
* Required for performance limits calculation.
|
||||
*/
|
||||
#define STM32_VDD ${doc1.board.clocks.@VDD[0]}U
|
||||
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
#define PIN_LOCKR_DISABLED(n) (0U << (n))
|
||||
#define PIN_LOCKR_ENABLED(n) (1U << (n))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB4(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB4(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,385 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
[#if doc1.board.ethernet_phy[0]??]
|
||||
|
||||
/*
|
||||
* Ethernet PHY type.
|
||||
*/
|
||||
#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]}
|
||||
[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"]
|
||||
#define BOARD_PHY_RMII
|
||||
[/#if]
|
||||
[/#if]
|
||||
[#if doc1.board.usb_phy[0]?? && doc1.board.usb_phy.bus_type[0]?string == "ULPI"]
|
||||
|
||||
/*
|
||||
* The board has an ULPI USB PHY.
|
||||
*/
|
||||
#define BOARD_OTG2_USES_ULPI
|
||||
[/#if]
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 3U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetIOP(STM32_GPIO_EN_MASK);
|
||||
rccEnableIOP(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 11U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
uint32_t ascr;
|
||||
uint32_t lockr;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
gpio_setup_t PIData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
|
||||
gpio_setup_t PJData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
|
||||
gpio_setup_t PKData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
|
||||
VAL_GPIOA_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
|
||||
VAL_GPIOB_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
|
||||
VAL_GPIOC_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
|
||||
VAL_GPIOD_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
|
||||
VAL_GPIOE_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
|
||||
VAL_GPIOF_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
|
||||
VAL_GPIOG_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
|
||||
VAL_GPIOH_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
|
||||
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
|
||||
VAL_GPIOI_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
|
||||
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
|
||||
VAL_GPIOJ_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
|
||||
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
|
||||
VAL_GPIOK_LOCKR}
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->ASCR = config->ascr;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
gpiop->LOCKR = config->lockr;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB2(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI
|
||||
gpio_init(GPIOI, &gpio_default_config.PIData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOJ
|
||||
gpio_init(GPIOJ, &gpio_default_config.PJData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOK
|
||||
gpio_init(GPIOK, &gpio_default_config.PKData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,449 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
[#if doc1.board.ethernet_phy[0]??]
|
||||
|
||||
/*
|
||||
* Ethernet PHY type.
|
||||
*/
|
||||
#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]}
|
||||
[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"]
|
||||
#define BOARD_PHY_RMII
|
||||
[/#if]
|
||||
[/#if]
|
||||
[#if doc1.board.usb_phy[0]?? && doc1.board.usb_phy.bus_type[0]?string == "ULPI"]
|
||||
|
||||
/*
|
||||
* The board has an ULPI USB PHY.
|
||||
*/
|
||||
#define BOARD_OTG2_USES_ULPI
|
||||
[/#if]
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 3U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* Board voltages.
|
||||
* Required for performance limits calculation.
|
||||
*/
|
||||
#define STM32_VDD ${doc1.board.clocks.@VDD[0]}U
|
||||
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
#define PIN_ASCR_DISABLED(n) (0U << (n))
|
||||
#define PIN_ASCR_ENABLED(n) (1U << (n))
|
||||
#define PIN_LOCKR_DISABLED(n) (0U << (n))
|
||||
#define PIN_LOCKR_ENABLED(n) (1U << (n))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ASCR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign switch = pin.@AnalogSwitch[0] /]
|
||||
[#if switch == "Disabled"]
|
||||
[#assign out = "PIN_ASCR_DISABLED(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ASCR_ENABLED(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ASCR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating LOCKR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign lock = pin.@PinLock[0] /]
|
||||
[#if lock == "Disabled"]
|
||||
[#assign out = "PIN_LOCKR_DISABLED(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_LOCKR_ENABLED(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_LOCKR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.c" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
[#list doc1.board.headers.header as header]
|
||||
#include "${header[0]?string?trim}"
|
||||
[/#list]
|
||||
#include "hal.h"
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
#include "stm32_gpio.h"
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief Type of STM32 GPIO port setup.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t moder;
|
||||
uint32_t otyper;
|
||||
uint32_t ospeedr;
|
||||
uint32_t pupdr;
|
||||
uint32_t odr;
|
||||
uint32_t afrl;
|
||||
uint32_t afrh;
|
||||
uint32_t lockr;
|
||||
} gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief Type of STM32 GPIO initialization data.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
gpio_setup_t PHData;
|
||||
#endif
|
||||
} gpio_config_t;
|
||||
|
||||
[/#if]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
/**
|
||||
* @brief STM32 GPIO static initialization data.
|
||||
*/
|
||||
static const gpio_config_t gpio_default_config = {
|
||||
[#else]
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
const PALConfig pal_default_config = {
|
||||
[/#if]
|
||||
#if STM32_HAS_GPIOA
|
||||
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
|
||||
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
|
||||
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
|
||||
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
|
||||
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
|
||||
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
|
||||
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
|
||||
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_LOCKR},
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
|
||||
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_LOCKR},
|
||||
#endif
|
||||
};
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "4.0.x"]
|
||||
#endif
|
||||
[/#if]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
|
||||
|
||||
gpiop->OTYPER = config->otyper;
|
||||
gpiop->OSPEEDR = config->ospeedr;
|
||||
gpiop->PUPDR = config->pupdr;
|
||||
gpiop->ODR = config->odr;
|
||||
gpiop->AFRL = config->afrl;
|
||||
gpiop->AFRH = config->afrh;
|
||||
gpiop->MODER = config->moder;
|
||||
gpiop->LOCKR = config->lockr;
|
||||
}
|
||||
|
||||
static void stm32_gpio_init(void) {
|
||||
|
||||
/* Enabling GPIO-related clocks, the mask comes from the
|
||||
registry header file.*/
|
||||
rccResetAHB2(STM32_GPIO_EN_MASK);
|
||||
rccEnableAHB2(STM32_GPIO_EN_MASK, true);
|
||||
|
||||
/* Initializing all the defined GPIO ports.*/
|
||||
#if STM32_HAS_GPIOA
|
||||
gpio_init(GPIOA, &gpio_default_config.PAData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB
|
||||
gpio_init(GPIOB, &gpio_default_config.PBData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC
|
||||
gpio_init(GPIOC, &gpio_default_config.PCData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD
|
||||
gpio_init(GPIOD, &gpio_default_config.PDData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE
|
||||
gpio_init(GPIOE, &gpio_default_config.PEData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF
|
||||
gpio_init(GPIOF, &gpio_default_config.PFData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG
|
||||
gpio_init(GPIOG, &gpio_default_config.PGData);
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH
|
||||
gpio_init(GPIOH, &gpio_default_config.PHData);
|
||||
#endif
|
||||
}
|
||||
|
||||
[/#if]
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Early initialization code.
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
* @details GPIO ports and system clocks are initialized before everything
|
||||
* else.
|
||||
[#else]
|
||||
* @details System clocks are initialized before everything else.
|
||||
[/#if]
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim != "4.0.x"]
|
||||
stm32_gpio_init();
|
||||
[/#if]
|
||||
stm32_clock_init();
|
||||
[#if doc1.board.board_functions.__early_init[0]??]
|
||||
${doc1.board.board_functions.__early_init[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
||||
#if HAL_USE_SDC || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief SDC card detection.
|
||||
*/
|
||||
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SDC card write protection detection.
|
||||
*/
|
||||
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
|
||||
[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.sdc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)sdcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif /* HAL_USE_SDC */
|
||||
|
||||
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief MMC_SPI card detection.
|
||||
*/
|
||||
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_card_inserted[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return true;
|
||||
[/#if]
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MMC_SPI card write protection detection.
|
||||
*/
|
||||
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
|
||||
[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??]
|
||||
${doc1.board.board_functions.mmc_lld_is_write_protected[0]}
|
||||
[#else]
|
||||
|
||||
(void)mmcp;
|
||||
/* CHTODO: Fill the implementation.*/
|
||||
return false;
|
||||
[/#if]
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Board-specific initialization code.
|
||||
* @note You can add your board-specific code here.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
|
||||
[#if doc1.board.board_functions.boardInit[0]??]
|
||||
${doc1.board.board_functions.boardInit[0]}
|
||||
[/#if]
|
||||
}
|
||||
|
|
@ -0,0 +1,420 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="board.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file has been automatically generated using ChibiStudio board
|
||||
* generator plugin. Do not edit manually.
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H
|
||||
#define BOARD_H
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Setup for ${doc1.board.board_name[0]} board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_${doc1.board.board_id[0]}
|
||||
#define BOARD_NAME "${doc1.board.board_name[0]}"
|
||||
[#if doc1.board.ethernet_phy[0]??]
|
||||
|
||||
/*
|
||||
* Ethernet PHY type.
|
||||
*/
|
||||
#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]}
|
||||
[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"]
|
||||
#define BOARD_PHY_RMII
|
||||
[/#if]
|
||||
[/#if]
|
||||
[#if doc1.board.usb_phy[0]?? && doc1.board.usb_phy.bus_type[0]?string == "ULPI"]
|
||||
|
||||
/*
|
||||
* The board has an ULPI USB PHY.
|
||||
*/
|
||||
#define BOARD_OTG2_USES_ULPI
|
||||
[/#if]
|
||||
|
||||
/*
|
||||
* Board oscillators-related settings.
|
||||
[#if doc1.board.clocks.@LSEFrequency[0]?number == 0]
|
||||
* NOTE: LSE not fitted.
|
||||
[/#if]
|
||||
[#if doc1.board.clocks.@HSEFrequency[0]?number == 0]
|
||||
* NOTE: HSE not fitted.
|
||||
[/#if]
|
||||
*/
|
||||
#if !defined(STM32_LSECLK)
|
||||
#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@LSEBypass[0]?string == "true"]
|
||||
#define STM32_LSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number}U << 3U)
|
||||
|
||||
#if !defined(STM32_HSECLK)
|
||||
#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]}U
|
||||
#endif
|
||||
|
||||
[#if doc1.board.clocks.@HSEBypass[0]?string == "true"]
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
[/#if]
|
||||
/*
|
||||
* Board voltages.
|
||||
* Required for performance limits calculation.
|
||||
*/
|
||||
#define STM32_VDD ${doc1.board.clocks.@VDD[0]}U
|
||||
|
||||
/*
|
||||
* MCU type as defined in the ST header.
|
||||
*/
|
||||
#define ${doc1.board.subtype[0]}
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
#define ${(port_name + "_" + pin_name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[#else]
|
||||
[#list names as name]
|
||||
#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string}U
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*
|
||||
* IO lines assignments.
|
||||
*/
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size > 0]
|
||||
[#list names as name]
|
||||
#define LINE_${name?right_pad(22, " ")} PAL_LINE(${port_name}, ${pin_index?string}U)
|
||||
[/#list]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[/#list]
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
|
||||
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
|
||||
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
|
||||
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
|
||||
#define PIN_ODR_LOW(n) (0U << (n))
|
||||
#define PIN_ODR_HIGH(n) (1U << (n))
|
||||
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
|
||||
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
|
||||
#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
|
||||
#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
|
||||
#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
|
||||
#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
|
||||
#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
|
||||
#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
|
||||
#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
|
||||
#define PIN_LOCKR_DISABLED(n) (0U << (n))
|
||||
#define PIN_LOCKR_ENABLED(n) (1U << (n))
|
||||
|
||||
[#list doc1.board.ports.* as port]
|
||||
[#assign port_name = port?node_name?upper_case /]
|
||||
/*
|
||||
* ${port_name} setup:
|
||||
*
|
||||
[#-- Generating pin descriptions inside the comment.--]
|
||||
[#list port.* as pin]
|
||||
[#assign pin_name = pin?node_name?upper_case /]
|
||||
[#assign name = pin.@ID[0]?string?trim /]
|
||||
[#if name?length == 0]
|
||||
[#assign name = pin_name /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#assign alternate = pin.@Alternate[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign desc = mode + " " + resistor /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign desc = mode + " " + type + " " + speed /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign desc = mode + " " + alternate /]
|
||||
[#else]
|
||||
[#assign desc = "Analog" /]
|
||||
[/#if]
|
||||
* P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}).
|
||||
[/#list]
|
||||
*/
|
||||
[#--
|
||||
-- Generating MODER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign mode = pin.@Mode[0] /]
|
||||
[#if mode == "Input"]
|
||||
[#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Output"]
|
||||
[#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /]
|
||||
[#elseif mode == "Alternate"]
|
||||
[#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_MODER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating OTYPER register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign type = pin.@Type[0] /]
|
||||
[#if type == "PushPull"]
|
||||
[#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating SPEEDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign speed = pin.@Speed[0] /]
|
||||
[#if speed == "Minimum"]
|
||||
[#assign out = "PIN_OSPEED_VERYLOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "Low"]
|
||||
[#assign out = "PIN_OSPEED_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#elseif speed == "High"]
|
||||
[#assign out = "PIN_OSPEED_MEDIUM(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_OSPEED_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating PUPDR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign resistor = pin.@Resistor[0] /]
|
||||
[#if resistor == "Floating"]
|
||||
[#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /]
|
||||
[#elseif resistor == "PullUp"]
|
||||
[#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating ODR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign level = pin.@Level[0] /]
|
||||
[#if level == "Low"]
|
||||
[#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_ODR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating AFRx registers values.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign alternate = pin.@Alternate[0]?trim /]
|
||||
[#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + "U)" /]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRL (" + out /]
|
||||
[#elseif pin_index == 8]
|
||||
[#assign line = "#define VAL_" + port_name + "_AFRH (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if (pin_index == 7) || (pin_index == 15)]
|
||||
${line + ")"}
|
||||
[#else]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#--
|
||||
-- Generating LOCKR register value.
|
||||
--]
|
||||
[#list port.* as pin]
|
||||
[#assign names = pin.@ID[0]?string?word_list /]
|
||||
[#if names?size == 0]
|
||||
[#assign name = pin?node_name?upper_case /]
|
||||
[#else]
|
||||
[#assign name = names[0] /]
|
||||
[/#if]
|
||||
[#assign lock = pin.@PinLock[0] /]
|
||||
[#if lock == "Disabled"]
|
||||
[#assign out = "PIN_LOCKR_DISABLED(" + port_name + "_" + name + ")" /]
|
||||
[#else]
|
||||
[#assign out = "PIN_LOCKR_ENABLED(" + port_name + "_" + name + ")" /]
|
||||
[/#if]
|
||||
[#if pin_index == 0]
|
||||
[#assign line = "#define VAL_" + port_name + "_LOCKR (" + out /]
|
||||
[#else]
|
||||
[#assign line = " " + out /]
|
||||
[/#if]
|
||||
[#if pin_index < 15]
|
||||
${(line + " |")?right_pad(76, " ") + "\\"}
|
||||
[#else]
|
||||
${line + ")"}
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
||||
[/#list]
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[@pp.changeOutputFile name="board.mk" /]
|
||||
[#if doc1.board.configuration_settings.board_files_path[0]??]
|
||||
[#assign path = doc1.board.configuration_settings.board_files_path[0]?string?trim /]
|
||||
[#if !path?ends_with("/")]
|
||||
[#assign path = path + "/"]
|
||||
[/#if]
|
||||
[#else]
|
||||
[#if doc1.board.configuration_settings.hal_version[0]?trim == "2.6.x"]
|
||||
[#assign path = "$(CHIBIOS)/boards/" /]
|
||||
[#else]
|
||||
[#assign path = "$(CHIBIOS)/os/hal/boards/" /]
|
||||
[/#if]
|
||||
[/#if]
|
||||
# List of all the board related files.
|
||||
BOARDSRC = ${path}${doc1.board.board_id[0]}/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${path}${doc1.board.board_id[0]}
|
||||
|
||||
# Shared variables
|
||||
ALLCSRC += $(BOARDSRC)
|
||||
ALLINC += $(BOARDINC)
|
||||
|
|
@ -0,0 +1,490 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="chconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file nil/templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup NIL_CONFIG
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef CHCONF_H
|
||||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_NIL_CONF_
|
||||
#define _CHIBIOS_NIL_CONF_VER_4_0_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel parameters and options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Maximum number of user threads in the application.
|
||||
* @note This number is not inclusive of the idle thread which is
|
||||
* implicitly handled.
|
||||
* @note Set this value to be exactly equal to the number of threads you
|
||||
* will use or you would be wasting RAM and cycles.
|
||||
* @note This values also defines the number of available priorities
|
||||
* (0..CH_CFG_MAX_THREADS-1).
|
||||
*/
|
||||
#if !defined(CH_CFG_MAX_THREADS)
|
||||
#define CH_CFG_MAX_THREADS ${doc.CH_CFG_MAX_THREADS!"4"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Auto starts threads when @p chSysInit() is invoked.
|
||||
*/
|
||||
#if !defined(CH_CFG_AUTOSTART_THREADS)
|
||||
#define CH_CFG_AUTOSTART_THREADS ${doc.CH_CFG_AUTOSTART_THREADS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name System timer settings
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System time counter resolution.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_RESOLUTION)
|
||||
#define CH_CFG_ST_RESOLUTION ${doc.CH_CFG_ST_RESOLUTION!"32"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System tick frequency.
|
||||
* @note This value together with the @p CH_CFG_ST_RESOLUTION
|
||||
* option defines the maximum amount of time allowed for
|
||||
* timeouts.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_FREQUENCY)
|
||||
#define CH_CFG_ST_FREQUENCY ${doc.CH_CFG_ST_FREQUENCY!"1000"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
* periodic tick. This value represents the minimum number
|
||||
* of ticks that is safe to specify in a timeout directive.
|
||||
* The value one is not valid, timeouts are rounded up to
|
||||
* this value.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_TIMEDELTA)
|
||||
#define CH_CFG_ST_TIMEDELTA ${doc.CH_CFG_ST_TIMEDELTA!"2"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Subsystem options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Threads synchronization APIs.
|
||||
* @details If enabled then the @p chThdWait() function is included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_WAITEXIT)
|
||||
#define CH_CFG_USE_WAITEXIT ${doc.CH_CFG_USE_WAITEXIT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Semaphores APIs.
|
||||
* @details If enabled then the Semaphores APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_SEMAPHORES)
|
||||
#define CH_CFG_USE_SEMAPHORES ${doc.CH_CFG_USE_SEMAPHORES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Mutexes APIs.
|
||||
* @details If enabled then the mutexes APIs are included in the kernel.
|
||||
*
|
||||
* @note Feature not currently implemented.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MUTEXES)
|
||||
#define CH_CFG_USE_MUTEXES ${doc.CH_CFG_USE_MUTEXES!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs.
|
||||
* @details If enabled then the event flags APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_EVENTS)
|
||||
#define CH_CFG_USE_EVENTS ${doc.CH_CFG_USE_EVENTS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages APIs.
|
||||
* @details If enabled then the synchronous messages APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MESSAGES)
|
||||
#define CH_CFG_USE_MESSAGES ${doc.CH_CFG_USE_MESSAGES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name OSLIB options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Mailboxes APIs.
|
||||
* @details If enabled then the asynchronous messages (mailboxes) APIs are
|
||||
* included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MAILBOXES)
|
||||
#define CH_CFG_USE_MAILBOXES ${doc.CH_CFG_USE_MAILBOXES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MEMCORE)
|
||||
#define CH_CFG_USE_MEMCORE ${doc.CH_CFG_USE_MEMCORE!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Managed RAM size.
|
||||
* @details Size of the RAM area to be managed by the OS. If set to zero
|
||||
* then the whole available RAM is used. The core memory is made
|
||||
* available to the heap allocator and/or can be used directly through
|
||||
* the simplified core memory allocator.
|
||||
*
|
||||
* @note In order to let the OS manage the whole RAM the linker script must
|
||||
* provide the @p __heap_base__ and @p __heap_end__ symbols.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE.
|
||||
*/
|
||||
#if !defined(CH_CFG_MEMCORE_SIZE)
|
||||
#define CH_CFG_MEMCORE_SIZE ${doc.CH_CFG_MEMCORE_SIZE!"0"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Heap Allocator APIs.
|
||||
* @details If enabled then the memory heap allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_HEAP)
|
||||
#define CH_CFG_USE_HEAP ${doc.CH_CFG_USE_HEAP!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Memory Pools Allocator APIs.
|
||||
* @details If enabled then the memory pools allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MEMPOOLS)
|
||||
#define CH_CFG_USE_MEMPOOLS ${doc.CH_CFG_USE_MEMPOOLS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_OBJ_FIFOS)
|
||||
#define CH_CFG_USE_OBJ_FIFOS ${doc.CH_CFG_USE_OBJ_FIFOS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Pipes APIs.
|
||||
* @details If enabled then the pipes APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_PIPES)
|
||||
#define CH_CFG_USE_PIPES ${doc.CH_CFG_USE_PIPES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Objects Caches APIs.
|
||||
* @details If enabled then the objects caches APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_OBJ_CACHES)
|
||||
#define CH_CFG_USE_OBJ_CACHES ${doc.CH_CFG_USE_OBJ_CACHES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delegate threads APIs.
|
||||
* @details If enabled then the delegate threads APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_DELEGATES)
|
||||
#define CH_CFG_USE_DELEGATES ${doc.CH_CFG_USE_DELEGATES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Jobs Queues APIs.
|
||||
* @details If enabled then the jobs queues APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_JOBS)
|
||||
#define CH_CFG_USE_JOBS ${doc.CH_CFG_USE_JOBS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_FACTORY)
|
||||
#define CH_CFG_USE_FACTORY ${doc.CH_CFG_USE_FACTORY!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH ${doc.CH_CFG_FACTORY_MAX_NAMES_LENGTH!"8"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY ${doc.CH_CFG_FACTORY_OBJECTS_REGISTRY!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS ${doc.CH_CFG_FACTORY_GENERIC_BUFFERS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
|
||||
#define CH_CFG_FACTORY_SEMAPHORES ${doc.CH_CFG_FACTORY_SEMAPHORES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_MAILBOXES)
|
||||
#define CH_CFG_FACTORY_MAILBOXES ${doc.CH_CFG_FACTORY_MAILBOXES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS ${doc.CH_CFG_FACTORY_OBJ_FIFOS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for Pipes.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_PIPES)
|
||||
#define CH_CFG_FACTORY_PIPES ${doc.CH_CFG_FACTORY_PIPES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Debug option, kernel statistics.
|
||||
*
|
||||
* @note Feature not currently implemented.
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_STATISTICS)
|
||||
#define CH_DBG_STATISTICS ${doc.CH_DBG_STATISTICS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, system state check.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK ${doc.CH_DBG_SYSTEM_STATE_CHECK!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, parameters checks.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_CHECKS)
|
||||
#define CH_DBG_ENABLE_CHECKS ${doc.CH_DBG_ENABLE_CHECKS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System assertions.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_ASSERTS)
|
||||
#define CH_DBG_ENABLE_ASSERTS ${doc.CH_DBG_ENABLE_ASSERTS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Stack check.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
|
||||
#define CH_DBG_ENABLE_STACK_CHECK ${doc.CH_DBG_ENABLE_STACK_CHECK!"FALSE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel hooks
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK() { \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXT_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXT_INIT_HOOK(tr) { \
|
||||
/* Add custom threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) {}
|
||||
|
||||
/**
|
||||
* @brief Idle thread enter hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread leave hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System halt hook.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port-specific settings (override port settings defaulted in nilcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* CHCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,767 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="chconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file rt/templates/chconf.h
|
||||
* @brief Configuration file template.
|
||||
* @details A copy of this file must be placed in each project directory, it
|
||||
* contains the application specific kernel settings.
|
||||
*
|
||||
* @addtogroup config
|
||||
* @details Kernel related settings and hooks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef CHCONF_H
|
||||
#define CHCONF_H
|
||||
|
||||
#define _CHIBIOS_RT_CONF_
|
||||
#define _CHIBIOS_RT_CONF_VER_6_1_
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name System timers settings
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System time counter resolution.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_RESOLUTION)
|
||||
#define CH_CFG_ST_RESOLUTION ${doc.CH_CFG_ST_RESOLUTION!"32"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System tick frequency.
|
||||
* @details Frequency of the system timer that drives the system ticks. This
|
||||
* setting also defines the system tick time unit.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_FREQUENCY)
|
||||
#define CH_CFG_ST_FREQUENCY ${doc.CH_CFG_ST_FREQUENCY!"10000"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time intervals data size.
|
||||
* @note Allowed values are 16, 32 or 64 bits.
|
||||
*/
|
||||
#if !defined(CH_CFG_INTERVALS_SIZE)
|
||||
#define CH_CFG_INTERVALS_SIZE ${doc.CH_CFG_INTERVALS_SIZE!"32"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time types data size.
|
||||
* @note Allowed values are 16 or 32 bits.
|
||||
*/
|
||||
#if !defined(CH_CFG_TIME_TYPES_SIZE)
|
||||
#define CH_CFG_TIME_TYPES_SIZE ${doc.CH_CFG_TIME_TYPES_SIZE!"32"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Time delta constant for the tick-less mode.
|
||||
* @note If this value is zero then the system uses the classic
|
||||
* periodic tick. This value represents the minimum number
|
||||
* of ticks that is safe to specify in a timeout directive.
|
||||
* The value one is not valid, timeouts are rounded up to
|
||||
* this value.
|
||||
*/
|
||||
#if !defined(CH_CFG_ST_TIMEDELTA)
|
||||
#define CH_CFG_ST_TIMEDELTA ${doc.CH_CFG_ST_TIMEDELTA!"2"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel parameters and options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Round robin interval.
|
||||
* @details This constant is the number of system ticks allowed for the
|
||||
* threads before preemption occurs. Setting this value to zero
|
||||
* disables the preemption for threads with equal priority and the
|
||||
* round robin becomes cooperative. Note that higher priority
|
||||
* threads can still preempt, the kernel is always preemptive.
|
||||
* @note Disabling the round robin preemption makes the kernel more compact
|
||||
* and generally faster.
|
||||
* @note The round robin preemption is not supported in tickless mode and
|
||||
* must be set to zero in that case.
|
||||
*/
|
||||
#if !defined(CH_CFG_TIME_QUANTUM)
|
||||
#define CH_CFG_TIME_QUANTUM ${doc.CH_CFG_TIME_QUANTUM!"0"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Idle thread automatic spawn suppression.
|
||||
* @details When this option is activated the function @p chSysInit()
|
||||
* does not spawn the idle thread. The application @p main()
|
||||
* function becomes the idle thread and must implement an
|
||||
* infinite loop.
|
||||
*/
|
||||
#if !defined(CH_CFG_NO_IDLE_THREAD)
|
||||
#define CH_CFG_NO_IDLE_THREAD ${doc.CH_CFG_NO_IDLE_THREAD!"FALSE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Performance options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief OS optimization.
|
||||
* @details If enabled then time efficient rather than space efficient code
|
||||
* is used when two possible implementations exist.
|
||||
*
|
||||
* @note This is not related to the compiler optimization options.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_OPTIMIZE_SPEED)
|
||||
#define CH_CFG_OPTIMIZE_SPEED ${doc.CH_CFG_OPTIMIZE_SPEED!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Subsystem options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Time Measurement APIs.
|
||||
* @details If enabled then the time measurement APIs are included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_TM)
|
||||
#define CH_CFG_USE_TM ${doc.CH_CFG_USE_TM!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Threads registry APIs.
|
||||
* @details If enabled then the registry APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_REGISTRY)
|
||||
#define CH_CFG_USE_REGISTRY ${doc.CH_CFG_USE_REGISTRY!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Threads synchronization APIs.
|
||||
* @details If enabled then the @p chThdWait() function is included in
|
||||
* the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_WAITEXIT)
|
||||
#define CH_CFG_USE_WAITEXIT ${doc.CH_CFG_USE_WAITEXIT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Semaphores APIs.
|
||||
* @details If enabled then the Semaphores APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_SEMAPHORES)
|
||||
#define CH_CFG_USE_SEMAPHORES ${doc.CH_CFG_USE_SEMAPHORES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Semaphores queuing mode.
|
||||
* @details If enabled then the threads are enqueued on semaphores by
|
||||
* priority rather than in FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
|
||||
#define CH_CFG_USE_SEMAPHORES_PRIORITY ${doc.CH_CFG_USE_SEMAPHORES_PRIORITY!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Mutexes APIs.
|
||||
* @details If enabled then the mutexes APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MUTEXES)
|
||||
#define CH_CFG_USE_MUTEXES ${doc.CH_CFG_USE_MUTEXES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables recursive behavior on mutexes.
|
||||
* @note Recursive mutexes are heavier and have an increased
|
||||
* memory footprint.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
|
||||
#define CH_CFG_USE_MUTEXES_RECURSIVE ${doc.CH_CFG_USE_MUTEXES_RECURSIVE!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs.
|
||||
* @details If enabled then the conditional variables APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MUTEXES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_CONDVARS)
|
||||
#define CH_CFG_USE_CONDVARS ${doc.CH_CFG_USE_CONDVARS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Conditional Variables APIs with timeout.
|
||||
* @details If enabled then the conditional variables APIs with timeout
|
||||
* specification are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_CONDVARS.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
|
||||
#define CH_CFG_USE_CONDVARS_TIMEOUT ${doc.CH_CFG_USE_CONDVARS_TIMEOUT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs.
|
||||
* @details If enabled then the event flags APIs are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_EVENTS)
|
||||
#define CH_CFG_USE_EVENTS ${doc.CH_CFG_USE_EVENTS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Events Flags APIs with timeout.
|
||||
* @details If enabled then the events APIs with timeout specification
|
||||
* are included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_EVENTS.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
|
||||
#define CH_CFG_USE_EVENTS_TIMEOUT ${doc.CH_CFG_USE_EVENTS_TIMEOUT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages APIs.
|
||||
* @details If enabled then the synchronous messages APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MESSAGES)
|
||||
#define CH_CFG_USE_MESSAGES ${doc.CH_CFG_USE_MESSAGES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Synchronous Messages queuing mode.
|
||||
* @details If enabled then messages are served by priority rather than in
|
||||
* FIFO order.
|
||||
*
|
||||
* @note The default is @p FALSE. Enable this if you have special
|
||||
* requirements.
|
||||
* @note Requires @p CH_CFG_USE_MESSAGES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
|
||||
#define CH_CFG_USE_MESSAGES_PRIORITY ${doc.CH_CFG_USE_MESSAGES_PRIORITY!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Dynamic Threads APIs.
|
||||
* @details If enabled then the dynamic threads creation APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_WAITEXIT.
|
||||
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_DYNAMIC)
|
||||
#define CH_CFG_USE_DYNAMIC ${doc.CH_CFG_USE_DYNAMIC!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name OSLIB options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Mailboxes APIs.
|
||||
* @details If enabled then the asynchronous messages (mailboxes) APIs are
|
||||
* included in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_SEMAPHORES.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MAILBOXES)
|
||||
#define CH_CFG_USE_MAILBOXES ${doc.CH_CFG_USE_MAILBOXES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Core Memory Manager APIs.
|
||||
* @details If enabled then the core memory manager APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MEMCORE)
|
||||
#define CH_CFG_USE_MEMCORE ${doc.CH_CFG_USE_MEMCORE!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Managed RAM size.
|
||||
* @details Size of the RAM area to be managed by the OS. If set to zero
|
||||
* then the whole available RAM is used. The core memory is made
|
||||
* available to the heap allocator and/or can be used directly through
|
||||
* the simplified core memory allocator.
|
||||
*
|
||||
* @note In order to let the OS manage the whole RAM the linker script must
|
||||
* provide the @p __heap_base__ and @p __heap_end__ symbols.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE.
|
||||
*/
|
||||
#if !defined(CH_CFG_MEMCORE_SIZE)
|
||||
#define CH_CFG_MEMCORE_SIZE ${doc.CH_CFG_MEMCORE_SIZE!"0"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Heap Allocator APIs.
|
||||
* @details If enabled then the memory heap allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
* @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
|
||||
* @p CH_CFG_USE_SEMAPHORES.
|
||||
* @note Mutexes are recommended.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_HEAP)
|
||||
#define CH_CFG_USE_HEAP ${doc.CH_CFG_USE_HEAP!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Memory Pools Allocator APIs.
|
||||
* @details If enabled then the memory pools allocator APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_MEMPOOLS)
|
||||
#define CH_CFG_USE_MEMPOOLS ${doc.CH_CFG_USE_MEMPOOLS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Objects FIFOs APIs.
|
||||
* @details If enabled then the objects FIFOs APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_OBJ_FIFOS)
|
||||
#define CH_CFG_USE_OBJ_FIFOS ${doc.CH_CFG_USE_OBJ_FIFOS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Pipes APIs.
|
||||
* @details If enabled then the pipes APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_PIPES)
|
||||
#define CH_CFG_USE_PIPES ${doc.CH_CFG_USE_PIPES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Objects Caches APIs.
|
||||
* @details If enabled then the objects caches APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_OBJ_CACHES)
|
||||
#define CH_CFG_USE_OBJ_CACHES ${doc.CH_CFG_USE_OBJ_CACHES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delegate threads APIs.
|
||||
* @details If enabled then the delegate threads APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_DELEGATES)
|
||||
#define CH_CFG_USE_DELEGATES ${doc.CH_CFG_USE_DELEGATES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Jobs Queues APIs.
|
||||
* @details If enabled then the jobs queues APIs are included
|
||||
* in the kernel.
|
||||
*
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_JOBS)
|
||||
#define CH_CFG_USE_JOBS ${doc.CH_CFG_USE_JOBS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Objects factory options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Objects Factory APIs.
|
||||
* @details If enabled then the objects factory APIs are included in the
|
||||
* kernel.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_CFG_USE_FACTORY)
|
||||
#define CH_CFG_USE_FACTORY ${doc.CH_CFG_USE_FACTORY!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Maximum length for object names.
|
||||
* @details If the specified length is zero then the name is stored by
|
||||
* pointer but this could have unintended side effects.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
|
||||
#define CH_CFG_FACTORY_MAX_NAMES_LENGTH ${doc.CH_CFG_FACTORY_MAX_NAMES_LENGTH!"8"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the registry of generic objects.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
|
||||
#define CH_CFG_FACTORY_OBJECTS_REGISTRY ${doc.CH_CFG_FACTORY_OBJECTS_REGISTRY!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for generic buffers.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
|
||||
#define CH_CFG_FACTORY_GENERIC_BUFFERS ${doc.CH_CFG_FACTORY_GENERIC_BUFFERS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for semaphores.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_SEMAPHORES)
|
||||
#define CH_CFG_FACTORY_SEMAPHORES ${doc.CH_CFG_FACTORY_SEMAPHORES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for mailboxes.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_MAILBOXES)
|
||||
#define CH_CFG_FACTORY_MAILBOXES ${doc.CH_CFG_FACTORY_MAILBOXES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for objects FIFOs.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
|
||||
#define CH_CFG_FACTORY_OBJ_FIFOS ${doc.CH_CFG_FACTORY_OBJ_FIFOS!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables factory for Pipes.
|
||||
*/
|
||||
#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
|
||||
#define CH_CFG_FACTORY_PIPES ${doc.CH_CFG_FACTORY_PIPES!"TRUE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Debug options
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Debug option, kernel statistics.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_STATISTICS)
|
||||
#define CH_DBG_STATISTICS ${doc.CH_DBG_STATISTICS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, system state check.
|
||||
* @details If enabled the correct call protocol for system APIs is checked
|
||||
* at runtime.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
|
||||
#define CH_DBG_SYSTEM_STATE_CHECK ${doc.CH_DBG_SYSTEM_STATE_CHECK!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, parameters checks.
|
||||
* @details If enabled then the checks on the API functions input
|
||||
* parameters are activated.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_CHECKS)
|
||||
#define CH_DBG_ENABLE_CHECKS ${doc.CH_DBG_ENABLE_CHECKS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, consistency checks.
|
||||
* @details If enabled then all the assertions in the kernel code are
|
||||
* activated. This includes consistency checks inside the kernel,
|
||||
* runtime anomalies and port-defined checks.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_ASSERTS)
|
||||
#define CH_DBG_ENABLE_ASSERTS ${doc.CH_DBG_ENABLE_ASSERTS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, trace buffer.
|
||||
* @details If enabled then the trace buffer is activated.
|
||||
*
|
||||
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#if !defined(CH_DBG_TRACE_MASK)
|
||||
#define CH_DBG_TRACE_MASK ${doc.CH_DBG_TRACE_MASK!"CH_DBG_TRACE_MASK_DISABLED"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Trace buffer entries.
|
||||
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
|
||||
* different from @p CH_DBG_TRACE_MASK_DISABLED.
|
||||
*/
|
||||
#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
|
||||
#define CH_DBG_TRACE_BUFFER_SIZE ${doc.CH_DBG_TRACE_BUFFER_SIZE!"128"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, stack checks.
|
||||
* @details If enabled then a runtime stack check is performed.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note The stack check is performed in a architecture/port dependent way.
|
||||
* It may not be implemented or some ports.
|
||||
* @note The default failure mode is to halt the system with the global
|
||||
* @p panic_msg variable set to @p NULL.
|
||||
*/
|
||||
#if !defined(CH_DBG_ENABLE_STACK_CHECK)
|
||||
#define CH_DBG_ENABLE_STACK_CHECK ${doc.CH_DBG_ENABLE_STACK_CHECK!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, stacks initialization.
|
||||
* @details If enabled then the threads working area is filled with a byte
|
||||
* value when a thread is created. This can be useful for the
|
||||
* runtime measurement of the used stack.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
*/
|
||||
#if !defined(CH_DBG_FILL_THREADS)
|
||||
#define CH_DBG_FILL_THREADS ${doc.CH_DBG_FILL_THREADS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Debug option, threads profiling.
|
||||
* @details If enabled then a field is added to the @p thread_t structure that
|
||||
* counts the system ticks occurred while executing the thread.
|
||||
*
|
||||
* @note The default is @p FALSE.
|
||||
* @note This debug option is not currently compatible with the
|
||||
* tickless mode.
|
||||
*/
|
||||
#if !defined(CH_DBG_THREADS_PROFILING)
|
||||
#define CH_DBG_THREADS_PROFILING ${doc.CH_DBG_THREADS_PROFILING!"FALSE"}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/**
|
||||
* @name Kernel hooks
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief System structure extension.
|
||||
* @details User fields added to the end of the @p ch_system_t structure.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief System initialization hook.
|
||||
* @details User initialization code added to the @p chSysInit() function
|
||||
* just before interrupts are enabled globally.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_INIT_HOOK() { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads descriptor structure extension.
|
||||
* @details User fields added to the end of the @p thread_t structure.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXTRA_FIELDS \
|
||||
/* Add threads custom fields here.*/
|
||||
|
||||
/**
|
||||
* @brief Threads initialization hook.
|
||||
* @details User initialization code added to the @p _thread_init() function.
|
||||
*
|
||||
* @note It is invoked from within @p _thread_init() and implicitly from all
|
||||
* the threads creation APIs.
|
||||
*/
|
||||
#define CH_CFG_THREAD_INIT_HOOK(tp) { \
|
||||
/* Add threads initialization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Threads finalization hook.
|
||||
* @details User finalization code added to the @p chThdExit() API.
|
||||
*/
|
||||
#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
|
||||
/* Add threads finalization code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Context switch hook.
|
||||
* @details This hook is invoked just before switching between threads.
|
||||
*/
|
||||
#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
|
||||
/* Context switch code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ISR enter hook.
|
||||
*/
|
||||
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
|
||||
/* IRQ prologue code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ISR exit hook.
|
||||
*/
|
||||
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
|
||||
/* IRQ epilogue code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread enter hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to activate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_ENTER_HOOK() { \
|
||||
/* Idle-enter code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle thread leave hook.
|
||||
* @note This hook is invoked within a critical zone, no OS functions
|
||||
* should be invoked from here.
|
||||
* @note This macro can be used to deactivate a power saving mode.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LEAVE_HOOK() { \
|
||||
/* Idle-leave code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Idle Loop hook.
|
||||
* @details This hook is continuously invoked by the idle thread loop.
|
||||
*/
|
||||
#define CH_CFG_IDLE_LOOP_HOOK() { \
|
||||
/* Idle loop code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System tick event hook.
|
||||
* @details This hook is invoked in the system tick handler immediately
|
||||
* after processing the virtual timers queue.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_TICK_HOOK() { \
|
||||
/* System tick event code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System halt hook.
|
||||
* @details This hook is invoked in case to a system halting error before
|
||||
* the system is halted.
|
||||
*/
|
||||
#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
|
||||
/* System halt code here.*/ \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Trace hook.
|
||||
* @details This hook is invoked each time a new record is written in the
|
||||
* trace buffer.
|
||||
*/
|
||||
#define CH_CFG_TRACE_HOOK(tep) { \
|
||||
/* Trace code here.*/ \
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Port-specific settings (override port settings defaulted in chcore.h). */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* CHCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,542 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="halconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file templates/halconf.h
|
||||
* @brief HAL configuration header.
|
||||
* @details HAL configuration file, this file allows to enable or disable the
|
||||
* various device drivers from your application. You may also use
|
||||
* this file in order to override the device drivers default settings.
|
||||
*
|
||||
* @addtogroup HAL_CONF
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef HALCONF_H
|
||||
#define HALCONF_H
|
||||
|
||||
#define _CHIBIOS_HAL_CONF_
|
||||
#define _CHIBIOS_HAL_CONF_VER_7_1_
|
||||
|
||||
#include "mcuconf.h"
|
||||
|
||||
/**
|
||||
* @brief Enables the PAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PAL ${doc.HAL_USE_PAL!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ADC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ADC ${doc.HAL_USE_ADC!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the CAN subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CAN ${doc.HAL_USE_CAN!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the cryptographic subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_CRY ${doc.HAL_USE_CRY!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the DAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_DAC ${doc.HAL_USE_DAC!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the EFlash subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_EFL ${doc.HAL_USE_EFL!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the GPT subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_GPT ${doc.HAL_USE_GPT!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2C subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2C ${doc.HAL_USE_I2C!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the I2S subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_I2S ${doc.HAL_USE_I2S!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the ICU subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_ICU ${doc.HAL_USE_ICU!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MAC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MAC ${doc.HAL_USE_MAC!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the MMC_SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_MMC_SPI ${doc.HAL_USE_MMC_SPI!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the PWM subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_PWM ${doc.HAL_USE_PWM!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the RTC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_RTC ${doc.HAL_USE_RTC!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SDC subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SDC ${doc.HAL_USE_SDC!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL ${doc.HAL_USE_SERIAL!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SERIAL over USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SERIAL_USB ${doc.HAL_USE_SERIAL_USB!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SIO subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SIO ${doc.HAL_USE_SIO!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the SPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_SPI ${doc.HAL_USE_SPI!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the TRNG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_TRNG ${doc.HAL_USE_TRNG!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the UART subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_UART ${doc.HAL_USE_UART!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the USB subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_USB ${doc.HAL_USE_USB!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WDG subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WDG ${doc.HAL_USE_WDG!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the WSPI subsystem.
|
||||
*/
|
||||
#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
|
||||
#define HAL_USE_WSPI ${doc.HAL_USE_WSPI!"FALSE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* PAL driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
|
||||
#define PAL_USE_CALLBACKS ${doc.PAL_USE_CALLBACKS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define PAL_USE_WAIT ${doc.PAL_USE_WAIT!"FALSE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* ADC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_WAIT ${doc.ADC_USE_WAIT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define ADC_USE_MUTUAL_EXCLUSION ${doc.ADC_USE_MUTUAL_EXCLUSION!"TRUE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CAN driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Sleep mode related APIs inclusion switch.
|
||||
*/
|
||||
#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
|
||||
#define CAN_USE_SLEEP_MODE ${doc.CAN_USE_SLEEP_MODE!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enforces the driver to use direct callbacks rather than OSAL events.
|
||||
*/
|
||||
#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
|
||||
#define CAN_ENFORCE_USE_CALLBACKS ${doc.CAN_ENFORCE_USE_CALLBACKS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* CRY driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the SW fall-back of the cryptographic driver.
|
||||
* @details When enabled, this option, activates a fall-back software
|
||||
* implementation for algorithms not supported by the underlying
|
||||
* hardware.
|
||||
* @note Fall-back implementations may not be present for all algorithms.
|
||||
*/
|
||||
#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_USE_FALLBACK ${doc.HAL_CRY_USE_FALLBACK!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Makes the driver forcibly use the fall-back implementations.
|
||||
*/
|
||||
#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
|
||||
#define HAL_CRY_ENFORCE_FALLBACK ${doc.HAL_CRY_ENFORCE_FALLBACK!"FALSE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* DAC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define DAC_USE_WAIT ${doc.DAC_USE_WAIT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define DAC_USE_MUTUAL_EXCLUSION ${doc.DAC_USE_MUTUAL_EXCLUSION!"TRUE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I2C driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the mutual exclusion APIs on the I2C bus.
|
||||
*/
|
||||
#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define I2C_USE_MUTUAL_EXCLUSION ${doc.I2C_USE_MUTUAL_EXCLUSION!"TRUE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MAC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables the zero-copy API.
|
||||
*/
|
||||
#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_ZERO_COPY ${doc.MAC_USE_ZERO_COPY!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables an event sources for incoming packets.
|
||||
*/
|
||||
#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
|
||||
#define MAC_USE_EVENTS ${doc.MAC_USE_EVENTS!"FALSE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* MMC_SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
* This option is recommended also if the SPI driver does not
|
||||
* use a DMA channel and heavily loads the CPU.
|
||||
*/
|
||||
#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define MMC_NICE_WAITING ${doc.MMC_NICE_WAITING!"TRUE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SDC driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Number of initialization attempts before rejecting the card.
|
||||
* @note Attempts are performed at 10mS intervals.
|
||||
*/
|
||||
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_RETRY ${doc.SDC_INIT_RETRY!"100"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Include support for MMC cards.
|
||||
* @note MMC support is not yet implemented so this option must be kept
|
||||
* at @p FALSE.
|
||||
*/
|
||||
#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
|
||||
#define SDC_MMC_SUPPORT ${doc.SDC_MMC_SUPPORT!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Delays insertions.
|
||||
* @details If enabled this options inserts delays into the MMC waiting
|
||||
* routines releasing some extra CPU time for the threads with
|
||||
* lower priority, this may slow down the driver a bit however.
|
||||
*/
|
||||
#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
|
||||
#define SDC_NICE_WAITING ${doc.SDC_NICE_WAITING!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief OCR initialization constant for V20 cards.
|
||||
*/
|
||||
#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_OCR_V20 ${doc.SDC_INIT_OCR_V20!"0x50FF8000U"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief OCR initialization constant for non-V20 cards.
|
||||
*/
|
||||
#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
|
||||
#define SDC_INIT_OCR ${doc.SDC_INIT_OCR!"0x80100000U"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Default bit rate.
|
||||
* @details Configuration parameter, this is the baud rate selected for the
|
||||
* default configuration.
|
||||
*/
|
||||
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_DEFAULT_BITRATE ${doc.SERIAL_DEFAULT_BITRATE!"38400"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial buffers size.
|
||||
* @details Configuration parameter, you can change the depth of the queue
|
||||
* buffers depending on the requirements of your application.
|
||||
* @note The default is 16 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_BUFFERS_SIZE ${doc.SERIAL_BUFFERS_SIZE!"16"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SERIAL_USB driver related setting. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Serial over USB buffers size.
|
||||
* @details Configuration parameter, the buffer size must be a multiple of
|
||||
* the USB data endpoint maximum packet size.
|
||||
* @note The default is 256 bytes for both the transmission and receive
|
||||
* buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_SIZE ${doc.SERIAL_USB_BUFFERS_SIZE!"256"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Serial over USB number of buffers.
|
||||
* @note The default is 2 buffers.
|
||||
*/
|
||||
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
|
||||
#define SERIAL_USB_BUFFERS_NUMBER ${doc.SERIAL_USB_BUFFERS_NUMBER!"2"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* SPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_WAIT ${doc.SPI_USE_WAIT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables circular transfers APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_CIRCULAR ${doc.SPI_USE_CIRCULAR!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define SPI_USE_MUTUAL_EXCLUSION ${doc.SPI_USE_MUTUAL_EXCLUSION!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Handling method for SPI CS line.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
|
||||
#define SPI_SELECT_MODE ${doc.SPI_SELECT_MODE!"SPI_SELECT_MODE_PAD"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* UART driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define UART_USE_WAIT ${doc.UART_USE_WAIT!"FALSE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define UART_USE_MUTUAL_EXCLUSION ${doc.UART_USE_MUTUAL_EXCLUSION!"FALSE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* USB driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define USB_USE_WAIT ${doc.USB_USE_WAIT!"FALSE"}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* WSPI driver related settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables synchronous APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
|
||||
#define WSPI_USE_WAIT ${doc.WSPI_USE_WAIT!"TRUE"}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
|
||||
* @note Disabling this option saves both code and data space.
|
||||
*/
|
||||
#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
|
||||
#define WSPI_USE_MUTUAL_EXCLUSION ${doc.WSPI_USE_MUTUAL_EXCLUSION!"TRUE"}
|
||||
#endif
|
||||
|
||||
#endif /* HALCONF_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F3xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F3xx_MCUCONF
|
||||
#define STM32F303_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PREDIV_VALUE ${doc.STM32_PREDIV_VALUE!"1"}
|
||||
#define STM32_PLLMUL_VALUE ${doc.STM32_PLLMUL_VALUE!"9"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV2"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_ADC12PRES ${doc.STM32_ADC12PRES!"STM32_ADC12PRES_DIV1"}
|
||||
#define STM32_ADC34PRES ${doc.STM32_ADC34PRES!"STM32_ADC34PRES_DIV1"}
|
||||
#define STM32_USART1SW ${doc.STM32_USART1SW!"STM32_USART1SW_PCLK"}
|
||||
#define STM32_USART2SW ${doc.STM32_USART2SW!"STM32_USART2SW_PCLK"}
|
||||
#define STM32_USART3SW ${doc.STM32_USART3SW!"STM32_USART3SW_PCLK"}
|
||||
#define STM32_UART4SW ${doc.STM32_UART4SW!"STM32_UART4SW_PCLK"}
|
||||
#define STM32_UART5SW ${doc.STM32_UART5SW!"STM32_UART5SW_PCLK"}
|
||||
#define STM32_I2C1SW ${doc.STM32_I2C1SW!"STM32_I2C1SW_SYSCLK"}
|
||||
#define STM32_I2C2SW ${doc.STM32_I2C2SW!"STM32_I2C2SW_SYSCLK"}
|
||||
#define STM32_TIM1SW ${doc.STM32_TIM1SW!"STM32_TIM1SW_PCLK2"}
|
||||
#define STM32_TIM8SW ${doc.STM32_TIM8SW!"STM32_TIM8SW_PCLK2"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
#define STM32_USB_CLOCK_REQUIRED ${doc.STM32_USB_CLOCK_REQUIRED!"TRUE"}
|
||||
#define STM32_USBPRE ${doc.STM32_USBPRE!"STM32_USBPRE_DIV1P5"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI21_22_29_PRIORITY ${doc.STM32_IRQ_EXTI21_22_29_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI30_32_PRIORITY ${doc.STM32_IRQ_EXTI30_32_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI33_PRIORITY ${doc.STM32_IRQ_EXTI33_PRIORITY!"6"}
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC4 ${doc.STM32_ADC_USE_ADC4!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_ADC_ADC4_DMA_STREAM ${doc.STM32_ADC_ADC4_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC4_DMA_PRIORITY ${doc.STM32_ADC_ADC4_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC4_IRQ_PRIORITY ${doc.STM32_ADC_ADC4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC4_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC12_CLOCK_MODE ${doc.STM32_ADC_ADC12_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}
|
||||
#define STM32_ADC_ADC34_CLOCK_MODE ${doc.STM32_ADC_ADC34_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"TRUE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"TRUE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY ${doc.STM32_GPT_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY ${doc.STM32_GPT_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY ${doc.STM32_GPT_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY ${doc.STM32_GPT_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM6_IRQ_PRIORITY ${doc.STM32_GPT_TIM6_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM7_IRQ_PRIORITY ${doc.STM32_GPT_TIM7_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY ${doc.STM32_GPT_TIM8_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2C_USE_DMA ${doc.STM32_I2C_USE_DMA!"TRUE"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY ${doc.STM32_ICU_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY ${doc.STM32_ICU_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY ${doc.STM32_ICU_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY ${doc.STM32_ICU_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY ${doc.STM32_ICU_TIM8_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY ${doc.STM32_PWM_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY ${doc.STM32_PWM_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY ${doc.STM32_PWM_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY ${doc.STM32_PWM_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY ${doc.STM32_PWM_TIM8_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART3_PRIORITY ${doc.STM32_SERIAL_USART3_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART4_PRIORITY ${doc.STM32_SERIAL_UART4_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART5_PRIORITY ${doc.STM32_SERIAL_UART5_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 ${doc.STM32_USB_USE_USB1!"FALSE"}
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"}
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,363 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F4xx_MCUCONF
|
||||
#define STM32F405_MCUCONF
|
||||
#define STM32F415_MCUCONF
|
||||
#define STM32F407_MCUCONF
|
||||
#define STM32F417_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"8"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"336"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"7"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV4"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV2"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"8"}
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
|
||||
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
|
||||
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV5"}
|
||||
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_CKIN"}
|
||||
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
|
||||
#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"4"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"15"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"6"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN2 ${doc.STM32_CAN_USE_CAN2!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM12 ${doc.STM32_GPT_USE_TIM12!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"}
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY ${doc.STM32_GPT_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY ${doc.STM32_GPT_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY ${doc.STM32_GPT_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY ${doc.STM32_GPT_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY ${doc.STM32_GPT_TIM5_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM6_IRQ_PRIORITY ${doc.STM32_GPT_TIM6_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM7_IRQ_PRIORITY ${doc.STM32_GPT_TIM7_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM8_IRQ_PRIORITY ${doc.STM32_GPT_TIM8_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM9_IRQ_PRIORITY ${doc.STM32_GPT_TIM9_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM11_IRQ_PRIORITY ${doc.STM32_GPT_TIM11_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM12_IRQ_PRIORITY ${doc.STM32_GPT_TIM12_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM14_IRQ_PRIORITY ${doc.STM32_GPT_TIM14_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 ${doc.STM32_I2S_USE_SPI2!"FALSE"}
|
||||
#define STM32_I2S_USE_SPI3 ${doc.STM32_I2S_USE_SPI3!"FALSE"}
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY ${doc.STM32_I2S_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY ${doc.STM32_I2S_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY ${doc.STM32_I2S_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY ${doc.STM32_I2S_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM ${doc.STM32_I2S_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM ${doc.STM32_I2S_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM ${doc.STM32_I2S_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM ${doc.STM32_I2S_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) ${doc.STM32_I2S_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY ${doc.STM32_ICU_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY ${doc.STM32_ICU_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY ${doc.STM32_ICU_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY ${doc.STM32_ICU_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY ${doc.STM32_ICU_TIM5_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM8_IRQ_PRIORITY ${doc.STM32_ICU_TIM8_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY ${doc.STM32_ICU_TIM9_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS ${doc.STM32_MAC_TRANSMIT_BUFFERS!"2"}
|
||||
#define STM32_MAC_RECEIVE_BUFFERS ${doc.STM32_MAC_RECEIVE_BUFFERS!"4"}
|
||||
#define STM32_MAC_BUFFERS_SIZE ${doc.STM32_MAC_BUFFERS_SIZE!"1522"}
|
||||
#define STM32_MAC_PHY_TIMEOUT ${doc.STM32_MAC_PHY_TIMEOUT!"100"}
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE ${doc.STM32_MAC_ETH1_CHANGE_PHY_STATE!"TRUE"}
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY ${doc.STM32_MAC_ETH1_IRQ_PRIORITY!"13"}
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD ${doc.STM32_MAC_IP_CHECKSUM_OFFLOAD!"0"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY ${doc.STM32_PWM_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY ${doc.STM32_PWM_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY ${doc.STM32_PWM_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY ${doc.STM32_PWM_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY ${doc.STM32_PWM_TIM5_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM8_IRQ_PRIORITY ${doc.STM32_PWM_TIM8_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY ${doc.STM32_PWM_TIM9_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_SDIO_DMA_PRIORITY ${doc.STM32_SDC_SDIO_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDIO_IRQ_PRIORITY ${doc.STM32_SDC_SDIO_IRQ_PRIORITY!"9"}
|
||||
#define STM32_SDC_WRITE_TIMEOUT_MS ${doc.STM32_SDC_WRITE_TIMEOUT_MS!"1000"}
|
||||
#define STM32_SDC_READ_TIMEOUT_MS ${doc.STM32_SDC_READ_TIMEOUT_MS!"1000"}
|
||||
#define STM32_SDC_CLOCK_ACTIVATION_DELAY ${doc.STM32_SDC_CLOCK_ACTIVATION_DELAY!"10"}
|
||||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDIO_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDIO_DMA_STREAM ${doc.STM32_SDC_SDIO_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"TRUE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
#define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART3_PRIORITY ${doc.STM32_SERIAL_USART3_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART4_PRIORITY ${doc.STM32_SERIAL_UART4_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART5_PRIORITY ${doc.STM32_SERIAL_UART5_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART6_PRIORITY ${doc.STM32_SERIAL_USART6_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART6_IRQ_PRIORITY ${doc.STM32_UART_USART6_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_USE_OTG2 ${doc.STM32_USB_USE_OTG2!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY ${doc.STM32_USB_OTG2_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE ${doc.STM32_USB_OTG2_RX_FIFO_SIZE!"1024"}
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION ${doc.STM32_USB_HOST_WAKEUP_DURATION!"2"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,359 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F4xx_MCUCONF
|
||||
#define STM32F413_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"8"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"384"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"4"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"8"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_PLLI2SSRC ${doc.STM32_PLLI2SSRC!"STM32_PLLI2SSRC_PLLSRC"}
|
||||
#define STM32_I2SCKIN_VALUE ${doc.STM32_I2SCKIN_VALUE!"0"}
|
||||
#define STM32_PLLI2SM_VALUE ${doc.STM32_PLLI2SM_VALUE!"8"}
|
||||
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
|
||||
#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"4"}
|
||||
#define STM32_PLLI2SQ_VALUE ${doc.STM32_PLLI2SQ_VALUE!"4"}
|
||||
#define STM32_PLLI2SDIVR_VALUE ${doc.STM32_PLLI2SDIVR_VALUE!"1"}
|
||||
#define STM32_PLLDIVR_VALUE ${doc.STM32_PLLDIVR_VALUE!"1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
|
||||
#define STM32_TIMPRE ${doc.STM32_TIMPRE!"STM32_TIMPRE_PCLK"}
|
||||
#define STM32_CK48MSEL ${doc.STM32_CK48MSEL!"STM32_CK48MSEL_PLL"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"8"}
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
|
||||
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
|
||||
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV5"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"15"}
|
||||
#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"15"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN2 ${doc.STM32_CAN_USE_CAN2!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN3 ${doc.STM32_CAN_USE_CAN3!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN3_IRQ_PRIORITY ${doc.STM32_CAN_CAN3_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
|
||||
#define STM32_GPT_TIM1_IRQ_PRIORITY ${doc.STM32_GPT_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM2_IRQ_PRIORITY ${doc.STM32_GPT_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM3_IRQ_PRIORITY ${doc.STM32_GPT_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM4_IRQ_PRIORITY ${doc.STM32_GPT_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM5_IRQ_PRIORITY ${doc.STM32_GPT_TIM5_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM9_IRQ_PRIORITY ${doc.STM32_GPT_TIM9_IRQ_PRIORITY!"7"}
|
||||
#define STM32_GPT_TIM11_IRQ_PRIORITY ${doc.STM32_GPT_TIM11_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* I2S driver system settings.
|
||||
*/
|
||||
#define STM32_I2S_USE_SPI2 ${doc.STM32_I2S_USE_SPI2!"FALSE"}
|
||||
#define STM32_I2S_USE_SPI3 ${doc.STM32_I2S_USE_SPI3!"FALSE"}
|
||||
#define STM32_I2S_SPI2_IRQ_PRIORITY ${doc.STM32_I2S_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI3_IRQ_PRIORITY ${doc.STM32_I2S_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_I2S_SPI2_DMA_PRIORITY ${doc.STM32_I2S_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI3_DMA_PRIORITY ${doc.STM32_I2S_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2S_SPI2_RX_DMA_STREAM ${doc.STM32_I2S_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2S_SPI2_TX_DMA_STREAM ${doc.STM32_I2S_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2S_SPI3_RX_DMA_STREAM ${doc.STM32_I2S_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2S_SPI3_TX_DMA_STREAM ${doc.STM32_I2S_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2S_DMA_ERROR_HOOK(i2sp) ${doc.STM32_I2S_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
|
||||
#define STM32_ICU_TIM1_IRQ_PRIORITY ${doc.STM32_ICU_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM2_IRQ_PRIORITY ${doc.STM32_ICU_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM3_IRQ_PRIORITY ${doc.STM32_ICU_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM4_IRQ_PRIORITY ${doc.STM32_ICU_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM5_IRQ_PRIORITY ${doc.STM32_ICU_TIM5_IRQ_PRIORITY!"7"}
|
||||
#define STM32_ICU_TIM9_IRQ_PRIORITY ${doc.STM32_ICU_TIM9_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
|
||||
#define STM32_PWM_TIM1_IRQ_PRIORITY ${doc.STM32_PWM_TIM1_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM2_IRQ_PRIORITY ${doc.STM32_PWM_TIM2_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM3_IRQ_PRIORITY ${doc.STM32_PWM_TIM3_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM4_IRQ_PRIORITY ${doc.STM32_PWM_TIM4_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM5_IRQ_PRIORITY ${doc.STM32_PWM_TIM5_IRQ_PRIORITY!"7"}
|
||||
#define STM32_PWM_TIM9_IRQ_PRIORITY ${doc.STM32_PWM_TIM9_IRQ_PRIORITY!"7"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_SDIO_DMA_PRIORITY ${doc.STM32_SDC_SDIO_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDIO_IRQ_PRIORITY ${doc.STM32_SDC_SDIO_IRQ_PRIORITY!"9"}
|
||||
#define STM32_SDC_WRITE_TIMEOUT_MS ${doc.STM32_SDC_WRITE_TIMEOUT_MS!"1000"}
|
||||
#define STM32_SDC_READ_TIMEOUT_MS ${doc.STM32_SDC_READ_TIMEOUT_MS!"1000"}
|
||||
#define STM32_SDC_CLOCK_ACTIVATION_DELAY ${doc.STM32_SDC_CLOCK_ACTIVATION_DELAY!"10"}
|
||||
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDIO_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDIO_DMA_STREAM ${doc.STM32_SDC_SDIO_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"TRUE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART7 ${doc.STM32_SERIAL_USE_UART7!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART8 ${doc.STM32_SERIAL_USE_UART8!"FALSE"}
|
||||
#define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART3_PRIORITY ${doc.STM32_SERIAL_USART3_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART4_PRIORITY ${doc.STM32_SERIAL_UART4_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART5_PRIORITY ${doc.STM32_SERIAL_UART5_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART6_PRIORITY ${doc.STM32_SERIAL_USART6_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART7_PRIORITY ${doc.STM32_SERIAL_UART7_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART8_PRIORITY ${doc.STM32_SERIAL_UART8_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USE_UART7 ${doc.STM32_UART_USE_UART7!"FALSE"}
|
||||
#define STM32_UART_USE_UART8 ${doc.STM32_UART_USE_UART8!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_UART7_RX_DMA_STREAM ${doc.STM32_UART_UART7_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART7_TX_DMA_STREAM ${doc.STM32_UART_UART7_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_UART8_RX_DMA_STREAM ${doc.STM32_UART_UART8_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_UART8_TX_DMA_STREAM ${doc.STM32_UART_UART8_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART6_IRQ_PRIORITY ${doc.STM32_UART_USART6_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART7_IRQ_PRIORITY ${doc.STM32_UART_UART7_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART8_IRQ_PRIORITY ${doc.STM32_UART_UART8_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART7_DMA_PRIORITY ${doc.STM32_UART_UART7_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART8_DMA_PRIORITY ${doc.STM32_UART_UART8_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION ${doc.STM32_USB_HOST_WAKEUP_DURATION!"2"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,392 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F7xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F7xx_MCUCONF
|
||||
#define STM32F722_MCUCONF
|
||||
#define STM32F732_MCUCONF
|
||||
#define STM32F723_MCUCONF
|
||||
#define STM32F733_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"8"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"432"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"9"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV4"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV2"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSE"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"25"}
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
|
||||
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
|
||||
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"}
|
||||
#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"}
|
||||
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"}
|
||||
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
|
||||
#define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"}
|
||||
#define STM32_PLLI2SQ_VALUE ${doc.STM32_PLLI2SQ_VALUE!"4"}
|
||||
#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"4"}
|
||||
#define STM32_PLLI2SDIVQ_VALUE ${doc.STM32_PLLI2SDIVQ_VALUE!"2"}
|
||||
#define STM32_PLLSAIN_VALUE ${doc.STM32_PLLSAIN_VALUE!"192"}
|
||||
#define STM32_PLLSAIP_VALUE ${doc.STM32_PLLSAIP_VALUE!"4"}
|
||||
#define STM32_PLLSAIQ_VALUE ${doc.STM32_PLLSAIQ_VALUE!"4"}
|
||||
#define STM32_PLLSAIR_VALUE ${doc.STM32_PLLSAIR_VALUE!"4"}
|
||||
#define STM32_PLLSAIDIVQ_VALUE ${doc.STM32_PLLSAIDIVQ_VALUE!"2"}
|
||||
#define STM32_PLLSAIDIVR_VALUE ${doc.STM32_PLLSAIDIVR_VALUE!"2"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
|
||||
#define STM32_LCDTFT_REQUIRED ${doc.STM32_LCDTFT_REQUIRED!"FALSE"}
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_PCLK2"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_PCLK1"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_PCLK1"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_PCLK1"}
|
||||
#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_PCLK1"}
|
||||
#define STM32_USART6SEL ${doc.STM32_USART6SEL!"STM32_USART6SEL_PCLK2"}
|
||||
#define STM32_UART7SEL ${doc.STM32_UART7SEL!"STM32_UART7SEL_PCLK1"}
|
||||
#define STM32_UART8SEL ${doc.STM32_UART8SEL!"STM32_UART8SEL_PCLK1"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK1"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_PCLK1"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_PCLK1"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_CK48MSEL ${doc.STM32_CK48MSEL!"STM32_CK48MSEL_PLL"}
|
||||
#define STM32_SDMMC1SEL ${doc.STM32_SDMMC1SEL!"STM32_SDMMC1SEL_PLL48CLK"}
|
||||
#define STM32_SDMMC2SEL ${doc.STM32_SDMMC2SEL!"STM32_SDMMC2SEL_PLL48CLK"}
|
||||
#define STM32_SRAM2_NOCACHE ${doc.STM32_SRAM2_NOCACHE!"FALSE"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI23_PRIORITY ${doc.STM32_IRQ_EXTI23_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM9_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM10_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY ${doc.STM32_IRQ_TIM8_BRK_TIM12_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY ${doc.STM32_IRQ_TIM8_UP_TIM13_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY ${doc.STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART6_PRIORITY ${doc.STM32_IRQ_USART6_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART7_PRIORITY ${doc.STM32_IRQ_UART7_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART8_PRIORITY ${doc.STM32_IRQ_UART8_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"6"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM10 ${doc.STM32_GPT_USE_TIM10!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM12 ${doc.STM32_GPT_USE_TIM12!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM13 ${doc.STM32_GPT_USE_TIM13!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM10 ${doc.STM32_ICU_USE_TIM10!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM11 ${doc.STM32_ICU_USE_TIM11!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM12 ${doc.STM32_ICU_USE_TIM12!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM13 ${doc.STM32_ICU_USE_TIM13!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM14 ${doc.STM32_ICU_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM10 ${doc.STM32_PWM_USE_TIM10!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM11 ${doc.STM32_PWM_USE_TIM11!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM12 ${doc.STM32_PWM_USE_TIM12!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM13 ${doc.STM32_PWM_USE_TIM13!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM14 ${doc.STM32_PWM_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_USE_SDMMC2 ${doc.STM32_SDC_USE_SDMMC2!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC1_DMA_STREAM ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SDC_SDMMC2_DMA_STREAM ${doc.STM32_SDC_SDMMC2_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SDC_SDMMC1_DMA_PRIORITY ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC2_DMA_PRIORITY ${doc.STM32_SDC_SDMMC2_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
|
||||
#define STM32_SDC_SDMMC2_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC2_IRQ_PRIORITY!"9"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART7 ${doc.STM32_SERIAL_USE_UART7!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART8 ${doc.STM32_SERIAL_USE_UART8!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USE_UART7 ${doc.STM32_UART_USE_UART7!"FALSE"}
|
||||
#define STM32_UART_USE_UART8 ${doc.STM32_UART_USE_UART8!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_UART7_RX_DMA_STREAM ${doc.STM32_UART_UART7_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART7_TX_DMA_STREAM ${doc.STM32_UART_UART7_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_UART8_RX_DMA_STREAM ${doc.STM32_UART_UART8_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_UART8_TX_DMA_STREAM ${doc.STM32_UART_UART8_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART7_DMA_PRIORITY ${doc.STM32_UART_UART7_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART8_DMA_PRIORITY ${doc.STM32_UART_UART8_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_USE_OTG2 ${doc.STM32_USB_USE_OTG2!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY ${doc.STM32_USB_OTG2_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE ${doc.STM32_USB_OTG2_RX_FIFO_SIZE!"1024"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F7xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F7xx_MCUCONF
|
||||
#define STM32F746_MCUCONF
|
||||
#define STM32F756_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"8"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"432"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"9"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV4"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV2"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSE"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"25"}
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
|
||||
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
|
||||
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"}
|
||||
#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"}
|
||||
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"}
|
||||
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
|
||||
#define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"}
|
||||
#define STM32_PLLI2SQ_VALUE ${doc.STM32_PLLI2SQ_VALUE!"4"}
|
||||
#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"4"}
|
||||
#define STM32_PLLI2SDIVQ_VALUE ${doc.STM32_PLLI2SDIVQ_VALUE!"2"}
|
||||
#define STM32_PLLSAIN_VALUE ${doc.STM32_PLLSAIN_VALUE!"192"}
|
||||
#define STM32_PLLSAIP_VALUE ${doc.STM32_PLLSAIP_VALUE!"4"}
|
||||
#define STM32_PLLSAIQ_VALUE ${doc.STM32_PLLSAIQ_VALUE!"4"}
|
||||
#define STM32_PLLSAIR_VALUE ${doc.STM32_PLLSAIR_VALUE!"4"}
|
||||
#define STM32_PLLSAIDIVQ_VALUE ${doc.STM32_PLLSAIDIVQ_VALUE!"2"}
|
||||
#define STM32_PLLSAIDIVR_VALUE ${doc.STM32_PLLSAIDIVR_VALUE!"2"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
|
||||
#define STM32_LCDTFT_REQUIRED ${doc.STM32_LCDTFT_REQUIRED!"FALSE"}
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_PCLK2"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_PCLK1"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_PCLK1"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_PCLK1"}
|
||||
#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_PCLK1"}
|
||||
#define STM32_USART6SEL ${doc.STM32_USART6SEL!"STM32_USART6SEL_PCLK2"}
|
||||
#define STM32_UART7SEL ${doc.STM32_UART7SEL!"STM32_UART7SEL_PCLK1"}
|
||||
#define STM32_UART8SEL ${doc.STM32_UART8SEL!"STM32_UART8SEL_PCLK1"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK1"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_PCLK1"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_PCLK1"}
|
||||
#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_PCLK1"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_CECSEL ${doc.STM32_CECSEL!"STM32_CECSEL_LSE"}
|
||||
#define STM32_CK48MSEL ${doc.STM32_CK48MSEL!"STM32_CK48MSEL_PLL"}
|
||||
#define STM32_SDMMC1SEL ${doc.STM32_SDMMC1SEL!"STM32_SDMMC1SEL_PLL48CLK"}
|
||||
#define STM32_SRAM2_NOCACHE ${doc.STM32_SRAM2_NOCACHE!"FALSE"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI23_PRIORITY ${doc.STM32_IRQ_EXTI23_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM9_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM10_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY ${doc.STM32_IRQ_TIM8_BRK_TIM12_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY ${doc.STM32_IRQ_TIM8_UP_TIM13_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY ${doc.STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART6_PRIORITY ${doc.STM32_IRQ_USART6_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART7_PRIORITY ${doc.STM32_IRQ_UART7_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART8_PRIORITY ${doc.STM32_IRQ_UART8_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"6"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN2 ${doc.STM32_CAN_USE_CAN2!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN3 ${doc.STM32_CAN_USE_CAN3!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN3_IRQ_PRIORITY ${doc.STM32_CAN_CAN3_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* CRY driver system settings.
|
||||
*/
|
||||
#define STM32_CRY_USE_CRYP1 ${doc.STM32_CRY_USE_CRYP1!"FALSE"}
|
||||
#define STM32_CRY_USE_HASH1 ${doc.STM32_CRY_USE_HASH1!"FALSE"}
|
||||
#define STM32_CRY_CRYP1_IRQ_PRIORITY ${doc.STM32_CRY_CRYP1_IRQ_PRIORITY!"9"}
|
||||
#define STM32_CRY_HASH1_IRQ_PRIORITY ${doc.STM32_CRY_HASH1_IRQ_PRIORITY!"9"}
|
||||
#define STM32_CRY_CRYP1_IN_DMA_STREAM ${doc.STM32_CRY_CRYP1_IN_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_CRY_CRYP1_OUT_DMA_STREAM ${doc.STM32_CRY_CRYP1_OUT_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_CRY_HASH1_DMA_STREAM ${doc.STM32_CRY_HASH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_CRY_CRYP1_IN_DMA_PRIORITY ${doc.STM32_CRY_CRYP1_IN_DMA_PRIORITY!"0"}
|
||||
#define STM32_CRY_CRYP1_OUT_DMA_PRIORITY ${doc.STM32_CRY_CRYP1_OUT_DMA_PRIORITY!"1"}
|
||||
#define STM32_CRY_HASH1_DMA_PRIORITY ${doc.STM32_CRY_HASH1_DMA_PRIORITY!"0"}
|
||||
#define STM32_CRY_HASH_SIZE_THRESHOLD ${doc.STM32_CRY_HASH_SIZE_THRESHOLD!"1024"}
|
||||
#define STM32_CRY_CRYP_DMA_ERROR_HOOK(cryp) ${doc.STM32_CRY_CRYP_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
#define STM32_CRY_HASH_DMA_ERROR_HOOK(cryp) ${doc.STM32_CRY_HASH_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM10 ${doc.STM32_GPT_USE_TIM10!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM12 ${doc.STM32_GPT_USE_TIM12!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM13 ${doc.STM32_GPT_USE_TIM13!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM10 ${doc.STM32_ICU_USE_TIM10!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM11 ${doc.STM32_ICU_USE_TIM11!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM12 ${doc.STM32_ICU_USE_TIM12!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM13 ${doc.STM32_ICU_USE_TIM13!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM14 ${doc.STM32_ICU_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS ${doc.STM32_MAC_TRANSMIT_BUFFERS!"2"}
|
||||
#define STM32_MAC_RECEIVE_BUFFERS ${doc.STM32_MAC_RECEIVE_BUFFERS!"4"}
|
||||
#define STM32_MAC_BUFFERS_SIZE ${doc.STM32_MAC_BUFFERS_SIZE!"1522"}
|
||||
#define STM32_MAC_PHY_TIMEOUT ${doc.STM32_MAC_PHY_TIMEOUT!"100"}
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE ${doc.STM32_MAC_ETH1_CHANGE_PHY_STATE!"TRUE"}
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY ${doc.STM32_MAC_ETH1_IRQ_PRIORITY!"13"}
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD ${doc.STM32_MAC_IP_CHECKSUM_OFFLOAD!"0"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM10 ${doc.STM32_PWM_USE_TIM10!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM11 ${doc.STM32_PWM_USE_TIM11!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM12 ${doc.STM32_PWM_USE_TIM12!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM13 ${doc.STM32_PWM_USE_TIM13!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM14 ${doc.STM32_PWM_USE_TIM14!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC1_DMA_STREAM ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SDC_SDMMC1_DMA_PRIORITY ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART7 ${doc.STM32_SERIAL_USE_UART7!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART8 ${doc.STM32_SERIAL_USE_UART8!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI6 ${doc.STM32_SPI_USE_SPI6!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI6_RX_DMA_STREAM ${doc.STM32_SPI_SPI6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_SPI_SPI6_TX_DMA_STREAM ${doc.STM32_SPI_SPI6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI6_DMA_PRIORITY ${doc.STM32_SPI_SPI6_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY ${doc.STM32_SPI_SPI6_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USE_UART7 ${doc.STM32_UART_USE_UART7!"FALSE"}
|
||||
#define STM32_UART_USE_UART8 ${doc.STM32_UART_USE_UART8!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_UART7_RX_DMA_STREAM ${doc.STM32_UART_UART7_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART7_TX_DMA_STREAM ${doc.STM32_UART_UART7_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_UART8_RX_DMA_STREAM ${doc.STM32_UART_UART8_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_UART8_TX_DMA_STREAM ${doc.STM32_UART_UART8_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART7_DMA_PRIORITY ${doc.STM32_UART_UART7_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART8_DMA_PRIORITY ${doc.STM32_UART_UART8_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_USE_OTG2 ${doc.STM32_USB_USE_OTG2!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY ${doc.STM32_USB_OTG2_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE ${doc.STM32_USB_OTG2_RX_FIFO_SIZE!"1024"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32F7xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32F7xx_MCUCONF
|
||||
#define STM32F765_MCUCONF
|
||||
#define STM32F767_MCUCONF
|
||||
#define STM32F777_MCUCONF
|
||||
#define STM32F769_MCUCONF
|
||||
#define STM32F779_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_BKPRAM_ENABLE ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_CLOCK48_REQUIRED ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"8"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"432"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"9"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV4"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV2"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSE"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"25"}
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
|
||||
#define STM32_MCO1PRE ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
|
||||
#define STM32_MCO2PRE ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV4"}
|
||||
#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"FALSE"}
|
||||
#define STM32_I2SSRC ${doc.STM32_I2SSRC!"STM32_I2SSRC_OFF"}
|
||||
#define STM32_PLLI2SN_VALUE ${doc.STM32_PLLI2SN_VALUE!"192"}
|
||||
#define STM32_PLLI2SP_VALUE ${doc.STM32_PLLI2SP_VALUE!"4"}
|
||||
#define STM32_PLLI2SQ_VALUE ${doc.STM32_PLLI2SQ_VALUE!"4"}
|
||||
#define STM32_PLLI2SR_VALUE ${doc.STM32_PLLI2SR_VALUE!"4"}
|
||||
#define STM32_PLLI2SDIVQ_VALUE ${doc.STM32_PLLI2SDIVQ_VALUE!"2"}
|
||||
#define STM32_PLLSAIN_VALUE ${doc.STM32_PLLSAIN_VALUE!"192"}
|
||||
#define STM32_PLLSAIP_VALUE ${doc.STM32_PLLSAIP_VALUE!"4"}
|
||||
#define STM32_PLLSAIQ_VALUE ${doc.STM32_PLLSAIQ_VALUE!"4"}
|
||||
#define STM32_PLLSAIR_VALUE ${doc.STM32_PLLSAIR_VALUE!"4"}
|
||||
#define STM32_PLLSAIDIVQ_VALUE ${doc.STM32_PLLSAIDIVQ_VALUE!"2"}
|
||||
#define STM32_PLLSAIDIVR_VALUE ${doc.STM32_PLLSAIDIVR_VALUE!"2"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
|
||||
#define STM32_LCDTFT_REQUIRED ${doc.STM32_LCDTFT_REQUIRED!"FALSE"}
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_PCLK2"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_PCLK1"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_PCLK1"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_PCLK1"}
|
||||
#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_PCLK1"}
|
||||
#define STM32_USART6SEL ${doc.STM32_USART6SEL!"STM32_USART6SEL_PCLK2"}
|
||||
#define STM32_UART7SEL ${doc.STM32_UART7SEL!"STM32_UART7SEL_PCLK1"}
|
||||
#define STM32_UART8SEL ${doc.STM32_UART8SEL!"STM32_UART8SEL_PCLK1"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK1"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_PCLK1"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_PCLK1"}
|
||||
#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_PCLK1"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_CECSEL ${doc.STM32_CECSEL!"STM32_CECSEL_LSE"}
|
||||
#define STM32_CK48MSEL ${doc.STM32_CK48MSEL!"STM32_CK48MSEL_PLL"}
|
||||
#define STM32_SDMMC1SEL ${doc.STM32_SDMMC1SEL!"STM32_SDMMC1SEL_PLL48CLK"}
|
||||
#define STM32_SDMMC2SEL ${doc.STM32_SDMMC2SEL!"STM32_SDMMC2SEL_PLL48CLK"}
|
||||
#define STM32_SRAM2_NOCACHE ${doc.STM32_SRAM2_NOCACHE!"FALSE"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_PRIORITY ${doc.STM32_IRQ_EXTI21_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI22_PRIORITY ${doc.STM32_IRQ_EXTI22_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI23_PRIORITY ${doc.STM32_IRQ_EXTI23_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM9_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM10_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY ${doc.STM32_IRQ_TIM8_BRK_TIM12_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY ${doc.STM32_IRQ_TIM8_UP_TIM13_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY ${doc.STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART6_PRIORITY ${doc.STM32_IRQ_USART6_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART7_PRIORITY ${doc.STM32_IRQ_UART7_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART8_PRIORITY ${doc.STM32_IRQ_UART8_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_ADCPRE ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_IRQ_PRIORITY ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"6"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"6"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN2 ${doc.STM32_CAN_USE_CAN2!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN3 ${doc.STM32_CAN_USE_CAN3!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN3_IRQ_PRIORITY ${doc.STM32_CAN_CAN3_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM9 ${doc.STM32_GPT_USE_TIM9!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM10 ${doc.STM32_GPT_USE_TIM10!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM11 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM12 ${doc.STM32_GPT_USE_TIM12!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM13 ${doc.STM32_GPT_USE_TIM13!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM9 ${doc.STM32_ICU_USE_TIM9!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM10 ${doc.STM32_ICU_USE_TIM10!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM11 ${doc.STM32_ICU_USE_TIM11!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM12 ${doc.STM32_ICU_USE_TIM12!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM13 ${doc.STM32_ICU_USE_TIM13!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM14 ${doc.STM32_ICU_USE_TIM14!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM17 ${doc.STM32_ICU_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS ${doc.STM32_MAC_TRANSMIT_BUFFERS!"2"}
|
||||
#define STM32_MAC_RECEIVE_BUFFERS ${doc.STM32_MAC_RECEIVE_BUFFERS!"4"}
|
||||
#define STM32_MAC_BUFFERS_SIZE ${doc.STM32_MAC_BUFFERS_SIZE!"1522"}
|
||||
#define STM32_MAC_PHY_TIMEOUT ${doc.STM32_MAC_PHY_TIMEOUT!"100"}
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE ${doc.STM32_MAC_ETH1_CHANGE_PHY_STATE!"TRUE"}
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY ${doc.STM32_MAC_ETH1_IRQ_PRIORITY!"13"}
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD ${doc.STM32_MAC_IP_CHECKSUM_OFFLOAD!"0"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM9 ${doc.STM32_PWM_USE_TIM9!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM10 ${doc.STM32_PWM_USE_TIM10!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM11 ${doc.STM32_PWM_USE_TIM11!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM12 ${doc.STM32_PWM_USE_TIM12!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM13 ${doc.STM32_PWM_USE_TIM13!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM14 ${doc.STM32_PWM_USE_TIM14!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_USE_SDMMC2 ${doc.STM32_SDC_USE_SDMMC2!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC1_DMA_STREAM ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SDC_SDMMC2_DMA_STREAM ${doc.STM32_SDC_SDMMC2_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SDC_SDMMC1_DMA_PRIORITY ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC2_DMA_PRIORITY ${doc.STM32_SDC_SDMMC2_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
|
||||
#define STM32_SDC_SDMMC2_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC2_IRQ_PRIORITY!"9"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART7 ${doc.STM32_SERIAL_USE_UART7!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART8 ${doc.STM32_SERIAL_USE_UART8!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI6 ${doc.STM32_SPI_USE_SPI6!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI6_RX_DMA_STREAM ${doc.STM32_SPI_SPI6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_SPI_SPI6_TX_DMA_STREAM ${doc.STM32_SPI_SPI6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI6_DMA_PRIORITY ${doc.STM32_SPI_SPI6_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY ${doc.STM32_SPI_SPI6_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USE_UART7 ${doc.STM32_UART_USE_UART7!"FALSE"}
|
||||
#define STM32_UART_USE_UART8 ${doc.STM32_UART_USE_UART8!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_UART7_RX_DMA_STREAM ${doc.STM32_UART_UART7_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART7_TX_DMA_STREAM ${doc.STM32_UART_UART7_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_UART_UART8_RX_DMA_STREAM ${doc.STM32_UART_UART8_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_UART8_TX_DMA_STREAM ${doc.STM32_UART_UART8_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART7_DMA_PRIORITY ${doc.STM32_UART_UART7_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART8_DMA_PRIORITY ${doc.STM32_UART_UART8_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_USE_OTG2 ${doc.STM32_USB_USE_OTG2!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY ${doc.STM32_USB_OTG2_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE ${doc.STM32_USB_OTG2_RX_FIFO_SIZE!"1024"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,247 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32G0xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 3...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32G0xx_MCUCONF
|
||||
#define STM32G071_MCUCONF
|
||||
#define STM32G081_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)"}
|
||||
#define STM32_HSIDIV_VALUE ${doc.STM32_HSIDIV_VALUE!"1"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLLRCLK"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSI16"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"2"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"16"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"2"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"4"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"2"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE ${doc.STM32_PPRE!"STM32_PPRE_DIV1"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
|
||||
/*
|
||||
* Peripherals clocks and sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}
|
||||
#define STM32_CECSEL ${doc.STM32_CECSEL!"STM32_CECSEL_HSI16DIV"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK"}
|
||||
#define STM32_I2S1SEL ${doc.STM32_I2S1SEL!"STM32_I2S1SEL_SYSCLK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK"}
|
||||
#define STM32_TIM1SEL ${doc.STM32_TIM1SEL!"STM32_TIM1SEL_TIMPCLK"}
|
||||
#define STM32_TIM15SEL ${doc.STM32_TIM15SEL!"STM32_TIM15SEL_TIMPCLK"}
|
||||
#define STM32_RNGSEL ${doc.STM32_RNGSEL!"STM32_RNGSEL_HSI16"}
|
||||
#define STM32_RNGDIV_VALUE ${doc.STM32_RNGDIV_VALUE!"1"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_PLLPCLK"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_NOCLOCK"}
|
||||
|
||||
/*
|
||||
* Shared IRQ settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_1_PRIORITY ${doc.STM32_IRQ_EXTI0_1_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI2_3_PRIORITY ${doc.STM32_IRQ_EXTI2_3_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI4_15_PRIORITY ${doc.STM32_IRQ_EXTI4_15_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI1921_PRIORITY ${doc.STM32_IRQ_EXTI1921_PRIORITY!"3"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"2"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"2"}
|
||||
#define STM32_IRQ_USART3_4_LP1_PRIORITY ${doc.STM32_IRQ_USART3_4_LP1_PRIORITY!"2"}
|
||||
|
||||
#define STM32_IRQ_TIM1_UP_PRIORITY ${doc.STM32_IRQ_TIM1_UP_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM14_PRIORITY ${doc.STM32_IRQ_TIM14_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM15_PRIORITY ${doc.STM32_IRQ_TIM15_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM16_PRIORITY ${doc.STM32_IRQ_TIM16_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM17_PRIORITY ${doc.STM32_IRQ_TIM17_PRIORITY!"1"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_CKMODE ${doc.STM32_ADC_ADC1_CKMODE!"STM32_ADC_CKMODE_ADCCLK"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_PRESCALER_VALUE ${doc.STM32_ADC_PRESCALER_VALUE!"2"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"3"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"TRUE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"2"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"2"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"2"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
* NOTE: STM32G081 only.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,318 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32G4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32G4xx_MCUCONF
|
||||
#define STM32G431_MCUCONF
|
||||
#define STM32G441_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
|
||||
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
|
||||
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
|
||||
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLLRCLK"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"6"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"85"}
|
||||
#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"8"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"2"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_PCLK1"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK1"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_PCLK1"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_PCLK1"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_SYSCLK"}
|
||||
#define STM32_I2S23SEL ${doc.STM32_I2S23SEL!"STM32_I2S23SEL_SYSCLK"}
|
||||
#define STM32_FDCANSEL ${doc.STM32_FDCANSEL!"STM32_FDCANSEL_HSE"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_HSI48"}
|
||||
#define STM32_ADC12SEL ${doc.STM32_ADC12SEL!"STM32_ADC12SEL_PLLPCLK"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_NOCLOCK"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI164041_PRIORITY ${doc.STM32_IRQ_EXTI164041_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI212229_PRIORITY ${doc.STM32_IRQ_EXTI212229_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI30_32_PRIORITY ${doc.STM32_IRQ_EXTI30_32_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI33_PRIORITY ${doc.STM32_IRQ_EXTI33_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_FDCAN1_PRIORITY ${doc.STM32_IRQ_FDCAN1_PRIORITY!"10"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_PRIORITY ${doc.STM32_IRQ_TIM8_UP_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"TRUE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"TRUE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC12_CLOCK_MODE ${doc.STM32_ADC_ADC12_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV4"}
|
||||
#define STM32_ADC_ADC12_PRESC ${doc.STM32_ADC_ADC12_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_FDCAN1 ${doc.STM32_CAN_USE_FDCAN1!"FALSE"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC3_CH1 ${doc.STM32_DAC_USE_DAC3_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC3_CH2 ${doc.STM32_DAC_USE_DAC3_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC3_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC3_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC3_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC3_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC3_CH1_DMA_STREAM ${doc.STM32_DAC_DAC3_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC3_CH2_DMA_STREAM ${doc.STM32_DAC_DAC3_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 ${doc.STM32_USB_USE_USB1!"FALSE"}
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"}
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,383 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32G4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32G4xx_MCUCONF
|
||||
#define STM32G473_MCUCONF
|
||||
#define STM32G483_MCUCONF
|
||||
#define STM32G474_MCUCONF
|
||||
#define STM32G484_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_PLS_LEV0)"}
|
||||
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_EIWF)"}
|
||||
#define STM32_PWR_CR4 ${doc.STM32_PWR_CR4!"(0U)"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
|
||||
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLLRCLK"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"6"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"85"}
|
||||
#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"8"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"2"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_SYSCLK"}
|
||||
#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_PCLK1"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_PCLK1"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_PCLK1"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_PCLK1"}
|
||||
#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_PCLK1"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_SYSCLK"}
|
||||
#define STM32_I2S23SEL ${doc.STM32_I2S23SEL!"STM32_I2S23SEL_SYSCLK"}
|
||||
#define STM32_FDCANSEL ${doc.STM32_FDCANSEL!"STM32_FDCANSEL_HSE"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_HSI48"}
|
||||
#define STM32_ADC12SEL ${doc.STM32_ADC12SEL!"STM32_ADC12SEL_PLLPCLK"}
|
||||
#define STM32_ADC345SEL ${doc.STM32_ADC345SEL!"STM32_ADC345SEL_PLLPCLK"}
|
||||
#define STM32_QSPISEL ${doc.STM32_QSPISEL!"STM32_QSPISEL_SYSCLK"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_NOCLOCK"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI164041_PRIORITY ${doc.STM32_IRQ_EXTI164041_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI212229_PRIORITY ${doc.STM32_IRQ_EXTI212229_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI30_32_PRIORITY ${doc.STM32_IRQ_EXTI30_32_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI33_PRIORITY ${doc.STM32_IRQ_EXTI33_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_FDCAN1_PRIORITY ${doc.STM32_IRQ_FDCAN1_PRIORITY!"10"}
|
||||
#define STM32_IRQ_FDCAN2_PRIORITY ${doc.STM32_IRQ_FDCAN2_PRIORITY!"10"}
|
||||
#define STM32_IRQ_FDCAN3_PRIORITY ${doc.STM32_IRQ_FDCAN3_PRIORITY!"10"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_PRIORITY ${doc.STM32_IRQ_TIM8_UP_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM20_UP_PRIORITY ${doc.STM32_IRQ_TIM20_UP_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM20_CC_PRIORITY ${doc.STM32_IRQ_TIM20_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"TRUE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"TRUE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"TRUE"}
|
||||
#define STM32_ADC_USE_ADC4 ${doc.STM32_ADC_USE_ADC4!"TRUE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC4_DMA_STREAM ${doc.STM32_ADC_ADC4_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC4_DMA_PRIORITY ${doc.STM32_ADC_ADC4_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC4_IRQ_PRIORITY ${doc.STM32_ADC_ADC4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC4_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC12_CLOCK_MODE ${doc.STM32_ADC_ADC12_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV4"}
|
||||
#define STM32_ADC_ADC345_CLOCK_MODE ${doc.STM32_ADC_ADC345_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV4"}
|
||||
#define STM32_ADC_ADC12_PRESC ${doc.STM32_ADC_ADC12_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
#define STM32_ADC_ADC345_PRESC ${doc.STM32_ADC_ADC345_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_FDCAN1 ${doc.STM32_CAN_USE_FDCAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_FDCAN2 ${doc.STM32_CAN_USE_FDCAN2!"FALSE"}
|
||||
#define STM32_CAN_USE_FDCAN3 ${doc.STM32_CAN_USE_FDCAN3!"FALSE"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC2_CH1 ${doc.STM32_DAC_USE_DAC2_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC3_CH1 ${doc.STM32_DAC_USE_DAC3_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC3_CH2 ${doc.STM32_DAC_USE_DAC3_CH2!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC4_CH1 ${doc.STM32_DAC_USE_DAC4_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC4_CH2 ${doc.STM32_DAC_USE_DAC4_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC2_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC2_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC3_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC3_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC3_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC3_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC4_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC4_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC4_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC4_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC2_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC2_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC3_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC3_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC3_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC3_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC4_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC4_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC4_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC4_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC2_CH1_DMA_STREAM ${doc.STM32_DAC_DAC2_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC3_CH1_DMA_STREAM ${doc.STM32_DAC_DAC3_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC3_CH2_DMA_STREAM ${doc.STM32_DAC_DAC3_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC4_CH1_DMA_STREAM ${doc.STM32_DAC_DAC4_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC4_CH2_DMA_STREAM ${doc.STM32_DAC_DAC4_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM17 ${doc.STM32_ICU_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM20 ${doc.STM32_PWM_USE_TIM20!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 ${doc.STM32_USB_USE_USB1!"FALSE"}
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"}
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,495 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32H7xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32H7xx_MCUCONF
|
||||
#define STM32H742_MCUCONF
|
||||
#define STM32H743_MCUCONF
|
||||
#define STM32H753_MCUCONF
|
||||
#define STM32H745_MCUCONF
|
||||
#define STM32H755_MCUCONF
|
||||
#define STM32H747_MCUCONF
|
||||
#define STM32H757_MCUCONF
|
||||
|
||||
/*
|
||||
* General settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_TARGET_CORE ${doc.STM32_TARGET_CORE!"1"}
|
||||
|
||||
/*
|
||||
* Memory attributes settings.
|
||||
*/
|
||||
#define STM32_NOCACHE_MPU_REGION ${doc.STM32_NOCACHE_MPU_REGION!"MPU_REGION_6"}
|
||||
#define STM32_NOCACHE_SRAM1_SRAM2 ${doc.STM32_NOCACHE_SRAM1_SRAM2!"FALSE"}
|
||||
#define STM32_NOCACHE_SRAM3 ${doc.STM32_NOCACHE_SRAM3!"TRUE"}
|
||||
|
||||
/*
|
||||
* PWR system settings.
|
||||
* Reading STM32 Reference Manual is required, settings in PWR_CR3 are
|
||||
* very critical.
|
||||
* Register constants are taken from the ST header.
|
||||
*/
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_SCALE1"}
|
||||
#define STM32_PWR_CR1 ${doc.STM32_PWR_CR1!"(PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)"}
|
||||
#define STM32_PWR_CR2 ${doc.STM32_PWR_CR2!"(PWR_CR2_BREN)"}
|
||||
#define STM32_PWR_CR3 ${doc.STM32_PWR_CR3!"(PWR_CR3_LDOEN | PWR_CR3_USB33DEN)"}
|
||||
#define STM32_PWR_CPUCR ${doc.STM32_PWR_CPUCR!"0"}
|
||||
|
||||
/*
|
||||
* Clock tree static settings.
|
||||
* Reading STM32 Reference Manual is required.
|
||||
*/
|
||||
#define STM32_HSI_ENABLED ${doc.STM32_HSI_ENABLED!"TRUE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_CSI_ENABLED ${doc.STM32_CSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"TRUE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_HSIDIV ${doc.STM32_HSIDIV!"STM32_HSIDIV_DIV1"}
|
||||
|
||||
/*
|
||||
* PLLs static settings.
|
||||
* Reading STM32 Reference Manual is required.
|
||||
*/
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE_CK"}
|
||||
#define STM32_PLLCFGR_MASK ${doc.STM32_PLLCFGR_MASK!"~0"}
|
||||
#define STM32_PLL1_ENABLED ${doc.STM32_PLL1_ENABLED!"TRUE"}
|
||||
#define STM32_PLL1_P_ENABLED ${doc.STM32_PLL1_P_ENABLED!"TRUE"}
|
||||
#define STM32_PLL1_Q_ENABLED ${doc.STM32_PLL1_Q_ENABLED!"TRUE"}
|
||||
#define STM32_PLL1_R_ENABLED ${doc.STM32_PLL1_R_ENABLED!"TRUE"}
|
||||
#define STM32_PLL1_DIVM_VALUE ${doc.STM32_PLL1_DIVM_VALUE!"4"}
|
||||
#define STM32_PLL1_DIVN_VALUE ${doc.STM32_PLL1_DIVN_VALUE!"400"}
|
||||
#define STM32_PLL1_FRACN_VALUE ${doc.STM32_PLL1_FRACN_VALUE!"0"}
|
||||
#define STM32_PLL1_DIVP_VALUE ${doc.STM32_PLL1_DIVP_VALUE!"2"}
|
||||
#define STM32_PLL1_DIVQ_VALUE ${doc.STM32_PLL1_DIVQ_VALUE!"16"}
|
||||
#define STM32_PLL1_DIVR_VALUE ${doc.STM32_PLL1_DIVR_VALUE!"8"}
|
||||
#define STM32_PLL2_ENABLED ${doc.STM32_PLL2_ENABLED!"TRUE"}
|
||||
#define STM32_PLL2_P_ENABLED ${doc.STM32_PLL2_P_ENABLED!"TRUE"}
|
||||
#define STM32_PLL2_Q_ENABLED ${doc.STM32_PLL2_Q_ENABLED!"TRUE"}
|
||||
#define STM32_PLL2_R_ENABLED ${doc.STM32_PLL2_R_ENABLED!"TRUE"}
|
||||
#define STM32_PLL2_DIVM_VALUE ${doc.STM32_PLL2_DIVM_VALUE!"4"}
|
||||
#define STM32_PLL2_DIVN_VALUE ${doc.STM32_PLL2_DIVN_VALUE!"400"}
|
||||
#define STM32_PLL2_FRACN_VALUE ${doc.STM32_PLL2_FRACN_VALUE!"0"}
|
||||
#define STM32_PLL2_DIVP_VALUE ${doc.STM32_PLL2_DIVP_VALUE!"40"}
|
||||
#define STM32_PLL2_DIVQ_VALUE ${doc.STM32_PLL2_DIVQ_VALUE!"8"}
|
||||
#define STM32_PLL2_DIVR_VALUE ${doc.STM32_PLL2_DIVR_VALUE!"8"}
|
||||
#define STM32_PLL3_ENABLED ${doc.STM32_PLL3_ENABLED!"TRUE"}
|
||||
#define STM32_PLL3_P_ENABLED ${doc.STM32_PLL3_P_ENABLED!"TRUE"}
|
||||
#define STM32_PLL3_Q_ENABLED ${doc.STM32_PLL3_Q_ENABLED!"TRUE"}
|
||||
#define STM32_PLL3_R_ENABLED ${doc.STM32_PLL3_R_ENABLED!"TRUE"}
|
||||
#define STM32_PLL3_DIVM_VALUE ${doc.STM32_PLL3_DIVM_VALUE!"4"}
|
||||
#define STM32_PLL3_DIVN_VALUE ${doc.STM32_PLL3_DIVN_VALUE!"400"}
|
||||
#define STM32_PLL3_FRACN_VALUE ${doc.STM32_PLL3_FRACN_VALUE!"0"}
|
||||
#define STM32_PLL3_DIVP_VALUE ${doc.STM32_PLL3_DIVP_VALUE!"8"}
|
||||
#define STM32_PLL3_DIVQ_VALUE ${doc.STM32_PLL3_DIVQ_VALUE!"8"}
|
||||
#define STM32_PLL3_DIVR_VALUE ${doc.STM32_PLL3_DIVR_VALUE!"8"}
|
||||
|
||||
/*
|
||||
* Core clocks dynamic settings (can be changed at runtime).
|
||||
* Reading STM32 Reference Manual is required.
|
||||
*/
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL1_P_CK"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSE_CK"}
|
||||
#define STM32_D1CPRE ${doc.STM32_D1CPRE!"STM32_D1CPRE_DIV1"}
|
||||
#define STM32_D1HPRE ${doc.STM32_D1HPRE!"STM32_D1HPRE_DIV2"}
|
||||
#define STM32_D1PPRE3 ${doc.STM32_D1PPRE3!"STM32_D1PPRE3_DIV2"}
|
||||
#define STM32_D2PPRE1 ${doc.STM32_D2PPRE1!"STM32_D2PPRE1_DIV2"}
|
||||
#define STM32_D2PPRE2 ${doc.STM32_D2PPRE2!"STM32_D2PPRE2_DIV2"}
|
||||
#define STM32_D3PPRE4 ${doc.STM32_D3PPRE4!"STM32_D3PPRE4_DIV2"}
|
||||
|
||||
/*
|
||||
* Peripherals clocks static settings.
|
||||
* Reading STM32 Reference Manual is required.
|
||||
*/
|
||||
#define STM32_MCO1SEL ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI_CK"}
|
||||
#define STM32_MCO1PRE_VALUE ${doc.STM32_MCO1PRE_VALUE!"4"}
|
||||
#define STM32_MCO2SEL ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYS_CK"}
|
||||
#define STM32_MCO2PRE_VALUE ${doc.STM32_MCO2PRE_VALUE!"4"}
|
||||
#define STM32_TIMPRE_ENABLE ${doc.STM32_TIMPRE_ENABLE!"TRUE"}
|
||||
#define STM32_HRTIMSEL ${doc.STM32_HRTIMSEL!"0"}
|
||||
#define STM32_STOPKERWUCK ${doc.STM32_STOPKERWUCK!"0"}
|
||||
#define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"0"}
|
||||
#define STM32_RTCPRE_VALUE ${doc.STM32_RTCPRE_VALUE!"8"}
|
||||
#define STM32_CKPERSEL ${doc.STM32_CKPERSEL!"STM32_CKPERSEL_HSE_CK"}
|
||||
#define STM32_SDMMCSEL ${doc.STM32_SDMMCSEL!"STM32_SDMMCSEL_PLL1_Q_CK"}
|
||||
#define STM32_QSPISEL ${doc.STM32_QSPISEL!"STM32_QSPISEL_HCLK"}
|
||||
#define STM32_FMCSEL ${doc.STM32_FMCSEL!"STM32_QSPISEL_HCLK"}
|
||||
#define STM32_SWPSEL ${doc.STM32_SWPSEL!"STM32_SWPSEL_PCLK1"}
|
||||
#define STM32_FDCANSEL ${doc.STM32_FDCANSEL!"STM32_FDCANSEL_HSE_CK"}
|
||||
#define STM32_DFSDM1SEL ${doc.STM32_DFSDM1SEL!"STM32_DFSDM1SEL_PCLK2"}
|
||||
#define STM32_SPDIFSEL ${doc.STM32_SPDIFSEL!"STM32_SPDIFSEL_PLL1_Q_CK"}
|
||||
#define STM32_SPI45SEL ${doc.STM32_SPI45SEL!"STM32_SPI45SEL_PCLK2"}
|
||||
#define STM32_SPI123SEL ${doc.STM32_SPI123SEL!"STM32_SPI123SEL_PLL1_Q_CK"}
|
||||
#define STM32_SAI23SEL ${doc.STM32_SAI23SEL!"STM32_SAI23SEL_PLL1_Q_CK"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_PLL1_Q_CK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_CECSEL ${doc.STM32_CECSEL!"STM32_CECSEL_LSE_CK"}
|
||||
#define STM32_USBSEL ${doc.STM32_USBSEL!"STM32_USBSEL_PLL1_Q_CK"}
|
||||
#define STM32_I2C123SEL ${doc.STM32_I2C123SEL!"STM32_I2C123SEL_PCLK1"}
|
||||
#define STM32_RNGSEL ${doc.STM32_RNGSEL!"STM32_RNGSEL_HSI48_CK"}
|
||||
#define STM32_USART16SEL ${doc.STM32_USART16SEL!"STM32_USART16SEL_PCLK2"}
|
||||
#define STM32_USART234578SEL ${doc.STM32_USART234578SEL!"STM32_USART234578SEL_PCLK1"}
|
||||
#define STM32_SPI6SEL ${doc.STM32_SPI6SEL!"STM32_SPI6SEL_PCLK4"}
|
||||
#define STM32_SAI4BSEL ${doc.STM32_SAI4BSEL!"STM32_SAI4BSEL_PLL1_Q_CK"}
|
||||
#define STM32_SAI4ASEL ${doc.STM32_SAI4ASEL!"STM32_SAI4ASEL_PLL1_Q_CK"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_PLL2_P_CK"}
|
||||
#define STM32_LPTIM345SEL ${doc.STM32_LPTIM345SEL!"STM32_LPTIM345SEL_PCLK4"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK4"}
|
||||
#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_PCLK4"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_PCLK4"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI17_PRIORITY ${doc.STM32_IRQ_EXTI17_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_21_PRIORITY ${doc.STM32_IRQ_EXTI20_21_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_FDCAN1_PRIORITY ${doc.STM32_IRQ_FDCAN1_PRIORITY!"10"}
|
||||
#define STM32_IRQ_FDCAN2_PRIORITY ${doc.STM32_IRQ_FDCAN2_PRIORITY!"10"}
|
||||
|
||||
#define STM32_IRQ_MDMA_PRIORITY ${doc.STM32_IRQ_MDMA_PRIORITY!"9"}
|
||||
|
||||
#define STM32_IRQ_QUADSPI1_PRIORITY ${doc.STM32_IRQ_QUADSPI1_PRIORITY!"10"}
|
||||
|
||||
#define STM32_IRQ_SDMMC1_PRIORITY ${doc.STM32_IRQ_SDMMC1_PRIORITY!"9"}
|
||||
#define STM32_IRQ_SDMMC2_PRIORITY ${doc.STM32_IRQ_SDMMC2_PRIORITY!"9"}
|
||||
|
||||
#define STM32_IRQ_TIM1_UP_PRIORITY ${doc.STM32_IRQ_TIM1_UP_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY ${doc.STM32_IRQ_TIM8_BRK_TIM12_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY ${doc.STM32_IRQ_TIM8_UP_TIM13_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY ${doc.STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM15_PRIORITY ${doc.STM32_IRQ_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM16_PRIORITY ${doc.STM32_IRQ_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM17_PRIORITY ${doc.STM32_IRQ_TIM17_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART6_PRIORITY ${doc.STM32_IRQ_USART6_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART7_PRIORITY ${doc.STM32_IRQ_UART7_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART8_PRIORITY ${doc.STM32_IRQ_UART8_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC12 ${doc.STM32_ADC_USE_ADC12!"TRUE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_ADC12_DMA_STREAM ${doc.STM32_ADC_ADC12_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC3_BDMA_STREAM ${doc.STM32_ADC_ADC3_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC12_DMA_PRIORITY ${doc.STM32_ADC_ADC12_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC12_CLOCK_MODE ${doc.STM32_ADC_ADC12_CLOCK_MODE!"ADC_CCR_CKMODE_ADCCK"}
|
||||
#define STM32_ADC_ADC3_CLOCK_MODE ${doc.STM32_ADC_ADC3_CLOCK_MODE!"ADC_CCR_CKMODE_ADCCK"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_FDCAN1 ${doc.STM32_CAN_USE_FDCAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_FDCAN2 ${doc.STM32_CAN_USE_FDCAN2!"FALSE"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM12 ${doc.STM32_GPT_USE_TIM12!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM13 ${doc.STM32_GPT_USE_TIM13!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM14 ${doc.STM32_GPT_USE_TIM14!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C4_RX_BDMA_STREAM ${doc.STM32_I2C_I2C4_RX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C4_TX_BDMA_STREAM ${doc.STM32_I2C_I2C4_TX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM12 ${doc.STM32_ICU_USE_TIM12!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM13 ${doc.STM32_ICU_USE_TIM13!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM14 ${doc.STM32_ICU_USE_TIM14!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM17 ${doc.STM32_ICU_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* MAC driver system settings.
|
||||
*/
|
||||
#define STM32_MAC_TRANSMIT_BUFFERS ${doc.STM32_MAC_TRANSMIT_BUFFERS!"2"}
|
||||
#define STM32_MAC_RECEIVE_BUFFERS ${doc.STM32_MAC_RECEIVE_BUFFERS!"4"}
|
||||
#define STM32_MAC_BUFFERS_SIZE ${doc.STM32_MAC_BUFFERS_SIZE!"1522"}
|
||||
#define STM32_MAC_PHY_TIMEOUT ${doc.STM32_MAC_PHY_TIMEOUT!"100"}
|
||||
#define STM32_MAC_ETH1_CHANGE_PHY_STATE ${doc.STM32_MAC_ETH1_CHANGE_PHY_STATE!"TRUE"}
|
||||
#define STM32_MAC_ETH1_IRQ_PRIORITY ${doc.STM32_MAC_ETH1_IRQ_PRIORITY!"13"}
|
||||
#define STM32_MAC_IP_CHECKSUM_OFFLOAD ${doc.STM32_MAC_IP_CHECKSUM_OFFLOAD!"0"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM12 ${doc.STM32_PWM_USE_TIM12!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM13 ${doc.STM32_PWM_USE_TIM13!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM14 ${doc.STM32_PWM_USE_TIM14!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_USE_SDMMC2 ${doc.STM32_SDC_USE_SDMMC2!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC_PWRSAV ${doc.STM32_SDC_SDMMC_PWRSAV!"TRUE"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART6 ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART7 ${doc.STM32_SERIAL_USE_UART7!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART8 ${doc.STM32_SERIAL_USE_UART8!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI4 ${doc.STM32_SPI_USE_SPI4!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI5 ${doc.STM32_SPI_USE_SPI5!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI6 ${doc.STM32_SPI_USE_SPI6!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI4_RX_DMA_STREAM ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI4_TX_DMA_STREAM ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI5_RX_DMA_STREAM ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI5_TX_DMA_STREAM ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI6_RX_BDMA_STREAM ${doc.STM32_SPI_SPI6_RX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI6_TX_BDMA_STREAM ${doc.STM32_SPI_SPI6_TX_BDMA_STREAM!"STM32_BDMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI4_DMA_PRIORITY ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI5_DMA_PRIORITY ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI6_DMA_PRIORITY ${doc.STM32_SPI_SPI6_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI4_IRQ_PRIORITY ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI5_IRQ_PRIORITY ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI6_IRQ_PRIORITY ${doc.STM32_SPI_SPI6_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USE_USART6 ${doc.STM32_UART_USE_USART6!"FALSE"}
|
||||
#define STM32_UART_USE_UART7 ${doc.STM32_UART_USE_UART7!"FALSE"}
|
||||
#define STM32_UART_USE_UART8 ${doc.STM32_UART_USE_UART8!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART6_RX_DMA_STREAM ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART6_TX_DMA_STREAM ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART7_RX_DMA_STREAM ${doc.STM32_UART_UART7_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART7_TX_DMA_STREAM ${doc.STM32_UART_UART7_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART8_RX_DMA_STREAM ${doc.STM32_UART_UART8_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART8_TX_DMA_STREAM ${doc.STM32_UART_UART8_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART6_DMA_PRIORITY ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART7_DMA_PRIORITY ${doc.STM32_UART_UART7_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART8_DMA_PRIORITY ${doc.STM32_UART_UART8_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_USE_OTG2 ${doc.STM32_USB_USE_OTG2!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG2_IRQ_PRIORITY ${doc.STM32_USB_OTG2_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
#define STM32_USB_OTG2_RX_FIFO_SIZE ${doc.STM32_USB_OTG2_RX_FIFO_SIZE!"1024"}
|
||||
#define STM32_USB_HOST_WAKEUP_DURATION ${doc.STM32_USB_HOST_WAKEUP_DURATION!"2"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
|
||||
#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL ${doc.STM32_WSPI_QUADSPI1_MDMA_CHANNEL!"STM32_MDMA_CHANNEL_ID_ANY"}
|
||||
#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY ${doc.STM32_WSPI_QUADSPI1_MDMA_PRIORITY!"1"}
|
||||
#define STM32_WSPI_MDMA_ERROR_HOOK(qspip) ${doc.STM32_WSPI_MDMA_ERROR_HOOK!"osalSysHalt(\"MDMA failure\")"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32L0xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 3...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32L0xx_MCUCONF
|
||||
#define STM32L052_MCUCONF
|
||||
#define STM32L053_MCUCONF
|
||||
#define STM32L062_MCUCONF
|
||||
#define STM32L063_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_1P8"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
|
||||
#define STM32_HSI16_DIVIDER_ENABLED ${doc.STM32_HSI16_DIVIDER_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_ADC_CLOCK_ENABLED ${doc.STM32_ADC_CLOCK_ENABLED!"TRUE"}
|
||||
#define STM32_USB_CLOCK_ENABLED ${doc.STM32_USB_CLOCK_ENABLED!"TRUE"}
|
||||
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_2M"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSI16"}
|
||||
#define STM32_PLLMUL_VALUE ${doc.STM32_PLLMUL_VALUE!"4"}
|
||||
#define STM32_PLLDIV_VALUE ${doc.STM32_PLLDIV_VALUE!"2"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_APB"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_APB"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_APB"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_APB"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_APB"}
|
||||
#define STM32_HSI48SEL ${doc.STM32_HSI48SEL!"STM32_HSI48SEL_HSI48"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSE"}
|
||||
#define STM32_RTCPRE ${doc.STM32_RTCPRE!"STM32_RTCPRE_DIV2"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_1_PRIORITY ${doc.STM32_IRQ_EXTI0_1_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI2_3_PRIORITY ${doc.STM32_IRQ_EXTI2_3_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI4_15_PRIORITY ${doc.STM32_IRQ_EXTI4_15_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI17_20_PRIORITY ${doc.STM32_IRQ_EXTI17_20_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"3"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"3"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"3"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"3"}
|
||||
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM21_PRIORITY ${doc.STM32_IRQ_TIM21_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM22_PRIORITY ${doc.STM32_IRQ_TIM22_PRIORITY!"1"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
* Note, IRQ is shared with EXT channels 21 and 22.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_CKMODE ${doc.STM32_ADC_ADC1_CKMODE!"STM32_ADC_CKMODE_ADCCLK"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_PRESCALER_VALUE ${doc.STM32_ADC_PRESCALER_VALUE!"2"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM21 ${doc.STM32_GPT_USE_TIM21!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM22 ${doc.STM32_GPT_USE_TIM22!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"3"}
|
||||
#define STM32_I2C_USE_DMA ${doc.STM32_I2C_USE_DMA!"TRUE"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM21 ${doc.STM32_ICU_USE_TIM21!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM22 ${doc.STM32_ICU_USE_TIM22!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM21 ${doc.STM32_PWM_USE_TIM21!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM22 ${doc.STM32_PWM_USE_TIM22!"FALSE"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"TRUE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"2"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"21"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"3"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,253 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2019 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
/*
|
||||
* STM32L0xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 3...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#define STM32L0xx_MCUCONF
|
||||
#define STM32L072_MCUCONF
|
||||
#define STM32L073_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_1P8"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"TRUE"}
|
||||
#define STM32_HSI16_DIVIDER_ENABLED ${doc.STM32_HSI16_DIVIDER_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"TRUE"}
|
||||
#define STM32_ADC_CLOCK_ENABLED ${doc.STM32_ADC_CLOCK_ENABLED!"TRUE"}
|
||||
#define STM32_USB_CLOCK_ENABLED ${doc.STM32_USB_CLOCK_ENABLED!"TRUE"}
|
||||
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_2M"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSI16"}
|
||||
#define STM32_PLLMUL_VALUE ${doc.STM32_PLLMUL_VALUE!"4"}
|
||||
#define STM32_PLLDIV_VALUE ${doc.STM32_PLLDIV_VALUE!"2"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_APB"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_APB"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_APB"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_APB"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_APB"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_APB"}
|
||||
#define STM32_HSI48SEL ${doc.STM32_HSI48SEL!"STM32_HSI48SEL_HSI48"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSE"}
|
||||
#define STM32_RTCPRE ${doc.STM32_RTCPRE!"STM32_RTCPRE_DIV2"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_1_PRIORITY ${doc.STM32_IRQ_EXTI0_1_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI2_3_PRIORITY ${doc.STM32_IRQ_EXTI2_3_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI4_15_PRIORITY ${doc.STM32_IRQ_EXTI4_15_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI16_PRIORITY ${doc.STM32_IRQ_EXTI16_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI17_20_PRIORITY ${doc.STM32_IRQ_EXTI17_20_PRIORITY!"3"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"3"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"3"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"3"}
|
||||
#define STM32_IRQ_USART4_5_PRIORITY ${doc.STM32_IRQ_USART4_5_PRIORITY!"3"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"3"}
|
||||
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM21_PRIORITY ${doc.STM32_IRQ_TIM21_PRIORITY!"1"}
|
||||
#define STM32_IRQ_TIM22_PRIORITY ${doc.STM32_IRQ_TIM22_PRIORITY!"1"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
* Note, IRQ is shared with EXT channels 21 and 22.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_CKMODE ${doc.STM32_ADC_ADC1_CKMODE!"STM32_ADC_CKMODE_ADCCLK"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_PRESCALER_VALUE ${doc.STM32_ADC_PRESCALER_VALUE!"2"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"3"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM21 ${doc.STM32_GPT_USE_TIM21!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM22 ${doc.STM32_GPT_USE_TIM22!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"3"}
|
||||
#define STM32_I2C_USE_DMA ${doc.STM32_I2C_USE_DMA!"TRUE"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"1"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM21 ${doc.STM32_ICU_USE_TIM21!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM22 ${doc.STM32_ICU_USE_TIM22!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM21 ${doc.STM32_PWM_USE_TIM21!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM22 ${doc.STM32_PWM_USE_TIM22!"FALSE"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"TRUE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"2"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"21"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"3"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"3"}
|
||||
#define STM32_UART_USART4_5_IRQ_PRIORITY ${doc.STM32_UART_USART4_5_IRQ_PRIORITY!"3"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 ${doc.STM32_USB_USE_USB1!"TRUE"}
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"0"}
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"0"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32L4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32L4xx_MCUCONF
|
||||
#define STM32L432_MCUCONF
|
||||
#define STM32L433_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"}
|
||||
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"}
|
||||
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}
|
||||
#define STM32_MSISRANGE ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"80"}
|
||||
#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"6"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"4"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"}
|
||||
#define STM32_PLLSAI1PDIV_VALUE ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
|
||||
#define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"}
|
||||
#define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"}
|
||||
#define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
|
||||
#define STM32_SWPMI1SEL ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1635_38_PRIORITY ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}
|
||||
#define STM32_ADC_ADC123_PRESC ${doc.STM32_ADC_ADC123_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
#define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_LPUART1_PRIORITY ${doc.STM32_SERIAL_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 ${doc.STM32_USB_USE_USB1!"FALSE"}
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"}
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32L4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32L4xx_MCUCONF
|
||||
#define STM32L452_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"}
|
||||
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"}
|
||||
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}
|
||||
#define STM32_MSISRANGE ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"80"}
|
||||
#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"6"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"4"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"}
|
||||
#define STM32_PLLSAI1PDIV_VALUE ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
|
||||
#define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"}
|
||||
#define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"}
|
||||
#define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_SYSCLK"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
|
||||
#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_SYSCLK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
|
||||
#define STM32_SWPMI1SEL ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1635_38_PRIORITY ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}
|
||||
#define STM32_ADC_ADC123_PRESC ${doc.STM32_ADC_ADC123_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC1_DMA_PRIORITY ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
|
||||
#define STM32_SDC_SDMMC1_DMA_STREAM ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
#define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART3_PRIORITY ${doc.STM32_SERIAL_USART3_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART4_PRIORITY ${doc.STM32_SERIAL_UART4_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_LPUART1_PRIORITY ${doc.STM32_SERIAL_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,362 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32L4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32L4xx_MCUCONF
|
||||
#define STM32L476_MCUCONF
|
||||
#define STM32L486_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"}
|
||||
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}
|
||||
#define STM32_MSISRANGE ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"80"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"6"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"4"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"}
|
||||
#define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"}
|
||||
#define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"}
|
||||
#define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"}
|
||||
#define STM32_PLLSAI2N_VALUE ${doc.STM32_PLLSAI2N_VALUE!"72"}
|
||||
#define STM32_PLLSAI2P_VALUE ${doc.STM32_PLLSAI2P_VALUE!"7"}
|
||||
#define STM32_PLLSAI2R_VALUE ${doc.STM32_PLLSAI2R_VALUE!"6"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_SYSCLK"}
|
||||
#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_SYSCLK"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
|
||||
#define STM32_SWPMI1SEL ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"}
|
||||
#define STM32_DFSDMSEL ${doc.STM32_DFSDMSEL!"STM32_DFSDMSEL_PCLK2"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1635_38_PRIORITY ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_PRIORITY ${doc.STM32_IRQ_TIM8_UP_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_DUAL_MODE ${doc.STM32_ADC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}
|
||||
#define STM32_ADC_ADC123_PRESC ${doc.STM32_ADC_ADC123_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM17 ${doc.STM32_ICU_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC1_DMA_PRIORITY ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
|
||||
#define STM32_SDC_SDMMC1_DMA_STREAM ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
#define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART3_PRIORITY ${doc.STM32_SERIAL_USART3_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART4_PRIORITY ${doc.STM32_SERIAL_UART4_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART5_PRIORITY ${doc.STM32_SERIAL_UART5_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_LPUART1_PRIORITY ${doc.STM32_SERIAL_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,372 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32L4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32L4xx_MCUCONF
|
||||
#define STM32L496_MCUCONF
|
||||
#define STM32L4A6_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"}
|
||||
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"}
|
||||
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}
|
||||
#define STM32_MSISRANGE ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"80"}
|
||||
#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"6"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"4"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"}
|
||||
#define STM32_PLLSAI1PDIV_VALUE ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
|
||||
#define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"}
|
||||
#define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"}
|
||||
#define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"}
|
||||
#define STM32_PLLSAI2N_VALUE ${doc.STM32_PLLSAI2N_VALUE!"72"}
|
||||
#define STM32_PLLSAI2PDIV_VALUE ${doc.STM32_PLLSAI2PDIV_VALUE!"6"}
|
||||
#define STM32_PLLSAI2P_VALUE ${doc.STM32_PLLSAI2P_VALUE!"7"}
|
||||
#define STM32_PLLSAI2R_VALUE ${doc.STM32_PLLSAI2R_VALUE!"6"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_SYSCLK"}
|
||||
#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_SYSCLK"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
|
||||
#define STM32_SWPMI1SEL ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"}
|
||||
#define STM32_DFSDMSEL ${doc.STM32_DFSDMSEL!"STM32_DFSDMSEL_PCLK2"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1635_38_PRIORITY ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_PRIORITY ${doc.STM32_IRQ_TIM8_UP_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC3 ${doc.STM32_ADC_USE_ADC3!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_ADC_ADC3_DMA_STREAM ${doc.STM32_ADC_ADC3_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY ${doc.STM32_ADC_ADC3_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC3_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}
|
||||
#define STM32_ADC_ADC123_PRESC ${doc.STM32_ADC_ADC123_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_USE_CAN2 ${doc.STM32_CAN_USE_CAN2!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
#define STM32_CAN_CAN2_IRQ_PRIORITY ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM17 ${doc.STM32_ICU_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC1_DMA_PRIORITY ${doc.STM32_SDC_SDMMC1_DMA_PRIORITY!"3"}
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
|
||||
#define STM32_SDC_SDMMC1_DMA_STREAM ${doc.STM32_SDC_SDMMC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
#define STM32_SERIAL_USART1_PRIORITY ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART2_PRIORITY ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_USART3_PRIORITY ${doc.STM32_SERIAL_USART3_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART4_PRIORITY ${doc.STM32_SERIAL_UART4_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_UART5_PRIORITY ${doc.STM32_SERIAL_UART5_PRIORITY!"12"}
|
||||
#define STM32_SERIAL_LPUART1_PRIORITY ${doc.STM32_SERIAL_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
|
||||
#define STM32_UART_USART1_IRQ_PRIORITY ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART2_IRQ_PRIORITY ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART3_IRQ_PRIORITY ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART4_IRQ_PRIORITY ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_UART5_IRQ_PRIORITY ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,374 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS.
|
||||
|
||||
ChibiOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--]
|
||||
[@pp.dropOutputFile /]
|
||||
[#import "/@lib/libutils.ftl" as utils /]
|
||||
[#import "/@lib/liblicense.ftl" as license /]
|
||||
[@pp.changeOutputFile name="mcuconf.h" /]
|
||||
/*
|
||||
[@license.EmitLicenseAsText /]
|
||||
*/
|
||||
|
||||
/*
|
||||
* STM32L4xx drivers configuration.
|
||||
* The following settings override the default settings present in
|
||||
* the various device driver implementation headers.
|
||||
* Note that the settings for each driver only have effect if the whole
|
||||
* driver is enabled in halconf.h.
|
||||
*
|
||||
* IRQ priorities:
|
||||
* 15...0 Lowest...Highest.
|
||||
*
|
||||
* DMA priorities:
|
||||
* 0...3 Lowest...Highest.
|
||||
*/
|
||||
|
||||
#ifndef MCUCONF_H
|
||||
#define MCUCONF_H
|
||||
|
||||
#define STM32L4xx_MCUCONF
|
||||
#define STM32L4R5_MCUCONF
|
||||
#define STM32L4S5_MCUCONF
|
||||
#define STM32L4R7_MCUCONF
|
||||
#define STM32L4S7_MCUCONF
|
||||
#define STM32L4R9_MCUCONF
|
||||
#define STM32L4S9_MCUCONF
|
||||
|
||||
/*
|
||||
* HAL driver system settings.
|
||||
*/
|
||||
#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
|
||||
#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
|
||||
#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
|
||||
#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
|
||||
#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"}
|
||||
#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
|
||||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"}
|
||||
#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}
|
||||
#define STM32_MSISRANGE ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
|
||||
#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}
|
||||
#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"}
|
||||
#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"60"}
|
||||
#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"}
|
||||
#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
|
||||
#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"4"}
|
||||
#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"2"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
|
||||
#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
|
||||
#define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
#define STM32_PLLSAI1M_VALUE ${doc.STM32_PLLSAI1M_VALUE!"1"}
|
||||
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"}
|
||||
#define STM32_PLLSAI1PDIV_VALUE ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
|
||||
#define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"}
|
||||
#define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"}
|
||||
#define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"}
|
||||
#define STM32_PLLSAI2M_VALUE ${doc.STM32_PLLSAI2M_VALUE!"1"}
|
||||
#define STM32_PLLSAI2N_VALUE ${doc.STM32_PLLSAI2N_VALUE!"72"}
|
||||
#define STM32_PLLSAI2PDIV_VALUE ${doc.STM32_PLLSAI2PDIV_VALUE!"6"}
|
||||
#define STM32_PLLSAI2P_VALUE ${doc.STM32_PLLSAI2P_VALUE!"7"}
|
||||
#define STM32_PLLSAI2Q_VALUE ${doc.STM32_PLLSAI2Q_VALUE!"6"}
|
||||
#define STM32_PLLSAI2R_VALUE ${doc.STM32_PLLSAI2R_VALUE!"6"}
|
||||
#define STM32_PLLSAI2DIVR ${doc.STM32_PLLSAI2DIVR!"STM32_PLLSAI2DIVR_DIV16"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_USART3SEL ${doc.STM32_USART3SEL!"STM32_USART3SEL_SYSCLK"}
|
||||
#define STM32_UART4SEL ${doc.STM32_UART4SEL!"STM32_UART4SEL_SYSCLK"}
|
||||
#define STM32_UART5SEL ${doc.STM32_UART5SEL!"STM32_UART5SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}
|
||||
#define STM32_I2C2SEL ${doc.STM32_I2C2SEL!"STM32_I2C2SEL_SYSCLK"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
|
||||
#define STM32_I2C4SEL ${doc.STM32_I2C4SEL!"STM32_I2C4SEL_SYSCLK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLLSAI1"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
|
||||
#define STM32_DFSDMSEL ${doc.STM32_DFSDMSEL!"STM32_DFSDMSEL_PCLK2"}
|
||||
#define STM32_ADFSDMSEL ${doc.STM32_ADFSDMSEL!"STM32_ADFSDMSEL_SAI1CLK"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_SAI2SEL ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
|
||||
#define STM32_DSISEL ${doc.STM32_DSISEL!"STM32_DSISEL_DSIPHY"}
|
||||
#define STM32_SDMMCSEL ${doc.STM32_SDMMC!"STM32_SDMMCSEL_48CLK"}
|
||||
#define STM32_OSPISEL ${doc.STM32_OSPISEL!"STM32_OSPISEL_SYSCLK"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1635_38_PRIORITY ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_SDMMC1_PRIORITY ${doc.STM32_IRQ_SDMMC1_PRIORITY!"9"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM3_PRIORITY ${doc.STM32_IRQ_TIM3_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM4_PRIORITY ${doc.STM32_IRQ_TIM4_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM5_PRIORITY ${doc.STM32_IRQ_TIM5_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_UP_PRIORITY ${doc.STM32_IRQ_TIM8_UP_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM8_CC_PRIORITY ${doc.STM32_IRQ_TIM8_CC_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART3_PRIORITY ${doc.STM32_IRQ_USART3_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART4_PRIORITY ${doc.STM32_IRQ_UART4_PRIORITY!"12"}
|
||||
#define STM32_IRQ_UART5_PRIORITY ${doc.STM32_IRQ_UART5_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV2"}
|
||||
#define STM32_ADC_ADC123_PRESC ${doc.STM32_ADC_ADC123_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 ${doc.STM32_CAN_USE_CAN1!"FALSE"}
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
|
||||
|
||||
/*
|
||||
* DAC driver system settings.
|
||||
*/
|
||||
#define STM32_DAC_DUAL_MODE ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH1 ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
|
||||
#define STM32_DAC_USE_DAC1_CH2 ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
|
||||
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
|
||||
#define STM32_DAC_DAC1_CH1_DMA_STREAM ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_DAC_DAC1_CH2_DMA_STREAM ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM3 ${doc.STM32_GPT_USE_TIM3!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM4 ${doc.STM32_GPT_USE_TIM4!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM5 ${doc.STM32_GPT_USE_TIM5!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM8 ${doc.STM32_GPT_USE_TIM8!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM17 ${doc.STM32_GPT_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C2 ${doc.STM32_I2C_USE_I2C2!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C4 ${doc.STM32_I2C_USE_I2C4!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_RX_DMA_STREAM ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C2_TX_DMA_STREAM ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C4_RX_DMA_STREAM ${doc.STM32_I2C_I2C4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C4_TX_DMA_STREAM ${doc.STM32_I2C_I2C4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C2_IRQ_PRIORITY ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C4_IRQ_PRIORITY ${doc.STM32_I2C_I2C4_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C2_DMA_PRIORITY ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C4_DMA_PRIORITY ${doc.STM32_I2C_I2C4_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM3 ${doc.STM32_ICU_USE_TIM3!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM4 ${doc.STM32_ICU_USE_TIM4!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM5 ${doc.STM32_ICU_USE_TIM5!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM8 ${doc.STM32_ICU_USE_TIM8!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM17 ${doc.STM32_ICU_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM3 ${doc.STM32_PWM_USE_TIM3!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM4 ${doc.STM32_PWM_USE_TIM4!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM5 ${doc.STM32_PWM_USE_TIM5!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM8 ${doc.STM32_PWM_USE_TIM8!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM17 ${doc.STM32_PWM_USE_TIM17!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SDC driver system settings.
|
||||
*/
|
||||
#define STM32_SDC_USE_SDMMC1 ${doc.STM32_SDC_USE_SDMMC1!"FALSE"}
|
||||
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT ${doc.STM32_SDC_SDMMC_UNALIGNED_SUPPORT!"TRUE"}
|
||||
#define STM32_SDC_SDMMC_WRITE_TIMEOUT ${doc.STM32_SDC_SDMMC_WRITE_TIMEOUT!"1000000"}
|
||||
#define STM32_SDC_SDMMC_READ_TIMEOUT ${doc.STM32_SDC_SDMMC_READ_TIMEOUT!"1000000"}
|
||||
#define STM32_SDC_SDMMC_CLOCK_DELAY ${doc.STM32_SDC_SDMMC_CLOCK_DELAY!"10"}
|
||||
#define STM32_SDC_SDMMC_PWRSAV ${doc.STM32_SDC_SDMMC_PWRSAV!"TRUE"}
|
||||
#define STM32_SDC_SDMMC1_IRQ_PRIORITY ${doc.STM32_SDC_SDMMC1_IRQ_PRIORITY!"9"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART3 ${doc.STM32_SERIAL_USE_USART3!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART4 ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
|
||||
#define STM32_SERIAL_USE_UART5 ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI2 ${doc.STM32_SPI_USE_SPI2!"FALSE"}
|
||||
#define STM32_SPI_USE_SPI3 ${doc.STM32_SPI_USE_SPI3!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_RX_DMA_STREAM ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI2_TX_DMA_STREAM ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_RX_DMA_STREAM ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI3_TX_DMA_STREAM ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI2_DMA_PRIORITY ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI3_DMA_PRIORITY ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI2_IRQ_PRIORITY ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_SPI3_IRQ_PRIORITY ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USE_USART3 ${doc.STM32_UART_USE_USART3!"FALSE"}
|
||||
#define STM32_UART_USE_UART4 ${doc.STM32_UART_USE_UART4!"FALSE"}
|
||||
#define STM32_UART_USE_UART5 ${doc.STM32_UART_USE_UART5!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_RX_DMA_STREAM ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART3_TX_DMA_STREAM ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_RX_DMA_STREAM ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART4_TX_DMA_STREAM ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART5_RX_DMA_STREAM ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_UART5_TX_DMA_STREAM ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_UART_USART1_DMA_PRIORITY ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART2_DMA_PRIORITY ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_USART3_DMA_PRIORITY ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART4_DMA_PRIORITY ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_UART5_DMA_PRIORITY ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_OTG1 ${doc.STM32_USB_USE_OTG1!"FALSE"}
|
||||
#define STM32_USB_OTG1_IRQ_PRIORITY ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
|
||||
#define STM32_USB_OTG1_RX_FIFO_SIZE ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_OCTOSPI1 ${doc.STM32_WSPI_USE_OCTOSPI1!"FALSE"}
|
||||
#define STM32_WSPI_USE_OCTOSPI2 ${doc.STM32_WSPI_USE_OCTOSPI2!"FALSE"}
|
||||
#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI1_PRESCALER_VALUE!"1"}
|
||||
#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE ${doc.STM32_WSPI_OCTOSPI2_PRESCALER_VALUE!"1"}
|
||||
#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_IRQ_PRIORITY!"10"}
|
||||
#define STM32_WSPI_OCTOSPI1_DMA_STREAM ${doc.STM32_WSPI_OCTOSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_WSPI_OCTOSPI2_DMA_STREAM ${doc.STM32_WSPI_OCTOSPI2_DMA_STREAM!"STM32_DMA_STREAM_ID_ANY"}
|
||||
#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_DMA_PRIORITY!"1"}
|
||||
#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY!"10"}
|
||||
#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY ${doc.STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY!"10"}
|
||||
#define STM32_WSPI_DMA_ERROR_HOOK(qspip) ${doc.STM32_WSPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
To quickly turn a configuration file into a template search/replace the file
|
||||
with the following regular expressions in notepad++:
|
||||
|
||||
Search: ^#define\s([\w()]+)( +)([\S].*)$
|
||||
Replace with: #define \1\2${doc.\1!"\3"}
|
||||
|
||||
Minor further edits are often required.
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS/RT - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
--]
|
||||
[#import "/@ftllibs/libutils.ftl" as utils /]
|
||||
[#list xml.*.application.instances.instance as inst]
|
||||
[#if inst.@id?string == "org.chibios.spc5.components.portable.chibios_unitary_tests_engine"]
|
||||
[#assign instance = inst /]
|
||||
[#break]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#assign conf = {"instance":instance} /]
|
||||
[#assign prefix_lower = conf.instance.global_data_and_code.code_prefix.value[0]?trim?lower_case /]
|
||||
[#assign prefix_upper = conf.instance.global_data_and_code.code_prefix.value[0]?trim?upper_case /]
|
||||
[@pp.dropOutputFile /]
|
||||
[@pp.changeOutputFile name=prefix_lower+"test_root.c" /]
|
||||
[@utils.EmitIndentedCCode "" 2 conf.instance.description.copyright.value[0] /]
|
||||
|
||||
/**
|
||||
* @mainpage Test Suite Specification
|
||||
[#if conf.instance.description.introduction.value[0]?trim != ""]
|
||||
[@utils.FormatStringAsText " * "
|
||||
" * "
|
||||
utils.WithDot(conf.instance.description.introduction.value[0]?trim?cap_first)
|
||||
72 /]
|
||||
[#else]
|
||||
* No introduction.
|
||||
[/#if]
|
||||
*
|
||||
* <h2>Test Sequences</h2>
|
||||
[#if conf.instance.sequences.sequence?size > 0]
|
||||
[#list conf.instance.sequences.sequence as sequence]
|
||||
* - @subpage ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")}
|
||||
[/#list]
|
||||
* .
|
||||
[#else]
|
||||
* No test sequences defined in the test suite.
|
||||
[/#if]
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file ${prefix_lower}test_root.c
|
||||
* @brief Test Suite root structures code.
|
||||
*/
|
||||
|
||||
#include "hal.h"
|
||||
#include "${prefix_lower}test_root.h"
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Module exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Array of test sequences.
|
||||
*/
|
||||
const testsequence_t * const ${prefix_lower}test_suite_array[] = {
|
||||
[#list conf.instance.sequences.sequence as sequence]
|
||||
[#if sequence.condition.value[0]?trim?length > 0]
|
||||
#if (${sequence.condition.value[0]}) || defined(__DOXYGEN__)
|
||||
[/#if]
|
||||
&${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")},
|
||||
[#if sequence.condition.value[0]?trim?length > 0]
|
||||
#endif
|
||||
[/#if]
|
||||
[/#list]
|
||||
NULL
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Test suite root structure.
|
||||
*/
|
||||
const testsuite_t ${prefix_lower}test_suite = {
|
||||
"${utils.WithoutDot(conf.instance.description.brief.value[0]?trim)}",
|
||||
${prefix_lower}test_suite_array
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Shared code. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if conf.instance.global_data_and_code.global_code.value[0]?trim?length > 0]
|
||||
[@utils.EmitIndentedCCode "" 2 conf.instance.global_data_and_code.global_code.value[0] /]
|
||||
|
||||
[/#if]
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS/RT - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
--]
|
||||
[#import "/@ftllibs/libutils.ftl" as utils /]
|
||||
[#list xml.*.application.instances.instance as inst]
|
||||
[#if inst.@id?string == "org.chibios.spc5.components.portable.chibios_unitary_tests_engine"]
|
||||
[#assign instance = inst /]
|
||||
[#break]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#assign conf = {"instance":instance} /]
|
||||
[#assign prefix_lower = conf.instance.global_data_and_code.code_prefix.value[0]?trim?lower_case /]
|
||||
[#assign prefix_upper = conf.instance.global_data_and_code.code_prefix.value[0]?trim?upper_case /]
|
||||
[@pp.dropOutputFile /]
|
||||
[@pp.changeOutputFile name=prefix_lower+"test_root.h" /]
|
||||
[@utils.EmitIndentedCCode "" 2 conf.instance.description.copyright.value[0] /]
|
||||
|
||||
/**
|
||||
* @file ${prefix_lower}test_root.h
|
||||
* @brief Test Suite root structures header.
|
||||
*/
|
||||
|
||||
#ifndef ${prefix_upper}TEST_ROOT_H
|
||||
#define ${prefix_upper}TEST_ROOT_H
|
||||
|
||||
#include "ch_test.h"
|
||||
|
||||
[#list conf.instance.sequences.sequence as sequence]
|
||||
#include "${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")}.h"
|
||||
[/#list]
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
extern const testsuite_t ${prefix_lower}test_suite;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Shared definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
[#if conf.instance.global_data_and_code.global_definitions.value[0]?trim?length > 0]
|
||||
[@utils.EmitIndentedCCode "" 2 conf.instance.global_data_and_code.global_definitions.value[0] /]
|
||||
|
||||
[/#if]
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
#endif /* ${prefix_upper}TEST_ROOT_H */
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS/RT - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
--]
|
||||
[#import "/@ftllibs/libutils.ftl" as utils /]
|
||||
[@pp.dropOutputFile /]
|
||||
[#list xml.*.application.instances.instance as inst]
|
||||
[#if inst.@id?string == "org.chibios.spc5.components.portable.chibios_unitary_tests_engine"]
|
||||
[#assign instance = inst /]
|
||||
[#break]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#assign conf = {"instance":instance} /]
|
||||
[#assign prefix_lower = conf.instance.global_data_and_code.code_prefix.value[0]?trim?lower_case /]
|
||||
[#assign prefix_upper = conf.instance.global_data_and_code.code_prefix.value[0]?trim?upper_case /]
|
||||
[#list conf.instance.sequences.sequence as sequence]
|
||||
[@pp.changeOutputFile name=prefix_lower+"test_sequence_" + (sequence_index + 1)?string("000") + ".c" /]
|
||||
[@utils.EmitIndentedCCode "" 2 conf.instance.description.copyright.value[0] /]
|
||||
|
||||
#include "hal.h"
|
||||
#include "${prefix_lower}test_root.h"
|
||||
|
||||
/**
|
||||
* @file ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")}.c
|
||||
* @brief Test Sequence ${(sequence_index + 1)?string("000")} code.
|
||||
*
|
||||
* @page ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")} [${(sequence_index + 1)?string}] ${utils.WithoutDot(sequence.brief.value[0]?string)}
|
||||
*
|
||||
* File: @ref ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")}.c
|
||||
*
|
||||
* <h2>Description</h2>
|
||||
[@utils.FormatStringAsText " * "
|
||||
" * "
|
||||
utils.WithDot(sequence.description.value[0]?string)
|
||||
72 /]
|
||||
*
|
||||
[#if sequence.condition.value[0]?trim?length > 0]
|
||||
* <h2>Conditions</h2>
|
||||
* This sequence is only executed if the following preprocessor condition
|
||||
* evaluates to true:
|
||||
* - ${sequence.condition.value[0]}
|
||||
* .
|
||||
*
|
||||
[/#if]
|
||||
* <h2>Test Cases</h2>
|
||||
[#if sequence.cases.case?size > 0]
|
||||
[#list sequence.cases.case as case]
|
||||
* - @subpage ${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")}
|
||||
[/#list]
|
||||
* .
|
||||
[#else]
|
||||
* No test cases defined in the test sequence.
|
||||
[/#if]
|
||||
*/
|
||||
|
||||
[#if sequence.condition.value[0]?trim?length > 0]
|
||||
#if (${sequence.condition.value[0]}) || defined(__DOXYGEN__)
|
||||
|
||||
[/#if]
|
||||
/****************************************************************************
|
||||
* Shared code.
|
||||
****************************************************************************/
|
||||
|
||||
[#if sequence.shared_code.value[0]?trim?length > 0]
|
||||
[@utils.EmitIndentedCCode "" 2 sequence.shared_code.value[0] /]
|
||||
[/#if]
|
||||
|
||||
/****************************************************************************
|
||||
* Test cases.
|
||||
****************************************************************************/
|
||||
|
||||
[#list sequence.cases.case as case]
|
||||
[#-- Building the sequence of the requirements covered by
|
||||
this test case.--]
|
||||
[#assign reqseq = [] /]
|
||||
[#list case.steps.step as step]
|
||||
[#assign reqseq = reqseq + step.tags.value[0]?string?trim?word_list /]
|
||||
[/#list]
|
||||
[#assign reqseq = reqseq?sort /]
|
||||
[#-- Checking if a condition should be generated.--]
|
||||
[#if case.condition.value[0]?trim?length > 0]
|
||||
#if (${case.condition.value[0]?trim}) || defined(__DOXYGEN__)
|
||||
[/#if]
|
||||
[#-- Header generation.--]
|
||||
/**
|
||||
* @page ${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")} [${(sequence_index + 1)?string}.${(case_index + 1)?string}] ${utils.WithoutDot(case.brief.value[0])}
|
||||
*
|
||||
* <h2>Description</h2>
|
||||
[@utils.FormatStringAsText " * "
|
||||
" * "
|
||||
utils.WithDot(case.description.value[0]?string)
|
||||
72 /]
|
||||
*
|
||||
[#if case.condition.value[0]?trim?length > 0]
|
||||
* <h2>Conditions</h2>
|
||||
* This test is only executed if the following preprocessor condition
|
||||
* evaluates to true:
|
||||
* - ${case.condition.value[0]}
|
||||
* .
|
||||
*
|
||||
[/#if]
|
||||
* <h2>Test Steps</h2>
|
||||
[#list case.steps.step as step]
|
||||
[@utils.FormatStringAsText " * - "
|
||||
" * "
|
||||
utils.WithDot("[" + (sequence_index + 1)?string + "." + (case_index + 1)?string + "." + (step_index + 1)?string + "] " + step.description.value[0]?string)
|
||||
72 /]
|
||||
[/#list]
|
||||
[#if case.steps.step?size > 0]
|
||||
* .
|
||||
[/#if]
|
||||
[#if reqseq?size > 0]
|
||||
* <h2>Covered Requirements</h2>
|
||||
[#assign reqs = "" /]
|
||||
[#list reqseq as r]
|
||||
[#assign reqs = reqs + r /]
|
||||
[#if r_has_next]
|
||||
[#assign reqs = reqs + ", " /]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[@utils.FormatStringAsText " * "
|
||||
" * "
|
||||
utils.WithDot(reqs)
|
||||
72 /]
|
||||
[/#if]
|
||||
*/
|
||||
|
||||
[#if case.various_code.setup_code.value[0]?trim?length > 0]
|
||||
static void ${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")}_setup(void) {
|
||||
[@utils.EmitIndentedCCode " " 2 case.various_code.setup_code.value[0] /]
|
||||
}
|
||||
|
||||
[/#if]
|
||||
[#if case.various_code.teardown_code.value[0]?trim?length > 0]
|
||||
static void ${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")}_teardown(void) {
|
||||
[@utils.EmitIndentedCCode " " 2 case.various_code.teardown_code.value[0] /]
|
||||
}
|
||||
|
||||
[/#if]
|
||||
static void ${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")}_execute(void) {
|
||||
[#if case.various_code.local_variables.value[0]?trim?length > 0]
|
||||
[@utils.EmitIndentedCCode " " 2 case.various_code.local_variables.value[0] /]
|
||||
[/#if]
|
||||
[#list case.steps.step as step]
|
||||
|
||||
[@utils.FormatStringAsText " /* "
|
||||
" "
|
||||
utils.WithDot("[" + (sequence_index + 1)?string + "." + (case_index + 1)?string + "." + (step_index + 1)?string + "] " + step.description.value[0]?string) + "*/"
|
||||
72 /]
|
||||
test_set_step(${(step_index + 1)?string});
|
||||
{
|
||||
[#if step.tags.value[0]?string?trim != ""]
|
||||
[#assign reqseq = step.tags.value[0]?string?trim?word_list?sort /]
|
||||
[#assign reqs = "" /]
|
||||
[#list reqseq as r]
|
||||
[#assign reqs = reqs + r /]
|
||||
[#if r_has_next]
|
||||
[#assign reqs = reqs + ", " /]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[@utils.FormatStringAsText " /* @covers "
|
||||
" "
|
||||
utils.WithDot(reqs) + "*/"
|
||||
72 /]
|
||||
[/#if]
|
||||
[#if step.code.value[0]?trim?length > 0]
|
||||
[@utils.EmitIndentedCCode " " 2 step.code.value[0] /]
|
||||
[/#if]
|
||||
}
|
||||
test_end_step(${(step_index + 1)?string});
|
||||
[/#list]
|
||||
}
|
||||
|
||||
static const testcase_t ${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")} = {
|
||||
"${utils.WithoutDot(case.brief.value[0]?string)}",
|
||||
[#if case.various_code.setup_code.value[0]?trim?length > 0]
|
||||
${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")}_setup,
|
||||
[#else]
|
||||
NULL,
|
||||
[/#if]
|
||||
[#if case.various_code.teardown_code.value[0]?trim?length > 0]
|
||||
${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")}_teardown,
|
||||
[#else]
|
||||
NULL,
|
||||
[/#if]
|
||||
${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")}_execute
|
||||
};
|
||||
[#if case.condition.value[0]?trim?length > 0]
|
||||
#endif /* ${case.condition.value[0]?trim} */
|
||||
[/#if]
|
||||
|
||||
[/#list]
|
||||
/****************************************************************************
|
||||
* Exported data.
|
||||
****************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Array of test cases.
|
||||
*/
|
||||
const testcase_t * const ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")}_array[] = {
|
||||
[#list sequence.cases.case as case]
|
||||
[#if case.condition.value[0]?trim?length > 0]
|
||||
#if (${case.condition.value[0]?trim}) || defined(__DOXYGEN__)
|
||||
[/#if]
|
||||
&${prefix_lower}test_${(sequence_index + 1)?string("000")}_${(case_index + 1)?string("000")},
|
||||
[#if case.condition.value[0]?trim?length > 0]
|
||||
#endif
|
||||
[/#if]
|
||||
[/#list]
|
||||
NULL
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief ${utils.WithDot(sequence.brief.value[0]?string)}
|
||||
*/
|
||||
const testsequence_t ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")} = {
|
||||
"${utils.WithoutDot(sequence.brief.value[0]?string)}",
|
||||
${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")}_array
|
||||
};
|
||||
[#if sequence.condition.value[0]?trim?length > 0]
|
||||
|
||||
#endif /* ${sequence.condition.value[0]} */
|
||||
[/#if]
|
||||
[/#list]
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
[#ftl]
|
||||
[#--
|
||||
ChibiOS/RT - Copyright (C) 2006..2018 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
--]
|
||||
[#import "/@ftllibs/libutils.ftl" as utils /]
|
||||
[@pp.dropOutputFile /]
|
||||
[#list xml.*.application.instances.instance as inst]
|
||||
[#if inst.@id?string == "org.chibios.spc5.components.portable.chibios_unitary_tests_engine"]
|
||||
[#assign instance = inst /]
|
||||
[#break]
|
||||
[/#if]
|
||||
[/#list]
|
||||
[#assign conf = {"instance":instance} /]
|
||||
[#assign prefix_lower = conf.instance.global_data_and_code.code_prefix.value[0]?trim?lower_case /]
|
||||
[#assign prefix_upper =conf. instance.global_data_and_code.code_prefix.value[0]?trim?upper_case /]
|
||||
[#list conf.instance.sequences.sequence as sequence]
|
||||
[@pp.changeOutputFile name=prefix_lower+"test_sequence_" + (sequence_index + 1)?string("000") + ".h" /]
|
||||
[@utils.EmitIndentedCCode "" 2 conf.instance.description.copyright.value[0] /]
|
||||
|
||||
/**
|
||||
* @file ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")}.h
|
||||
* @brief Test Sequence ${(sequence_index + 1)?string("000")} header.
|
||||
*/
|
||||
|
||||
#ifndef ${prefix_upper}TEST_SEQUENCE_${(sequence_index + 1)?string("000")}_H
|
||||
#define ${prefix_upper}TEST_SEQUENCE_${(sequence_index + 1)?string("000")}_H
|
||||
|
||||
extern const testsequence_t ${prefix_lower}test_sequence_${(sequence_index + 1)?string("000")};
|
||||
|
||||
#endif /* ${prefix_upper}TEST_SEQUENCE_${(sequence_index + 1)?string("000")}_H */
|
||||
[/#list]
|
||||
Loading…
Reference in New Issue