From c0f5c2b5ae338aff2f3035bc09fc41c6ee3d6a85 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 4 Mar 2022 12:20:30 +0000 Subject: [PATCH] Shared some code between types 1 and 2. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15469 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/STM32H7xx/hal_lld.h | 35 ++++++++ os/hal/ports/STM32/STM32H7xx/hal_lld_type1.h | 62 +++++--------- os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h | 85 ++++---------------- 3 files changed, 69 insertions(+), 113 deletions(-) diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 148595ca9..38df366d1 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -47,6 +47,41 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options (common) + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + * @note All the clock tree constants are calculated but the initialization + * is not performed. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief MPU region to be used for no-cache RAM area. + */ +#if !defined(STM32_NOCACHE_MPU_REGION) || defined(__DOXYGEN__) +#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 +#endif + +/** + * @brief Add no-cache attribute to SRAM1 and SRAM2. + */ +#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__) +#define STM32_NOCACHE_SRAM1_SRAM2 FALSE +#endif + +/** + * @brief Add no-cache attribute to SRAM3. + */ +#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__) +#define STM32_NOCACHE_SRAM3 TRUE +#endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32H7xx/hal_lld_type1.h index 4dde8a2d4..8dfa934c9 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld_type1.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld_type1.h @@ -76,6 +76,10 @@ #endif /** @} */ +/** + * @name Absolute Maximum Ratings + * @{ + */ #if !defined(STM32_ENFORCE_H7_REV_XY) /** * @brief Absolute maximum system clock. @@ -231,6 +235,7 @@ #define STM32_ADCCLK_MAX 36000000 #endif /* defined(STM32_ENFORCE_H7_REV_XY) */ +/** @} */ /** * @name Internal clock sources frequencies @@ -574,18 +579,9 @@ /*===========================================================================*/ /** - * @name Configuration options + * @name Configuration options (type 1) * @{ */ -/** - * @brief Disables the PWR/RCC initialization in the HAL. - * @note All the clock tree constants are calculated but the initialization - * is not performed. - */ -#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) -#define STM32_NO_INIT FALSE -#endif - /** * @brief Target code for this HAL configuration. * @note Core 1 is the Cortex-M7, core 2 is the Cortex-M4. @@ -594,29 +590,6 @@ #define STM32_TARGET_CORE 1 #endif -/** - * @brief MPU region to be used for no-cache RAM area. - */ -#if !defined(STM32_NOCACHE_MPU_REGION) || defined(__DOXYGEN__) -#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 -#endif - -/** - * @brief Add no-cache attribute to SRAM1 and SRAM2. - * @note MPU region 7 is used if enabled. - */ -#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__) -#define STM32_NOCACHE_SRAM1_SRAM2 FALSE -#endif - -/** - * @brief Add no-cache attribute to SRAM3. - * @note MPU region 7 is used if enabled. - */ -#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__) -#define STM32_NOCACHE_SRAM3 TRUE -#endif - /** * @brief PWR CR1 initializer. */ @@ -2239,25 +2212,33 @@ #error "invalid STM32_D1HPRE value specified" #endif +/* + * AHB frequency check. + */ +#if STM32_HCLK > STM32_HCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_HCLK_MAX)" +#endif + /** - * @brief Core clock. + * @brief Core 1 clock. */ #define STM32_CORE1_CK STM32_SYS_D1CPRE_CK /** - * @brief Core clock. + * @brief Core 2 clock. */ #define STM32_CORE2_CK STM32_HCLK +/** + * @brief Current core clock. + */ #if (STM32_TARGET_CORE == 1) || defined(__DOXYGEN__) - #if STM32_HAS_M7 != TRUE #error "Cortex-M7 not present in this device" #endif #define STM32_CORE_CK STM32_CORE1_CK #elif STM32_TARGET_CORE == 2 - #if STM32_HAS_M4 != TRUE #error "Cortex-M4 not present in this device" #endif @@ -2267,13 +2248,6 @@ #error "invalid STM32_TARGET_CORE value specified" #endif -/* - * AHB frequency check. - */ -#if STM32_HCLK > STM32_HCLK_MAX -#error "STM32_HCLK exceeding maximum frequency (STM32_HCLK_MAX)" -#endif - /** * @brief D1 PCLK3 clock. */ diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h index 2c791f110..bace6fcb0 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld_type2.h @@ -523,49 +523,9 @@ /*===========================================================================*/ /** - * @name Configuration options + * @name Configuration options (type 2) * @{ */ -/** - * @brief Disables the PWR/RCC initialization in the HAL. - * @note All the clock tree constants are calculated but the initialization - * is not performed. - */ -#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) -#define STM32_NO_INIT FALSE -#endif - -/** - * @brief Target code for this HAL configuration. - * @note Core 1 is the Cortex-M7, core 2 is the Cortex-M4. - */ -#if !defined(STM32_TARGET_CORE) || defined(__DOXYGEN__) -#define STM32_TARGET_CORE 1 -#endif - -/** - * @brief MPU region to be used for no-cache RAM area. - */ -#if !defined(STM32_NOCACHE_MPU_REGION) || defined(__DOXYGEN__) -#define STM32_NOCACHE_MPU_REGION MPU_REGION_6 -#endif - -/** - * @brief Add no-cache attribute to SRAM1 and SRAM2. - * @note MPU region 7 is used if enabled. - */ -#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__) -#define STM32_NOCACHE_SRAM1_SRAM2 FALSE -#endif - -/** - * @brief Add no-cache attribute to SRAM3. - * @note MPU region 7 is used if enabled. - */ -#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__) -#define STM32_NOCACHE_SRAM3 TRUE -#endif - /** * @brief PWR CR1 initializer. */ @@ -2168,34 +2128,6 @@ #error "invalid STM32_D1HPRE value specified" #endif -/** - * @brief Core clock. - */ -#define STM32_CORE1_CK STM32_SYS_D1CPRE_CK - -/** - * @brief Core clock. - */ -#define STM32_CORE2_CK STM32_HCLK - -#if (STM32_TARGET_CORE == 1) || defined(__DOXYGEN__) - -#if STM32_HAS_M7 != TRUE -#error "Cortex-M7 not present in this device" -#endif -#define STM32_CORE_CK STM32_CORE1_CK - -#elif STM32_TARGET_CORE == 2 - -#if STM32_HAS_M4 != TRUE -#error "Cortex-M4 not present in this device" -#endif -#define STM32_CORE_CK STM32_CORE2_CK - -#else -#error "invalid STM32_TARGET_CORE value specified" -#endif - /* * AHB frequency check. */ @@ -2203,6 +2135,21 @@ #error "STM32_HCLK exceeding maximum frequency (STM32_HCLK_MAX)" #endif +/** + * @brief Core 1 clock. + */ +#define STM32_CORE1_CK STM32_SYS_D1CPRE_CK + +/** + * @brief Core 2 clock. + */ +#define STM32_CORE2_CK 0U + +/** + * @brief Current core clock. + */ +#define STM32_CORE_CK STM32_CORE1_CK + /** * @brief D1 PCLK3 clock. */