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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5764 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2013-05-27 08:51:18 +00:00
parent 386a2bf390
commit c16062e326
3 changed files with 13 additions and 8 deletions
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11
os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
View File

@ -425,7 +425,7 @@ static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
(void)channel; (void)channel;
/* Stops the DSPI and clears the queues.*/ /* Stops the DSPI and clears the queues.*/
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT |
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF; SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
/* Portable SPI ISR code defined in the high level driver, note, it is /* Portable SPI ISR code defined in the high level driver, note, it is
@ -442,7 +442,7 @@ static void spi_serve_dma_error_irq(edma_channel_t channel,
(void)esr; (void)esr;
/* Stops the DSPI and clears the queues.*/ /* Stops the DSPI and clears the queues.*/
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT |
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF; SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
edmaChannelStop(spip->tx1_channel); edmaChannelStop(spip->tx1_channel);
@ -558,7 +558,7 @@ void spi_lld_start(SPIDriver *spip) {
} }
/* Configures the peripheral.*/ /* Configures the peripheral.*/
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | spip->config->mcr; spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_HALT;
spip->dspi->CTAR[0].R = spip->config->ctar0; spip->dspi->CTAR[0].R = spip->config->ctar0;
spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS | spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS; SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
@ -584,7 +584,7 @@ void spi_lld_stop(SPIDriver *spip) {
spip->dspi->CTAR[0].R = 0; spip->dspi->CTAR[0].R = 0;
spip->dspi->RSER.R = 0; spip->dspi->RSER.R = 0;
spip->dspi->SR.R = spip->dspi->SR.R; spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_MDIS | spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS | SPC5_MCR_MDIS |
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF | SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF |
SPC5_MCR_HALT; SPC5_MCR_HALT;
@ -679,7 +679,8 @@ void spi_lld_exchange(SPIDriver *spip, size_t n,
/* Starting transfer.*/ /* Starting transfer.*/
spip->dspi->SR.R = spip->dspi->SR.R; spip->dspi->SR.R = spip->dspi->SR.R;
spip->dspi->MCR.B.HALT = 0; spip->dspi->MCR.R = DSPI_MCR_ENFORCED_BITS |
(spip->config->mcr & ~DSPI_MCR_EXCLUDED_BITS);
/* DMAs require a different setup depending on the frame size.*/ /* DMAs require a different setup depending on the frame size.*/
if (spip->dspi->CTAR[0].B.FMSZ < 8) { if (spip->dspi->CTAR[0].B.FMSZ < 8) {

6
os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h
View File

@ -101,8 +101,12 @@
/** /**
* @brief Alternate "n" output pad. * @brief Alternate "n" output pad.
* @note Both the IBE and OBE bits are specified in this mask, the OBE
* bit is not required for some PCRs but in that case it is
* ignored.
*/ */
#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_PA(n)) #define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \
PAL_SPC5_PA(n))
/** @} */ /** @} */
/*===========================================================================*/ /*===========================================================================*/

4
testhal/SPC563Mxx/SPI/main.c
View File

@ -24,8 +24,8 @@ static const SPIConfig hs_spicfg = {
NULL, NULL,
0, 0,
0, 0,
0, /* MCR. */ SPC5_MCR_PCSIS0, /* MCR. */
SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ SPC5_CTAR_FMSZ(8) | SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV128, /* CTAR0. */
SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */
}; };