From c168de907f2a1a79d6ceaafcf0db36acd74f8659 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 22 Jun 2010 19:26:25 +0000 Subject: [PATCH] Fixed bugs 3019594 and 3019738. Added timer clock sources to the STM32 clock trees. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.0.x@2035 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/hal_lld_f103.h | 18 ++++++++++++++++ os/hal/platforms/STM32/hal_lld_f105_f107.h | 22 ++++++++++++++++++-- os/ports/GCC/ARMCMx/chcore_v7m.c | 24 ++++++++++------------ os/ports/GCC/ARMCMx/chcore_v7m.h | 8 +++++--- readme.txt | 7 +++++++ 5 files changed, 61 insertions(+), 18 deletions(-) diff --git a/os/hal/platforms/STM32/hal_lld_f103.h b/os/hal/platforms/STM32/hal_lld_f103.h index 224ff6329..17d797a84 100644 --- a/os/hal/platforms/STM32/hal_lld_f103.h +++ b/os/hal/platforms/STM32/hal_lld_f103.h @@ -331,6 +331,24 @@ #error "STM32_ADCCLK exceeding maximum frequency (14MHz)" #endif +/** + * @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timers 1, 8, 9, 10 and 11 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + /** * @brief Flash settings. */ diff --git a/os/hal/platforms/STM32/hal_lld_f105_f107.h b/os/hal/platforms/STM32/hal_lld_f105_f107.h index 9330d579b..ddd664e7e 100644 --- a/os/hal/platforms/STM32/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32/hal_lld_f105_f107.h @@ -167,7 +167,7 @@ #endif /** - * @brief PLL2 multiplier value. + * @brief PLL2 multiplier value. * @note The default value is calculated for a 72MHz system clock from * a 25MHz crystal using both PLL and PLL2. */ @@ -264,7 +264,7 @@ for the PLL clock */ #if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__) /** - * @brief PLL2 input frequency. + * @brief PLL2 input frequency. */ #define STM32_PLL2CLKIN (STM32_HSECLK / STM32_PREDIV2_VALUE) @@ -433,6 +433,24 @@ #error "STM32_ADCCLK exceeding maximum frequency (14MHz)" #endif +/** + * @brief Timers 2, 3, 4, 5, 6, 7 clock. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Timer 1 clock. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + /** * @brief Flash settings. */ diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index 980948df3..dbce1c320 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -35,19 +35,17 @@ #include "ch.h" /** - * @brief Internal context stacking. + * @brief Internal context stacking. */ -#define PUSH_CONTEXT(sp) { \ +#define PUSH_CONTEXT() { \ asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \ } - /** * @brief Internal context unstacking. */ -#define POP_CONTEXT(sp) { \ - asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \ - : : "r" (sp)); \ +#define POP_CONTEXT() { \ + asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}"); \ } #if !CH_OPTIMIZE_SPEED @@ -95,7 +93,7 @@ void SVCallVector(void) { } /** - * @brief Reschedule verification and setup after an IRQ. + * @brief Reschedule verification and setup after an IRQ. */ void _port_irq_epilogue(void) { @@ -145,21 +143,21 @@ void _port_switch_from_isr(void) { __attribute__((naked)) #endif void port_switch(Thread *ntp, Thread *otp) { - register struct intctx *r13 asm ("r13"); - /* Stack overflow check, if enabled.*/ #if CH_DBG_ENABLE_STACK_CHECK + /* Stack overflow check, if enabled.*/ + register struct intctx *r13 asm ("r13"); if ((void *)(r13 - 1) < (void *)(otp + 1)) asm volatile ("movs r0, #0 \n\t" "b chDbgPanic"); #endif /* CH_DBG_ENABLE_STACK_CHECK */ - PUSH_CONTEXT(r13); + PUSH_CONTEXT(); - otp->p_ctx.r13 = r13; - r13 = ntp->p_ctx.r13; + asm volatile ("str sp, [%1, #12] \n\t" + "ldr sp, [%0, #12]" : : "r" (ntp), "r" (otp)); - POP_CONTEXT(r13); + POP_CONTEXT(); } /** diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index dfba14336..cb3dea05e 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -99,7 +99,8 @@ struct intctx { * the idle thread should take no more space than those reserved * by @p INT_REQUIRED_STACK. * @note In this port it is set to 4 because the idle thread does have - * a stack frame when compiling without optimizations. + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. */ #ifndef IDLE_THREAD_STACK_SIZE #define IDLE_THREAD_STACK_SIZE 4 @@ -112,10 +113,11 @@ struct intctx { * This value can be zero on those architecture where there is a * separate interrupt stack and the stack space between @p intctx and * @p extctx is known to be zero. - * @note This port requires no extra stack space for interrupt handling. + * @note In this port it is set to 8 because the function + * @p chSchDoRescheduleI() has a stack frame. */ #ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 0 +#define INT_REQUIRED_STACK 8 #endif /** diff --git a/readme.txt b/readme.txt index 27c906888..db1cee52e 100644 --- a/readme.txt +++ b/readme.txt @@ -59,9 +59,16 @@ ***************************************************************************** *** 2.0.1 *** +- FIX: Fixed non functional CH_DBG_ENABLE_STACK_CHECK option in the Cortex-M3 + caused by GCC 4.5.0, the fix also improves the context switch performance + because GCC 4.5.0 apparently was generating useless instructions within the + very critical context switch code (bug 3019738). +- FIX: Fixed insufficient stack space assigned to the idle thread in + Cortex-M3 port (bug 3019594). - FIX: Fixed missing check in chIQReadTimeout() and chIQWriteTimeout() (bug 3019158). - FIX: Fixed instability in Mutexes subsystem (bug 3019099). +- NEW: Added timers clock macros to the STM32 clock tree HAL driver. *** 2.0.0 *** - NEW: Implemented the concept of thread references, this mechanism ensures