diff --git a/docs/reports/STM32F407-168-GCC-FPU.txt b/docs/reports/STM32F407-168-GCC-FPU.txt new file mode 100644 index 000000000..47dc76c84 --- /dev/null +++ b/docs/reports/STM32F407-168-GCC-FPU.txt @@ -0,0 +1,164 @@ +*************************************************************************** +Options: -O2 -fomit-frame-pointer -falign-functions=16 +Settings: SYSCLK=168, ACR=0x705 (5 wait states) +*************************************************************************** + +*** ChibiOS/RT test suite +*** +*** Kernel: 2.3.5unstable +*** Compiled: Dec 11 2011 - 17:14:07 +*** Compiler: GCC 4.6.2 +*** Architecture: ARMv7-ME +*** Core Variant: Cortex-M4F +*** Port Info: Advanced kernel mode +*** Platform: STM32F4 High Performance & DSP +*** Test Board: ST STM32F4-Discovery + +---------------------------------------------------------------------------- +--- Test Case 1.1 (Threads, enqueuing test #1) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.2 (Threads, enqueuing test #2) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.3 (Threads, priority change) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 1.4 (Threads, delays) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.1 (Semaphores, enqueuing) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.2 (Semaphores, timeout) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.3 (Semaphores, atomic signal-wait) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 2.4 (Binary Semaphores, functionality) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.1 (Mutexes, priority enqueuing test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.2 (Mutexes, priority inheritance, simple case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.3 (Mutexes, priority inheritance, complex case) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.4 (Mutexes, priority return) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.5 (Mutexes, status) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.6 (CondVar, signal test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.7 (CondVar, broadcast test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 3.8 (CondVar, boost test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 4.1 (Messages, loop) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 5.1 (Mailboxes, queuing and timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.1 (Events, registration and dispatch) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.2 (Events, wait and broadcast) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 6.3 (Events, timeouts) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 7.1 (Heap, allocation and fragmentation test) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 8.1 (Memory Pools, queue/dequeue) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.1 (Dynamic APIs, threads creation from heap) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 9.3 (Dynamic APIs, registry and references) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.1 (Queues, input queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 10.2 (Queues, output queues) +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.1 (Benchmark, messages #1) +--- Score : 559399 msgs/S, 1118798 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.2 (Benchmark, messages #2) +--- Score : 476758 msgs/S, 953516 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.3 (Benchmark, messages #3) +--- Score : 476757 msgs/S, 953514 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.4 (Benchmark, context switch) +--- Score : 1639312 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.5 (Benchmark, threads, full cycle) +--- Score : 371289 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.6 (Benchmark, threads, create only) +--- Score : 496514 threads/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads) +--- Score : 151014 reschedules/S, 906084 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.8 (Benchmark, round robin context switching) +--- Score : 1018620 ctxswc/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.9 (Benchmark, I/O Queues throughput) +--- Score : 1766592 bytes/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.10 (Benchmark, virtual timers set/reset) +--- Score : 1997950 timers/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.11 (Benchmark, semaphores wait/signal) +--- Score : 2601996 wait+signal/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.12 (Benchmark, mutexes lock/unlock) +--- Score : 1766592 lock+unlock/S +--- Result: SUCCESS +---------------------------------------------------------------------------- +--- Test Case 11.13 (Benchmark, RAM footprint) +--- System: 648 bytes +--- Thread: 72 bytes +--- Timer : 20 bytes +--- Semaph: 12 bytes +--- EventS: 4 bytes +--- EventL: 12 bytes +--- Mutex : 16 bytes +--- CondV.: 8 bytes +--- Queue : 32 bytes +--- MailB.: 40 bytes +--- Result: SUCCESS +---------------------------------------------------------------------------- + +Final result: SUCCESS diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index aedaeea10..936823755 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -33,10 +33,10 @@ */ #if CORTEX_USE_FPU || defined(__DOXYGEN__) #define PUSH_CONTEXT() { \ - asm volatile ("vpush {s16-s31}" \ - : : : "memory"); \ asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" \ : : : "memory"); \ + asm volatile ("vpush {s16-s31}" \ + : : : "memory"); \ } #else /* !CORTEX_USE_FPU */ #define PUSH_CONTEXT() { \ @@ -50,10 +50,10 @@ */ #if CORTEX_USE_FPU || defined(__DOXYGEN__) #define POP_CONTEXT() { \ - asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \ - : : : "memory"); \ asm volatile ("vpop {s16-s31}" \ : : : "memory"); \ + asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \ + : : : "memory"); \ } #else /* !CORTEX_USE_FPU */ #define POP_CONTEXT() { \ @@ -99,21 +99,20 @@ CH_IRQ_HANDLER(SysTickVector) { */ void SVCallVector(void) { uint32_t *psp; - register struct extctx *ctxp; /* Current PSP value.*/ asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory"); + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + psp = (uint32_t *)((struct extctx *)psp + 1); + #if CORTEX_USE_FPU /* Restoring the special registers SCB_FPCCR and FPCAR.*/ SCB_FPCAR = *psp++; SCB_FPCCR = *psp++; #endif - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp = (struct extctx *)psp + 1; - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + asm volatile ("msr PSP, %0" : : "r" (psp) : "memory"); port_unlock_from_isr(); } #endif /* !CORTEX_SIMPLIFIED_PRIORITY */ @@ -127,21 +126,20 @@ void SVCallVector(void) { */ void PendSVVector(void) { uint32_t *psp; - register struct extctx *ctxp; /* Current PSP value.*/ asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory"); + /* Discarding the current exception context and positioning the stack to + point to the real one.*/ + psp = (uint32_t *)((struct extctx *)psp + 1); + #if CORTEX_USE_FPU /* Restoring the special registers SCB_FPCCR and FPCAR.*/ SCB_FPCAR = *psp++; SCB_FPCCR = *psp++; #endif - - /* Discarding the current exception context and positioning the stack to - point to the real one.*/ - ctxp = (struct extctx *)psp + 1; - asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); + asm volatile ("msr PSP, %0" : : "r" (psp) : "memory"); } #endif /* CORTEX_SIMPLIFIED_PRIORITY */ @@ -170,7 +168,7 @@ void _port_init(void) { SCB_FPDSCR = reg; /* Initializing the FPU context save in lazy mode.*/ - SCB_FPCCR = FPCCR_LSPEN; + SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN; #endif /* Initialization of the system vectors used by the port.*/ @@ -210,7 +208,7 @@ void _port_irq_epilogue(void) { /* Adding an artificial exception return context, there is no need to populate it fully.*/ - ctxp = (struct extctx *)psp - 1; + ctxp = ((struct extctx *)psp) - 1; asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory"); ctxp->pc = _port_switch_from_isr; ctxp->xpsr = (regarm_t)0x01000000; diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index 3cd2b9e18..8dd42f909 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -47,7 +47,7 @@ * @details Activating this option will make the Kernel work in compact mode. */ #if !defined(CORTEX_USE_FPU) -#define CORTEX_USE_FPU FALSE/*CORTEX_HAS_FPU*/ +#define CORTEX_USE_FPU CORTEX_HAS_FPU #elif CORTEX_USE_FPU && !CORTEX_HAS_FPU /* This setting requires an FPU presence check in case it is externally redefined.*/ @@ -183,22 +183,12 @@ struct extctx { regarm_t s13; regarm_t s14; regarm_t s15; - regarm_t s16; regarm_t fpscr; regarm_t reserved; #endif /* CORTEX_USE_FPU */ }; struct intctx { - regarm_t r4; - regarm_t r5; - regarm_t r6; - regarm_t r7; - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr; #if CORTEX_USE_FPU || defined(__DOXYGEN__) regarm_t s16; regarm_t s17; @@ -217,6 +207,15 @@ struct intctx { regarm_t s30; regarm_t s31; #endif /* CORTEX_USE_FPU */ + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr; }; #endif diff --git a/readme.txt b/readme.txt index d53e7fb73..1cb86d244 100644 --- a/readme.txt +++ b/readme.txt @@ -80,6 +80,7 @@ structures and stacks in the CCM RAM instead normal RAM. It is done using a special .ld file that can be customized to decide how to allocate data in the various RAM sections. +- NEW: Added support for the Cortex-M4 FPU (default when the FPU is present). - NEW: Improved I2C driver model and STM32 implementation by Barthess. *** 2.3.4 ***