Modified USARTv2 to support HW FIFOs where present.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12288 110e8d01-0319-4d1e-a829-52ad28d1bb01

os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c

@@ -338,25 +338,41 @@ static void serve_interrupt(SerialDriver *sdp) {
     osalSysUnlockFromISR();
   }
 
-  /* Data available.*/
-  if (isr & USART_ISR_RXNE) {
+  /* Data available, note it is a while in order to handle two situations:
+     1) Another byte arrived after removing the previous one, this would cause
+        an extra interrupt to serve.
+     2) FIFO mode is enabled on devices that support it, we need to empty
+        the FIFO.*/
+  while (isr & USART_ISR_RXNE) {
     osalSysLockFromISR();
     sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask);
     osalSysUnlockFromISR();
+
+    isr = u->ISR;
   }
 
-  /* Transmission buffer empty.*/
-  if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
-    msg_t b;
-    osalSysLockFromISR();
-    b = oqGetI(&sdp->oqueue);
-    if (b < MSG_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      u->CR1 = cr1 & ~USART_CR1_TXEIE;
-    }
-    else
+  /* Transmission buffer empty, note it is a while in order to handle two
+     situations:
+     1) The data registers has been emptied immediately after writing it, this
+        would cause an extra interrupt to serve.
+     2) FIFO mode is enabled on devices that support it, we need to fill
+        the FIFO.*/
+  if (cr1 & USART_CR1_TXEIE) {
+    while (isr & USART_ISR_TXE) {
+      msg_t b;
+
+      osalSysLockFromISR();
+      b = oqGetI(&sdp->oqueue);
+      if (b < MSG_OK) {
+        chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+        u->CR1 = cr1 & ~USART_CR1_TXEIE;
+        break;
+      }
       u->TDR = b;
-    osalSysUnlockFromISR();
+      osalSysUnlockFromISR();
+
+      isr = u->ISR;
+    }
   }
 
   /* Physical transmission end.*/

os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h

@@ -428,7 +428,7 @@
 
 #endif /* !defined(STM32_USART3_8_HANDLER) */
 
-#if STM32_SERIAL_USE_LPUART1 &&                                               \
+#if STM32_SERIAL_USE_LPUART1 &&                                             \
     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_LPUART1_PRIORITY)
 #error "Invalid IRQ priority assigned to LPUART1"
 #endif

readme.txt

@@ -94,6 +94,7 @@
 - NEW: Added mcuconf.h generators for STM32L476xx, STM32L496xx and STM32L4R5xx
        devices.
 - NEW: Added demo for STM32L496ZG-Nucleo144 and STM32L4R5ZI-Nucleo144 boards.
+- NEW: Modified USARTv2 to support HW FIFOs where present.
 - NEW: STM32 DMAv1, ADCv3, DACv1, I2Cv2, SPIv2 and USARTv2 are now
        DMAMUX-aware.
 - NEW: Introduced support for STM32L4+ devices.