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Modified USARTv2 to support HW FIFOs where present. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12288 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-09-23 14:34:26 +00:00
parent d749f21cb9
commit c27b36536a
3 changed files with 31 additions and 14 deletions
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42
os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
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@ -338,25 +338,41 @@ static void serve_interrupt(SerialDriver *sdp) {
osalSysUnlockFromISR(); osalSysUnlockFromISR();
} }
/* Data available.*/ /* Data available, note it is a while in order to handle two situations:
if (isr & USART_ISR_RXNE) { 1) Another byte arrived after removing the previous one, this would cause
an extra interrupt to serve.
2) FIFO mode is enabled on devices that support it, we need to empty
the FIFO.*/
while (isr & USART_ISR_RXNE) {
osalSysLockFromISR(); osalSysLockFromISR();
sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask); sdIncomingDataI(sdp, (uint8_t)u->RDR & sdp->rxmask);
osalSysUnlockFromISR(); osalSysUnlockFromISR();
isr = u->ISR;
} }
/* Transmission buffer empty.*/ /* Transmission buffer empty, note it is a while in order to handle two
if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) { situations:
msg_t b; 1) The data registers has been emptied immediately after writing it, this
osalSysLockFromISR(); would cause an extra interrupt to serve.
b = oqGetI(&sdp->oqueue); 2) FIFO mode is enabled on devices that support it, we need to fill
if (b < MSG_OK) { the FIFO.*/
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); if (cr1 & USART_CR1_TXEIE) {
u->CR1 = cr1 & ~USART_CR1_TXEIE; while (isr & USART_ISR_TXE) {
} msg_t b;
else
osalSysLockFromISR();
b = oqGetI(&sdp->oqueue);
if (b < MSG_OK) {
chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
u->CR1 = cr1 & ~USART_CR1_TXEIE;
break;
}
u->TDR = b; u->TDR = b;
osalSysUnlockFromISR(); osalSysUnlockFromISR();
isr = u->ISR;
}
} }
/* Physical transmission end.*/ /* Physical transmission end.*/

2
os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.h
View File

@ -428,7 +428,7 @@
#endif /* !defined(STM32_USART3_8_HANDLER) */ #endif /* !defined(STM32_USART3_8_HANDLER) */
#if STM32_SERIAL_USE_LPUART1 && \ #if STM32_SERIAL_USE_LPUART1 && \
!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_LPUART1_PRIORITY) !OSAL_IRQ_IS_VALID_PRIORITY(STM32_SERIAL_LPUART1_PRIORITY)
#error "Invalid IRQ priority assigned to LPUART1" #error "Invalid IRQ priority assigned to LPUART1"
#endif #endif

1
readme.txt
View File

@ -94,6 +94,7 @@
- NEW: Added mcuconf.h generators for STM32L476xx, STM32L496xx and STM32L4R5xx - NEW: Added mcuconf.h generators for STM32L476xx, STM32L496xx and STM32L4R5xx
devices. devices.
- NEW: Added demo for STM32L496ZG-Nucleo144 and STM32L4R5ZI-Nucleo144 boards. - NEW: Added demo for STM32L496ZG-Nucleo144 and STM32L4R5ZI-Nucleo144 boards.
- NEW: Modified USARTv2 to support HW FIFOs where present.
- NEW: STM32 DMAv1, ADCv3, DACv1, I2Cv2, SPIv2 and USARTv2 are now - NEW: STM32 DMAv1, ADCv3, DACv1, I2Cv2, SPIv2 and USARTv2 are now
DMAMUX-aware. DMAMUX-aware.
- NEW: Introduced support for STM32L4+ devices. - NEW: Introduced support for STM32L4+ devices.