diff --git a/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h index 295ac1ae6..8cb7ff3ef 100644 --- a/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H723ZG-NUCLEO144/cfg/mcuconf.h @@ -55,10 +55,10 @@ * very critical. * Register constants are taken from the ST header. */ -#define STM32_VOS STM32_VOS_SCALE1 +#define STM32_VOS STM32_VOS_SCALE0 #define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0) #define STM32_PWR_CR2 (PWR_CR2_BREN) -#define STM32_PWR_CR3 (PWR_CR3_SMPSEN | PWR_CR3_USB33DEN) +#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN) #define STM32_PWR_CPUCR 0 /* @@ -84,11 +84,11 @@ #define STM32_PLL1_Q_ENABLED TRUE #define STM32_PLL1_R_ENABLED TRUE #define STM32_PLL1_DIVM_VALUE 4 -#define STM32_PLL1_DIVN_VALUE 480 +#define STM32_PLL1_DIVN_VALUE 260 #define STM32_PLL1_FRACN_VALUE 0 -#define STM32_PLL1_DIVP_VALUE 2 -#define STM32_PLL1_DIVQ_VALUE 20 -#define STM32_PLL1_DIVR_VALUE 8 +#define STM32_PLL1_DIVP_VALUE 1 +#define STM32_PLL1_DIVQ_VALUE 10 +#define STM32_PLL1_DIVR_VALUE 4 #define STM32_PLL2_ENABLED TRUE #define STM32_PLL2_P_ENABLED TRUE #define STM32_PLL2_Q_ENABLED TRUE @@ -139,7 +139,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_OCTOSPISEL STM32_OCTOSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK /* TODO ERROR XXXXXXXXXXXXXXXXXXX */ +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h index 46d75768c..43148ed1a 100644 --- a/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h index bc2b1c7f8..639550ff3 100644 --- a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h index 54bafcb39..770824586 100644 --- a/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/demos/STM32/RT-STM32H755ZI_M4-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H755ZI_M4-NUCLEO144/cfg/mcuconf.h index 295134df7..304a45d0d 100644 --- a/demos/STM32/RT-STM32H755ZI_M4-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H755ZI_M4-NUCLEO144/cfg/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H723xG_ITCM64k.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H723xG_ITCM64k.ld index d39479b4c..2576781f2 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H723xG_ITCM64k.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32H723xG_ITCM64k.ld @@ -48,27 +48,27 @@ MEMORY and a load region (_LMA suffix).*/ /* Flash region to be used for exception vectors.*/ -REGION_ALIAS("VECTORS_FLASH", flash1); -REGION_ALIAS("VECTORS_FLASH_LMA", flash1); +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); /* Flash region to be used for constructors and destructors.*/ -REGION_ALIAS("XTORS_FLASH", flash1); -REGION_ALIAS("XTORS_FLASH_LMA", flash1); +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); /* Flash region to be used for code text.*/ -REGION_ALIAS("TEXT_FLASH", flash1); -REGION_ALIAS("TEXT_FLASH_LMA", flash1); +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); /* Flash region to be used for read only data.*/ -REGION_ALIAS("RODATA_FLASH", flash1); -REGION_ALIAS("RODATA_FLASH_LMA", flash1); +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); /* Flash region to be used for various.*/ -REGION_ALIAS("VARIOUS_FLASH", flash1); -REGION_ALIAS("VARIOUS_FLASH_LMA", flash1); +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); /* Flash region to be used for RAM(n) initialization data.*/ -REGION_ALIAS("RAM_INIT_FLASH_LMA", flash1); +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); /* RAM region to be used for Main stack. This stack accommodates the processing of all exceptions and interrupts.*/ @@ -80,7 +80,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram5); /* RAM region to be used for data segment.*/ REGION_ALIAS("DATA_RAM", ram0); -REGION_ALIAS("DATA_RAM_LMA", flash1); +REGION_ALIAS("DATA_RAM_LMA", flash0); /* RAM region to be used for BSS segment.*/ REGION_ALIAS("BSS_RAM", ram0); diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c index 2f4d1b92f..cd0f357ce 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c @@ -108,8 +108,10 @@ static inline void init_pwr(void) { PWR->CR3 = STM32_PWR_CR3; /* Other bits, lower byte is not changed. */ PWR->CPUCR = STM32_PWR_CPUCR; PWR->D3CR = STM32_VOS; +#if defined(HAL_LLD_TYPE1_H) #if !defined(STM32_ENFORCE_H7_REV_XY) SYSCFG->PWRCR = STM32_ODEN; +#endif #endif while ((PWR->D3CR & PWR_D3CR_VOSRDY) == 0) ; /* CHTODO timeout handling.*/ @@ -387,17 +389,31 @@ void stm32_clock_init(void) { RCC->D3CFGR = STM32_D3PPRE4; /* Peripherals clocks.*/ - RCC->D1CCIPR = STM32_CKPERSEL | STM32_SDMMCSEL | STM32_QSPISEL | +#if defined(HAL_LLD_TYPE1_H) + RCC->D1CCIPR = STM32_CKPERSEL | STM32_SDMMCSEL | STM32_QSPISEL | STM32_FMCSEL; - RCC->D2CCIP1R = STM32_SWPSEL | STM32_FDCANSEL | STM32_DFSDM1SEL | - STM32_SPDIFSEL | STM32_SPDIFSEL | STM32_SPI45SEL | - STM32_SPI123SEL | STM32_SAI23SEL | STM32_SAI1SEL; - RCC->D2CCIP2R = STM32_LPTIM1SEL | STM32_CECSEL | STM32_USBSEL | - STM32_I2C123SEL | STM32_RNGSEL | STM32_USART16SEL | + RCC->D2CCIP1R = STM32_SWPSEL | STM32_FDCANSEL | STM32_DFSDM1SEL | + STM32_SPDIFSEL | STM32_SPDIFSEL | STM32_SPI45SEL | + STM32_SPI123SEL | STM32_SAI23SEL | STM32_SAI1SEL; + RCC->D2CCIP2R = STM32_LPTIM1SEL | STM32_CECSEL | STM32_USBSEL | + STM32_I2C123SEL | STM32_RNGSEL | STM32_USART16SEL | STM32_USART234578SEL; - RCC->D3CCIPR = STM32_SPI6SEL | STM32_SAI4BSEL | STM32_SAI4ASEL | - STM32_ADCSEL | STM32_LPTIM345SEL | STM32_LPTIM2SEL | - STM32_I2C4SEL | STM32_LPUART1SEL; + RCC->D3CCIPR = STM32_SPI6SEL | STM32_SAI4BSEL | STM32_SAI4ASEL | + STM32_ADCSEL | STM32_LPTIM345SEL | STM32_LPTIM2SEL | + STM32_I2C4SEL | STM32_LPUART1SEL; +#elif defined(HAL_LLD_TYPE2_H) + RCC->D1CCIPR = STM32_CKPERSEL | STM32_SDMMCSEL | STM32_OCTOSPISEL | + STM32_FMCSEL; + RCC->D2CCIP1R = STM32_SWPSEL | STM32_FDCANSEL | STM32_DFSDM1SEL | + STM32_SPDIFSEL | STM32_SPDIFSEL | STM32_SPI45SEL | + STM32_SPI123SEL | STM32_SAI23SEL | STM32_SAI1SEL; + RCC->D2CCIP2R = STM32_LPTIM1SEL | STM32_CECSEL | STM32_USBSEL | + STM32_I2C1235SEL | STM32_RNGSEL | STM32_USART16910SEL | + STM32_USART234578SEL; + RCC->D3CCIPR = STM32_SPI6SEL | STM32_SAI4BSEL | STM32_SAI4ASEL | + STM32_ADCSEL | STM32_LPTIM345SEL | STM32_LPTIM2SEL | + STM32_I2C4SEL | STM32_LPUART1SEL; +#endif /* Flash setup.*/ FLASH->ACR = FLASH_ACR_WRHIGHFREQ_1 | FLASH_ACR_WRHIGHFREQ_0 | @@ -427,7 +443,9 @@ void stm32_clock_init(void) { /* RAM1 2 and 3 clocks enabled.*/ rccEnableSRAM1(true); rccEnableSRAM2(true); +#if !defined(HAL_LLD_TYPE2_H) rccEnableSRAM3(true); +#endif #endif /* STM32_NO_INIT */ } diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_isr.c b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c index 8ed4d72fc..162f7ccff 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c @@ -67,7 +67,11 @@ #include "stm32_fdcan1.inc" #include "stm32_fdcan2.inc" +#if defined(HAL_LLD_TYPE1_H) #include "stm32_quadspi1.inc" +#elif defined(HAL_LLD_TYPE2_H) +//#include "stm32_octospi1.inc" +#endif #include "stm32_sdmmc1.inc" #include "stm32_sdmmc2.inc" @@ -120,7 +124,11 @@ void irqInit(void) { mdma_irq_init(); +#if defined(HAL_LLD_TYPE1_H) quadspi1_irq_init(); +#elif defined(HAL_LLD_TYPE2_H) +// octospi1_irq_init(); +#endif sdmmc1_irq_init(); sdmmc2_irq_init(); @@ -170,7 +178,11 @@ void irqDeinit(void) { mdma_irq_deinit(); +#if defined(HAL_LLD_TYPE1_H) quadspi1_irq_deinit(); +#elif defined(HAL_LLD_TYPE2_H) +// octospi1_irq_deinit(); +#endif sdmmc1_irq_deinit(); sdmmc2_irq_deinit(); diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h index fda74ab33..53adf966f 100644 --- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h @@ -190,6 +190,9 @@ #define STM32_HAS_I2C3 TRUE #define STM32_HAS_I2C4 TRUE +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 FALSE + /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 TRUE #define STM32_HAS_QUADSPI2 FALSE @@ -420,6 +423,9 @@ #define STM32_HAS_I2C3 TRUE #define STM32_HAS_I2C4 TRUE +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 TRUE + /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 FALSE #define STM32_HAS_QUADSPI2 FALSE @@ -640,6 +646,9 @@ #define STM32_HAS_I2C3 TRUE #define STM32_HAS_I2C4 TRUE +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 FALSE + /* QUADSPI attributes.*/ #define STM32_HAS_QUADSPI1 TRUE #define STM32_HAS_QUADSPI2 FALSE diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h index 91ed76df9..cba22e4d6 100644 --- a/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h index 767d017ff..0a633eca2 100644 --- a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h index 6872bf196..33bb5086b 100644 --- a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h index a33678de2..5dd91f070 100644 --- a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2 diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h index 678aeabfd..d558e8327 100644 --- a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h +++ b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h @@ -144,7 +144,7 @@ #define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK #define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK #define STM32_QSPISEL STM32_QSPISEL_HCLK -#define STM32_FMCSEL STM32_QSPISEL_HCLK +#define STM32_FMCSEL STM32_FMCSEL_HCLK #define STM32_SWPSEL STM32_SWPSEL_PCLK1 #define STM32_FDCANSEL STM32_FDCANSEL_HSE_CK #define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2