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Artery AT32F4xx port: USB clock settings

This commit is contained in:
Andrey Gusakov 2023-05-31 10:41:16 +03:00 committed by rusefillc
parent d24b9f19e7
commit c39a274485
4 changed files with 70 additions and 17 deletions
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16
os/common/ext/Artery/AT32F4xx/at32f435xx.h
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@ -11450,6 +11450,22 @@ typedef struct
#define RCC_MISC2_AUTO_STEP_EN RCC_MISC2_AUTO_STEP_EN_Msk
#define RCC_MISC2_AUTO_STEP_DIS (0x0)
#define RCC_MISC2_USB_DIV_Pos (12U)
#define RCC_MISC2_USB_DIV_Msk (0x0FU << RCC_MISC2_USB_DIV_Pos)
#define RCC_MISC2_USB_DIV_1_5 (0x00U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div1.5 to usbclk */
#define RCC_MISC2_USB_DIV_1 (0x01U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div1 to usbclk */
#define RCC_MISC2_USB_DIV_2_5 (0x02U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div2.5 to usbclk */
#define RCC_MISC2_USB_DIV_2 (0x03U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div2 to usbclk */
#define RCC_MISC2_USB_DIV_3_5 (0x04U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div3.5 to usbclk */
#define RCC_MISC2_USB_DIV_3 (0x05U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div3 to usbclk */
#define RCC_MISC2_USB_DIV_4_5 (0x06U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div4.5 to usbclk */
#define RCC_MISC2_USB_DIV_4 (0x07U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div4 to usbclk */
#define RCC_MISC2_USB_DIV_5_5 (0x08U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div5.5 to usbclk */
#define RCC_MISC2_USB_DIV_5 (0x09U << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div5 to usbclk */
#define RCC_MISC2_USB_DIV_6_5 (0x0AU << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div6.5 to usbclk */
#define RCC_MISC2_USB_DIV_6 (0x0BU << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div6 to usbclk */
#define RCC_MISC2_USB_DIV_7 (0x0CU << RCC_MISC2_USB_DIV_Pos) /*!< pllclk div7 to usbclk */
/******************************************************************************/
/* */
/* RNG */

5
os/hal/ports/AT32/AT32F4xx/hal_lld.c
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@ -239,6 +239,11 @@ void stm32_clock_init(void) {
/* disable auto step mode */
RCC->MISC2 &= ~RCC_MISC2_AUTO_STEP_EN;
#if STM32_CLOCK48_REQUIRED
RCC->MISC1 = (RCC->MISC1 & (~(STM32_CK48MSEL_MASK | RCC_MISC2_USB_DIV_Msk))) |
(STM32_CK48MSEL | STM32_USBDIV_VALUE);
#endif
#endif
#endif /* STM32_NO_INIT */

46
os/hal/ports/AT32/AT32F4xx/hal_lld.h
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@ -181,17 +181,49 @@
* @brief 48MHz frequency.
*/
#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
#if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLALT
#define STM32_PLL48CLK STM32_PLL48CLK_ALTSRC
#if (STM32_PLLCLKOUT == 48000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_1
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 72000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_1_5
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 96000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_2
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 120000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_2_5
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 144000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_3
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 168000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_3_5
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 192000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_4
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 216000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_4_5
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 240000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_5
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 264000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_5_5
#define STM32_PLL48CLK 48000000
#elif (STM32_PLLCLKOUT == 288000000)
#define STM32_USBDIV_VALUE RCC_MISC2_USB_DIV_6
#define STM32_PLL48CLK 48000000
#else
#error "no divider to get 48000000 USB clock from PLLCLKOUT"
#endif
#elif STM32_CK48MSEL == STM32_CK48MSEL_HICK
#error "HICK clock as USB 48MHz source is not implemented"
//#define STM32_PLL48CLK STM32_PLL48CLK_ALTSRC
#else
#error "invalid source selected for PLL48CLK clock"
#endif
#else /* !STM32_HAS_RCC_CK48MSEL */
#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
#endif /* !STM32_HAS_RCC_CK48MSEL */
#else /* !STM32_CLOCK48_REQUIRED */
#define STM32_PLL48CLK 0
#endif /* STM32_CLOCK48_REQUIRED */

20
os/hal/ports/AT32/AT32F4xx/hal_lld_type1.h
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@ -337,20 +337,10 @@
* @name RCC_DCKCFGR2 register bits definitions
* @{
*/
#define STM32_I2C1SEL_MASK (3 << 22) /**< I2C1SEL mask. */
#define STM32_I2C1SEL_PCLK1 (0 << 22) /**< I2C1 source is APB/PCLK1. */
#define STM32_I2C1SEL_SYSCLK (1 << 22) /**< I2C1 source is SYSCLK. */
#define STM32_I2C1SEL_HSI (2 << 22) /**< I2C1 source is HSI. */
#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */
#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */
#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */
#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */
#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */
#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */
#define STM32_CK48MSEL_PLLALT (1 << 27) /**< Alias. */
#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */
#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */
#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */
@ -366,6 +356,16 @@
#define STM32_LPTIM1SEL_LSE (3 << 30) /**< LPTIM1 source is LSE. */
/** @} */
/**
* @name RCC_MISC1 register bits definitions
* @{
*/
#define STM32_CK48MSEL_MASK (1 << 13) /**< CK48MSEL mask. */
#define STM32_CK48MSEL_PLL (0 << 13) /**< PLL48CLK source is PLL. */
#define STM32_CK48MSEL_HICK (1 << 13) /**< PLL48CLK source is HICK. */
#define STM32_CK48MSEL_PLLALT (1 << 13) /**< Alias. */
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/