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Fixed GPIO port index calculation. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10573 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-09-11 19:36:26 +00:00
parent 67ac09b2f3
commit c3c4b3af58
3 changed files with 6 additions and 6 deletions
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4
os/hal/ports/STM32/LLD/GPIOv1/hal_pal_lld.c
View File

@ -224,7 +224,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = ((uint32_t)port >> 10U) & 0xFU;
portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
AFIO->EXTICR[cridx] = (AFIO->EXTICR[cridx] & crmask) | (portidx << croff);
@ -272,7 +272,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = ((uint32_t)port >> 10U) & 0xFU;
portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
crport = (AFIO->EXTICR[cridx] >> croff) & 0xFU;

4
os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
View File

@ -253,7 +253,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = ((uint32_t)port >> 10U) & 0xFU;
portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
@ -301,7 +301,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = ((uint32_t)port >> 10U) & 0xFU;
portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU;

4
os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
View File

@ -249,7 +249,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = ((uint32_t)port >> 10U) & 0xFU;
portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
@ -297,7 +297,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
portidx = ((uint32_t)port >> 10U) & 0xFU;
portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 10U) & 0xFU;
crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU;