andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Added the L2 management, and an option on cache disable. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11931 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
isiora 2018-04-13 13:54:40 +00:00
parent 47fd49fd55
commit c3d741a761
2 changed files with 57 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
os/common/startup/ARM/devices/SAMA5D2/boot.S
View File

@ -49,15 +49,16 @@ Boot_Handler:
*/ */
ldr r0, =_start ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 mcr p15, 0, r0, c12, c0, 0
/* /*
* Reset SCTLR Settings * Reset SCTLR Settings
*/ */
mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register
#if defined(ARM_RESET_SYS_CTRL)
bic r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache bic r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache bic r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
bic r0, r0, #0x1 // Clear M bit 0 to disable MMU bic r0, r0, #0x1 // Clear M bit 0 to disable MMU
bic r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction bic r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
#endif
bic r0, r0, #(0x1 << 13) // Clear V bit 13 to disable hivecs bic r0, r0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
mcr p15, 0, r0, c1, c0, 0 // Write value back to CP15 System Control register mcr p15, 0, r0, c1, c0, 0 // Write value back to CP15 System Control register
isb isb

70
os/common/startup/ARM/devices/SAMA5D2/mmu.c
View File

@ -31,6 +31,7 @@
#include "mmu.h" #include "mmu.h"
#include "armparams.h" #include "armparams.h"
#include "mcuconf.h"
#include "ARMCA5.h" #include "ARMCA5.h"
#if defined(__GNUC__) || defined(__DOXYGEN__) #if defined(__GNUC__) || defined(__DOXYGEN__)
#include "cmsis_gcc.h" #include "cmsis_gcc.h"
@ -39,6 +40,14 @@
#endif #endif
#include "ccportab.h" #include "ccportab.h"
#if !defined(SAMA_L2CC_ASSUME_ENABLED)
#define SAMA_L2CC_ASSUME_ENABLED 0
#endif
#if !defined(SAMA_L2CC_ENABLE)
#define SAMA_L2CC_ENABLE 0
#endif
/*===========================================================================*/ /*===========================================================================*/
/* Module local definitions. */ /* Module local definitions. */
/*===========================================================================*/ /*===========================================================================*/
@ -96,13 +105,31 @@ static uint32_t mmuTable[4096] CC_ALIGN(16384);
void __core_init(void) { void __core_init(void) {
uint32_t pm; uint32_t pm;
/* #if ARM_SUPPORTS_L2CC
* Invalidate L1 D Cache if it was disabled #if !SAMA_L2CC_ASSUME_ENABLED
*/
pm = __get_SCTLR(); /* Flush and disable an enabled L2 Cache
if ((pm & SCTLR_C_Msk) == 0) { invalidate a disabled L2 Cache.*/
__L1C_CleanInvalidateCache(DCISW_INVALIDATE); if ((L2C_310->CONTROL & L2CC_CR_L2CEN) != 0) {
L2C_Disable();
L2C_CleanInvAllByWay();
} }
#endif
#endif
/* Flush and disable an enabled L1 D Cache
Invalidate a disabled L1 D Cache.*/
pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk)) {
L1C_CleanInvalidateCache(DCISW_CLEAN);
L1C_DisableCaches();
}
/* Disable the MMU and invalidate TLB.*/
MMU_Disable();
L1C_InvalidateBTAC();
MMU_InvalidateTLB();
/* /*
* Default, undefined regions * Default, undefined regions
*/ */
@ -271,6 +298,7 @@ void __core_init(void) {
TTE_SECT_RW_ACCESS | TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) | TTE_SECT_DOM(0x00) |
TTE_SECT_S | TTE_TYPE_SECT; TTE_SECT_S | TTE_TYPE_SECT;
/* /*
* SDMMC0/1 regions * SDMMC0/1 regions
* *
@ -282,7 +310,7 @@ void __core_init(void) {
TTE_SECT_RW_ACCESS | TTE_SECT_RW_ACCESS |
TTE_SECT_DOM(0x00) | TTE_SECT_DOM(0x00) |
TTE_SECT_EXE_NEVER | TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT; TTE_TYPE_SECT;
/* /*
* NFC regions * NFC regions
* *
@ -331,40 +359,37 @@ void __core_init(void) {
TTE_SECT_DOM(0x00) | TTE_SECT_DOM(0x00) |
TTE_SECT_EXE_NEVER | TTE_SECT_EXE_NEVER |
TTE_SECT_S | TTE_TYPE_SECT; TTE_SECT_S | TTE_TYPE_SECT;
/*
* Invalidate TLB and L1 I cache /* Invalidate TLB and L1 I cache
* Enable caches and MMU Enable caches and MMU.*/
*/
MMU_InvalidateTLB(); MMU_InvalidateTLB();
__set_TTBR0((uint32_t)mmuTable|0x5B); __set_TTBR0((uint32_t)mmuTable|0x5B);
__set_DACR(0x00000001); __set_DACR(0x00000001);
__DSB(); __DSB();
__ISB(); __ISB();
/* /* L1 I cache invalidate and enable.*/
* L1 I cache invalidate and enable
*/
pm = __get_SCTLR(); pm = __get_SCTLR();
if ((pm & SCTLR_I_Msk) == 0) { if ((pm & SCTLR_I_Msk) == 0) {
__set_ICIALLU(0); __set_ICIALLU(0);
__set_SCTLR(pm | SCTLR_I_Msk); __set_SCTLR(pm | SCTLR_I_Msk);
} }
/*
* MMU enable /* MMU enable.*/
*/
pm = __get_SCTLR(); pm = __get_SCTLR();
if ((pm & SCTLR_M_Msk) == 0) if ((pm & SCTLR_M_Msk) == 0)
__set_SCTLR(pm | SCTLR_M_Msk); __set_SCTLR(pm | SCTLR_M_Msk);
/*
* L1 D cache enable /* L1 D cache enable.*/
*/
pm = __get_SCTLR(); pm = __get_SCTLR();
if ((pm & SCTLR_C_Msk) == 0) { if ((pm & SCTLR_C_Msk) == 0) {
L1C_CleanInvalidateCache(DCISW_INVALIDATE);
__set_SCTLR(pm | SCTLR_C_Msk); __set_SCTLR(pm | SCTLR_C_Msk);
} }
#if defined(ARM_ENABLE_L2CC) #if ARM_SUPPORTS_L2CC
#if ARM_ENABLE_L2CC #if !(SAMA_L2CC_ASSUME_ENABLED) && (SAMA_L2CC_ENABLE)
if (!(L2C_310->CONTROL & L2CC_CR_L2CEN)) {
/* High SRAM to L2CC.*/ /* High SRAM to L2CC.*/
SFR->SFR_L2CC_HRAMC = 0x1; SFR->SFR_L2CC_HRAMC = 0x1;
@ -373,6 +398,7 @@ void __core_init(void) {
L2C_Enable(); L2C_Enable();
__DSB(); __DSB();
__ISB(); __ISB();
}
#endif #endif
#endif #endif
} }