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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1865 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-04-13 17:29:54 +00:00
parent 676bb610cb
commit c406099319
4 changed files with 62 additions and 64 deletions
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56
os/ports/GCC/ARMCMx/chcore_v6m.c
View File

@ -64,13 +64,13 @@ __attribute__((naked))
#endif #endif
void _port_switch_from_irq(void) { void _port_switch_from_irq(void) {
/* Note, saves r4 to make space for the PC.*/ /* Note, saves r4 to make space for the PC.*/
asm volatile ("push {r0, r1, r2, r3, r4} \n\t" \ asm volatile ("push {r0, r1, r2, r3, r4} \n\t"
"mrs r0, APSR \n\t" \ "mrs r0, APSR \n\t"
"mov r1, r12 \n\t" \ "mov r1, r12 \n\t"
"push {r0, r1, lr} \n\t" \ "push {r0, r1, lr} \n\t"
"ldr r0, =_port_saved_pc \n\t" \ "ldr r0, =_port_saved_pc \n\t"
"ldr r0, [r0] \n\t" \ "ldr r0, [r0] \n\t"
"add r0, r0, #1 \n\t" \ "add r0, r0, #1 \n\t"
"str r0, [sp, #28]"); "str r0, [sp, #28]");
chSchDoRescheduleI(); chSchDoRescheduleI();
@ -80,30 +80,30 @@ void _port_switch_from_irq(void) {
possibility that the stack is filled by continuous and saturating possibility that the stack is filled by continuous and saturating
interrupts that would not allow that last words to be pulled out of interrupts that would not allow that last words to be pulled out of
the stack.*/ the stack.*/
asm volatile ("pop {r0, r1, r2} \n\t" \ asm volatile ("pop {r0, r1, r2} \n\t"
"mov r12, r1 \n\t" \ "mov r12, r1 \n\t"
"msr APSR, r0 \n\t" \ "msr APSR, r0 \n\t"
"mov lr, r2 \n\t" \ "mov lr, r2 \n\t"
"cpsie i \n\t" \ "cpsie i \n\t"
"pop {r0, r1, r2, r3, pc}"); "pop {r0, r1, r2, r3, pc}");
} }
#define PUSH_CONTEXT(sp) { \ #define PUSH_CONTEXT(sp) { \
asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \ asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \
"mov r4, r8 \n\t" \ "mov r4, r8 \n\t" \
"mov r5, r9 \n\t" \ "mov r5, r9 \n\t" \
"mov r6, r10 \n\t" \ "mov r6, r10 \n\t" \
"mov r7, r11 \n\t" \ "mov r7, r11 \n\t" \
"push {r4, r5, r6, r7}"); \ "push {r4, r5, r6, r7}"); \
} }
#define POP_CONTEXT(sp) { \ #define POP_CONTEXT(sp) { \
asm volatile ("pop {r4, r5, r6, r7} \n\t" \ asm volatile ("pop {r4, r5, r6, r7} \n\t" \
"mov r8, r4 \n\t" \ "mov r8, r4 \n\t" \
"mov r9, r5 \n\t" \ "mov r9, r5 \n\t" \
"mov r10, r6 \n\t" \ "mov r10, r6 \n\t" \
"mov r11, r7 \n\t" \ "mov r11, r7 \n\t" \
"pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \ "pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \
} }
/** /**
@ -145,8 +145,8 @@ void port_switch(Thread *ntp, Thread *otp) {
void _port_thread_start(void) { void _port_thread_start(void) {
port_unlock(); port_unlock();
asm volatile ("mov r0, r5 \n\t" \ asm volatile ("mov r0, r5 \n\t"
"blx r4 \n\t" \ "blx r4 \n\t"
"bl chThdExit"); "bl chThdExit");
} }

8
os/ports/GCC/ARMCMx/chcore_v6m.h
View File

@ -129,9 +129,9 @@ struct intctx {
* enabled to invoke system APIs. * enabled to invoke system APIs.
*/ */
#define PORT_IRQ_PROLOGUE() { \ #define PORT_IRQ_PROLOGUE() { \
chSysLockFromIsr(); \ port_lock_from_isr(); \
_port_irq_nesting++; \ _port_irq_nesting++; \
chSysUnlockFromIsr(); \ port_unlock_from_isr(); \
} }
/** /**
@ -140,7 +140,7 @@ struct intctx {
* enabled to invoke system APIs. * enabled to invoke system APIs.
*/ */
#define PORT_IRQ_EPILOGUE() { \ #define PORT_IRQ_EPILOGUE() { \
chSysLockFromIsr(); \ port_lock_from_isr(); \
if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) { \ if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) { \
register struct cmxctx *ctxp; \ register struct cmxctx *ctxp; \
\ \
@ -149,7 +149,7 @@ struct intctx {
ctxp->pc = _port_switch_from_irq; \ ctxp->pc = _port_switch_from_irq; \
return; \ return; \
} \ } \
chSysUnlockFromIsr(); \ port_unlock_from_isr(); \
} }
/** /**

20
os/ports/GCC/ARMCMx/chcore_v7m_test.c
View File

@ -63,7 +63,7 @@ CH_IRQ_HANDLER(SysTickVector) {
void SVCallVector(void) { void SVCallVector(void) {
register struct extctx *ctxp; register struct extctx *ctxp;
/* Discardig the current exception context and positioning the stack to /* Discarding the current exception context and positioning the stack to
point to the real one.*/ point to the real one.*/
asm volatile ("mrs %0, PSP" : "=r" (ctxp) : ); asm volatile ("mrs %0, PSP" : "=r" (ctxp) : );
ctxp++; ctxp++;
@ -94,9 +94,7 @@ void _port_irq_epilogue(void) {
/** /**
* @brief Post-IRQ switch code. * @brief Post-IRQ switch code.
* @details On entry the stack and the registers are restored by the exception * @details Exception handlers return here for context switching.
* return, the PC value is stored in @p _port_saved_pc, the interrupts
* are disabled.
*/ */
#if !defined(__DOXYGEN__) #if !defined(__DOXYGEN__)
__attribute__((naked)) __attribute__((naked))
@ -107,13 +105,13 @@ void _port_switch_from_isr(void) {
asm volatile ("svc #0"); asm volatile ("svc #0");
} }
#define PUSH_CONTEXT(sp) { \ #define PUSH_CONTEXT(sp) { \
asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \ asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \
} }
#define POP_CONTEXT(sp) { \ #define POP_CONTEXT(sp) { \
asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \ asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
: : "r" (sp)); \ : : "r" (sp)); \
} }
/** /**
@ -155,8 +153,8 @@ void port_switch(Thread *ntp, Thread *otp) {
void _port_thread_start(void) { void _port_thread_start(void) {
port_unlock(); port_unlock();
asm volatile ("mov r0, r5 \n\t" \ asm volatile ("mov r0, r5 \n\t"
"blx r4 \n\t" \ "blx r4 \n\t"
"bl chThdExit"); "bl chThdExit");
} }

42
os/ports/GCC/ARMCMx/chcore_v7m_test.h
View File

@ -150,13 +150,13 @@ struct intctx {
* @note In this port this it raises the base priority to kernel level. * @note In this port this it raises the base priority to kernel level.
*/ */
#if CH_OPTIMIZE_SPEED #if CH_OPTIMIZE_SPEED
#define port_lock() { \ #define port_lock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
} }
#else #else
#define port_lock() { \ #define port_lock() { \
asm volatile ("bl _port_lock" : : : "r3", "lr"); \ asm volatile ("bl _port_lock" : : : "r3", "lr"); \
} }
#endif #endif
@ -164,16 +164,16 @@ struct intctx {
* @brief Kernel-unlock action. * @brief Kernel-unlock action.
* @details Usually this function just disables interrupts but may perform * @details Usually this function just disables interrupts but may perform
* more actions. * more actions.
* @note In this port this it lowers the base priority to kernel level. * @note In this port this it lowers the base priority to user level.
*/ */
#if CH_OPTIMIZE_SPEED #if CH_OPTIMIZE_SPEED
#define port_unlock() { \ #define port_unlock() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
} }
#else #else
#define port_unlock() { \ #define port_unlock() { \
asm volatile ("bl _port_unlock" : : : "r3", "lr"); \ asm volatile ("bl _port_unlock" : : : "r3", "lr"); \
} }
#endif #endif
@ -208,20 +208,20 @@ struct intctx {
* @note Interrupt sources above kernel level remains enabled. * @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level. * @note In this port it raises/lowers the base priority to kernel level.
*/ */
#define port_suspend() { \ #define port_suspend() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0 \n\t" \ asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \ "cpsie i" : : "r" (tmp)); \
} }
/** /**
* @brief Enables all the interrupt sources. * @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level. * @note In this port it lowers the base priority to user level.
*/ */
#define port_enable() { \ #define port_enable() { \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
asm volatile ("msr BASEPRI, %0 \n\t" \ asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \ "cpsie i" : : "r" (tmp)); \
} }
/** /**
@ -233,8 +233,8 @@ struct intctx {
* @note Implemented as an inlined @p WFI instruction. * @note Implemented as an inlined @p WFI instruction.
*/ */
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) #if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
#define port_wait_for_interrupt() { \ #define port_wait_for_interrupt() { \
asm volatile ("wfi"); \ asm volatile ("wfi"); \
} }
#else #else
#define port_wait_for_interrupt() #define port_wait_for_interrupt()